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A number of companies use Verific HDL source code components for their HDL language needs. Some responses to their use of Verific Design Automation HDL Software Components: |
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Rocketick |
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"Verific enabled us to kick-start our development and focus on our
core technology early on. It is a pleasure to work
with Verific's software and the team behind it.""
Uri Tal, chief executive officer,
www.rocketick.com |
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Forte Design Systems |
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"Verific's reputation for solid product offerings and strong customer
support are well earned. We've been impressed with Verific's
willingness to work with us through the transition and its commitment
to making CellMath Designer a 'must-have' datapath synthesis tool."
Sean Dart, chief executive officer,
www.forteds.com |
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Parallel Engines |
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"Verific is a company with first-rate products and excellent
support. Parallel Engines will utilize Verific in its upcoming IP/RT
Level, web-enabled floorplanner, aiding designers in physical
semiconductor-IP integration."
George Janac, chief executive officer,
www.parallelengines.com |
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Vennsa |
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"Verific's software is robust and dependable, which allows our
engineers to focus on our core expertise, automated debugging, On the
business side, Verific has been an extremely supportive business
partner from our university spin-off days to today."
Dr. Sean Safarpour, vice president of engineering,
www.vennsa.com |
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Oasys |
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"Integrating Verific's software with RealTime Designer had been a part
of our product planning and development from the beginning because of
its superior quality. Verific's customer support group has a
reputation for outstanding service and each member lived up to that
reputation."
Paul van Besouw, chief executive officer,
www.oasys-ds.com |
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Tiempo |
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"Verific's software serves as an essential component of our
product development plan and gave us an immediate head start on
worldwide product deployment,"
Serge Maginot, chief executive officer,
www.tiempo-ic.com |
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Xilinx |
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"Verific has been an exceptional technology partner with a team whose
expertise we value. Verific has delivered high-quality RTL front-end
software to help us differentiate ISE Design Suite's superior
capabilities and benefits and allow us to focus on our core
competencies."
Dan Gibbons, senior director for Interactive Design Tools,
www.xilinx.com |
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Real Intent |
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"Real Intent knows first hand why Verific has had long-term success.
We have had a winning collaboration with Verific over a long period of
time and knew where to go when we needed to upgrade to SystemVerilog.
"
Carol Hallett, vice president of World Wide Sales and Marketing
www.realintent.com |
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Elastix |
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"I am pleased with Verific's software. Using the netlist parser and data structures enabled us to kick-start our development and focus on our core technology early on. It is well structured, easy to understand and efficient."
Dr. Emre Tuncer, vice president of engineering
www.elastix-corp.com
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Achronix Semiconductor |
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"Building ACE leveraging Verific's netlist parser and datastructures saved us a significant amount of time and effort. Their industry-proven software and customer support enabled us to focus on developing our own key software capabilities."
Raymond Nijssen, chief software architect,
www.achronix.com
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iRoC Technologies |
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"Soft Errors are affecting more electronic systems in advanced technologies
than ever. iRoC Technologies provides design solutions and EDA tools to
measure, analyze and fix the problem of soft errors in modern integrated
circuits. And when iRoC needed support for Verilog RTL, we selected Verific
Design Automation as our partner."
Eric Dupont, CEO,
www.iroctech.com
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Concise Logic |
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"I've had the opportunity to work with the Verific R&D team on two prior
projects involving RTL parsing, and was pleasantly surprised when I found
out that they now also ship a netlist-only parser, together with their
netlist database. Using Verific's netlist parser helped us to get
development of our Concise Optimization Tool quickly off the ground, and has
us fully prepared for future expansion into RTL support."
Mike Bohm, chief technology officer,
www.conciselogic.net
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Fenix |
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"Our core competency is in the analysis of layout and SPICE views, not the
parsing of Verilog and VHDL models. Rather than developing this expertise
on our own, we chose to license the parsers from Verific. It was an
excellent decision."
Chris Strolenberg, chief technology officer
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Actel |
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"Through a tight integration of Verific's front-end software with
Libero, designers are able to create and automatically abstract block-based
system designs into synthesis-ready VHDL or Verilog components. Verific's
goal to provide quality products and exceptional support is perfectly in
tune with our way of thinking that keeps us innovating to ease design
challenges."
Ken Joyner, director of engineering,
www.actel.com
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Certess (acquired by Springsoft) |
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"Certitude has already been implemented by 50 design teams worldwide and
many have given us high marks for our HDL capabilities. We credit Verific
for quality products and highly professional support and service, making it
a vendor we've enjoyed as a business partner."
Michel Courtoy, chief executive officer
www.certess.com
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CLKDA |
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"With next-generation tools such as Amber, only the best-in-class software
like those from Verific will help us meet complex design challenges. We
found that the Verific HDL Component Software had the capacity and
performance our customers require for their designs."
Isadore Katz, president and CEO
www.clkda.com
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DeFacTo |
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"We were immediately impressed with the range of Verific's customers,
many of whom are our EDA partners. It became clear early in our relationship
that Verific's products and support team are equally impressive. It's been
an extremely rewarding joint technical development effort."
Philippe Duchene, vice president of engineering
www.defactotech.com
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S2C |
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"Verific is a best-in-class provider of HDL Component Software. The
ability to seamlessly incorporate Verific's software into our design flow is
a key reason we can offer powerful and stable FPGA-based ESL tools to our
customers"
Mon-Ren Chene, chief technology officer
www.s2cinc.com |
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GateRocket |
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"We are offering the best solution to address an acute debugging and
verification problem and Verific is the only EDA tool provider that can meet
our rigorous requirements. I've worked with Verific and know the team to be
highly competent and customer focused.. It was an easy choice for us."
Dave Orecchio, president and CEO
www.gaterocket.com |
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Denali Software |
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"We are happy working with Verific, as utilizing SystemVerilog
represents a cornerstone of our configurable IP strategy. Incorporating its tool into our flows saves us valuable time and resources. We find Verific's customer support and service to be exceptional."
Brian Gardner, vice president of IP products
www.denali.com |
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Lattice Semiconductor |
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"Verific's HDL Component Software is a comprehensive tool that Lattice has leveraged in its development of our HDL Explorer tool, a significant
new capability that enables FPGA designers to more effectively and quickly complete their designs."
Chris Fanning, corporate vice president of software and IP solutions
www.latticesemi.com |
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ArchPro (Acquired by Synopsys) |
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"When looking for software to serve as a front end to EDA design tools, Verific is the first name that comes up every time. And, for good reason --
its products are easy to integrate and offer good value. With Verific
serving as MVSIM's front end, users can be assured quality and high
performance verification."
Pratap Reddy, CEO and Chairman
www.archpro.com |
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Magma Design Automation |
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"Quartz Formal, our state-of-the-art equivalence checker,
required a language front-end that would match its quality
and performance. We found all that and more in Verific's
Verilog, VHDL, and SystemVerilog parsers / elaborators.
Their software is great and matched with excellent support."
Rajeev Madhavan, Chairman & CEO
www.magma-da.com |
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Liga Systems |
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"Liga Systems turned to Verific for its industry-leading HDL Component Software because it helped us save invaluable time and effort. Our team has
found the Verific code to be very clear, providing good value as we extend
its use for simulation. Using Verific's front-end technology, we were able
to bring up a complex Verilog RTL compiler quickly, reducing our time to market, while achieving a high quality product."
Henry Verheyen, Chief Executive Officer |
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Concept Engineering |
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"We relied on Verific to help us meet our product plan to link code with
interactive graphic fragments. This partnership is effective and one that we
see lasting for a long time."
Gerhard Angst, president and CEO
www.concept.de |
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Arithmatica (acquired by Forte Design Systems) |
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"Verific's best-in-class component software solutions allow us to offer
Verilog support to our customers, which we would not have been able to do on
our own. Verific is a company dedicated to excellence in customer support,
top-quality HDL software and serves a formerly underserved EDA component
software market segment."
Dr. Tony Curzon Price, Chief Executive Officer
www.arithmatica.com |
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Tenison |
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"We are committed to increasing our customers' profitability through software solutions that accelerate system design. Verific's HDL Component
Software was instrumental in us being able to more quickly support our
customer's needs."
Dr. Jeremy Bennett, Chief Technology Officer
www.tenison.com |
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ProDesign (ChipIt business unit acquired by Synopsys) |
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"We looked no further than Verific when we sought out a front-end development partner. With the integration of Verific's HDL Component Software we could expand the capabilities of our CHIPit systems, especially for the transaction-based verification Verific offers an exceptional package of production-proven, quality software, along with excellent support and service"
Gunnar Scholl, director of Marketing and Business Development
www.prodesign-europe.com |
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EVE |
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"Verific's HDL Component Software has become the industry standard and for good reason. The software is first rate and the support is outstanding. Verific is an excellent development partner."
Dr. Luc Burgun, CEO and president
www.eve-team.com |
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Renesas |
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"Verific's commitment to customer support by the R&D team is commendable. Their dedication ensured that we got the features we needed, and made a
significant impact with us."
Keiichi Suzuki, senior engineer
www.renesas.com |
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Jasper |
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"Without Verific, an internal SystemVerilog development effort would have
been a long, difficult process. Verific's language solutions, combined with
Jasper's leading assertion synthesis technology, have contributed to our
leading position in formal verification for standard assertion and design
languages. Verific is a superior business partner and we commend them for
being responsive and committed to the current market success of JasperGold
Verification System."
dr. Claudionor Coelho, vice president of engineering
www.jasper-da.com |
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Altium |
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"We felt that it was crucial to provide strong support for
Verilog within Nexar. Rather than developing our own
parsers and analyzers, we found that Verific's well-engineered
and reliable HDL Component Software was the right fit for
our needs. We can focus on other aspects of Nexar, and
strengthen its position as the universal design system of choice
for FPGA-based systems development."
Nick Martin, founder and joint CEO
www.altium.com |
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Calypto |
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"The decision to work with Verific was an easy one for us
because its HDL Component Software is the standard front-end
source code. Verific's team is exceptional and its support is
unmatched. Our experience working with Verific has been excellent."
Gagan Hasteer, vice president of engineering
www.calypto.com |
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Stelar Tools, Inc. (Acquired by Lattice Semiconductor) |
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"The runtime and memory footprint is vastly superior to all other parsers
that we evaluated. Support has been superb as well. No issue took longer
then three days to have a workaround, and all enhancement requests were
granted."
Scott Bloom, vice president of engineering
www.stelartools.com |
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DAFCA, Inc. |
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"Verific's technology is enabling us to develop our product with full
multi-language support and proven Verilog and VHDL language compatibility.
Working with the Verific software team, we have enjoyed a productive
development relationship and appreciate their excellent responsiveness and
support."
Dave Miller, vice president of engineering
www.dafca.com |
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Altera |
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"When we were developing Quartus II, we realized we also needed a best-in-class HDL solution for our FPGAs and CPLDs. Rather than developing this ourselves, we chose the industry-proven VHDL and Verilog HDL solution from Verific. They have not disappointed us. Integration was painless and support continues to be excellent."
Misha Burich, Senior VP Software Engineering
www.altera.com |
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Sequence (acquired by Apache Design Solutions) |
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"We replaced our existing Verilog and VHDL parsers and elaborator with
Verific's solution. This solution has resulted in significant improvements
in the performance and accuracy of the language front-end to Powertheater.
Our partnership with Verific will be of great benefit to all our PowerTheater
customers."
Tom Miller, VP of Engineering
www.sequencedesign.com |
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NEC |
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"NEC spends significant resources in advancing state-of-the-art EDA research to maintain its leadership position in SOC design. Using Verifics software fits right into our best-in-class strategy. We very much like that Verific provides us with source code. In addition, support and training so far have been excellent."
Dr. Masao Fukuma, vice president and general manager of NEC System Devices Research Laboratories
http://www.nec.co.jp/rd/Eng/ |
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Infineon |
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"2.5 hours after receiving the code from Infineon, we were fully up and running, including invoking the Verific makefile from our own compilation flow. We had a seamless migration from using the Verific evaluation binaries to using the real
source code. We, and Infineon, are very happy with the quality of your deliverables.
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Peter Jensen, Sysosil Consulting / Infineon
www.syosil.dk |
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Wolfson |
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"Verific's tool does exactly what we need to improve our design flow for mixed-signal chips. As a result, Verific has become an important design tool partner, helping us to construct an integrated tool set for mixed-signal design.
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Jim Reid, Chief Technical Officer
www.wolfsonmicro.com |
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Tharas (acquired by EVE) |
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"As a performance leader in Hardware Acceleration, Tharas was pushed by its customers to add VHDL support. To accelerate time to market, Tharas decided to look at 3rd party VHDL front-ends. Ater extensive evaluations, we chose Verific as our VHDL front-end. The quality and accessibility of the source code makes it far superior over its competitors. Verific has provided outstanding support, and has proved to be a great R&D partner."
Ramesh Narayanaswamy, VP engineering
www.eve-team.com |
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NXP Semiconductor |
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"So far, we have used Verific's Verilog and VHDL front-ends for a DFT rule checker and a Logic Equivalence checker. Both products are in production use with our internal customers. We, as well as our end-users, are very impressed with the language support, overall quality and speed of the software. It would have taken us at least 2 years of development and debug time to get to the same results. With Verific's language front-ends our development team can now focus on its core competency and the actual design problems of our customers."
Mario Konijnenburg, Research Scientist and Software Engineer
www.nxp.com |
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Prover Technology |
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"We chose Verific Design Automation as our Verilog and VHDL front-end
provider, since they offered the best solution in terms of maturity,
language coverage and source code access. Verific has been a great company to work with, they offer excellent technical support, and they have a strong product
road map going forward."
Arne Boralv, CTO
www.prover.com |
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HDL Works |
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"Our products require push-button import of legacy Verilog and VHDL designs with syntax checking. Rather than developing our own parsers and analysers, we chose to purchase software from Verific Design Automation for reasons of product quality and time to market. We found the software well architected and very reliable and as a result, we easily saved 12 months of engineering development time."
Willem Gruter, founder and president
www.hdlworks.com |
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Theseus Logic |
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"Deploying Verific's source code saved us at least 6 months of development time right from the start of our EDA project. In addition, the quality and maturity of the code were such that we spent little to no time on debug or unanticipated improvements. Using Verific's software drastically accelerated time-to-market for our product NCL-SHELL, which is used in the design of asynchronous ICs."
Oriol Riog, Manager Software Development |