To complement its HDL language readers, Verific also provides SDF, EDIF, and Liberty (Synopsys .lib format) readers that interface directly into the common database.

EDIF reader

• Supports EDIF version 2 0 0

SDF reader

• Supports SDF version 3.0 (May 1995), IEEE 1497-2001

Liberty reader

• Supports full logical (.lib) set of constructs including SPDM and both syntax and common semantic checks

Database

The database stores netlist, library, and timing data in a language-independent simple model. The database is common to all readers and has an efficient and clean API for easy integration into your existing database or object model.

• Very memory efficient. Average overall memory usage just 300 bytes/gate.

• Fast database traversal due to optimal container/pointer organization between database objects.

• Full hierarchy support, with grouping/ungrouping, etc.

• Full support for any number of libraries, and no restrictions on library interaction (instantiations across different libraries).

• Support for buses.

• Compact storage of line/file origination info from RTL Readers.

• Simple and clean data model and Procedural Interface for easy integration with your existing database.

SystemVerilog - Verilog - Verilog Netlist Only - VHDL - PSL - EDIF - Liberty - SDF