Verific Design Automation (Verilog/VHDL frontends/compilers/analyzers/elaborators)

Verilog Netlist Only Parser

Verific's Verilog Netlist Only Parser reads a Verilog structural netlist directly into Verific's hierarchical database. It does not create any intermediate parse tree or other persistent data structure. The Verilog Netlist Only Parser can be of great use to EDA applications that do not (yet) require RTL support. As with all Verific's software, the product is shipped as C++ source code and backed with a rigorous support and maintenance program.

Highlights

Parses structural subset of Verilog-2001 (IEEE-1364 standard).

Support for Verilog and Liberty libraries.

Includes Verific's hierarchical database.

Also parses EDIF 2 0 0

Complete line / file information.

Fully compatible with Verific's RTL parsers / elaborators.

Netlist Database

Average memory usage approximately 300 bytes / instance
Full hierarchy support, with grouping/ungrouping, etc.
Find, insert, remove, and change cells, ports, and wires.
Full support for any number of libraries, and no restrictions on library interaction (instantiations across different libraries).
Maintains all attribute information
Support for busses.
Compact storage of line and file origination.
Comprehensive error handler.
Simple and clean data model and Procedural Interface

SystemVerilog - Verilog - Verilog Netlist Only - VHDL - PSL - EDIF - Liberty - SDF