Verific's Parser Platform
Verific Design Automation software offers a number of packages, all written in platform independent C++. These include the following:
- SystemVerilog IEEE 1800 – 2005 / 2009 parser, analyzer, and elaborator
- VHDL IEEE 1076 – 1993 / 2008 parser, analyzer, static and RTL elaborator.
- Verilog IEEE 1364-1995/2001 parser, analyzer, static and RTL elaborator
- Verilog-AMS parser and analyzer
- PSL IEEE 1850 parser and analyzer for VHDL and Verilog
- Automatic FSM/RAM extraction from RTL
- EDIF 2.0 Reader
- SDF Reader
- Liberty Reader
- Hierarchical, Technology Independent Database
HDL Front Ends
SystemVerilog, VHDL and Verilog 2001 are parsed and processed in two steps, analysis and elaboration. Since the readers create and use a common database, mixed VHDL and Verilog compilation is fully supported.
Analysis creates parse-trees and performs type-inferencing to resolve the meaning of identifiers. The Parser/Analyzer supports the entire SystemVerilog IEEE 1800, VHDL IEEE 1076-1993, and Verilog IEEE 1364-1995/2001 languages, without any restrictions. The resulting parse tree comes with an extensive API.
Elaboration supports both static elaboration and RTL elaboration. Static elaboration elaborates the entire language, and specifically binds instances to modules, resolves library references, propagates defparams, unrolls generate statements, and checks all hierarchical names and function/task calls. The result after static elaboration is an elaborated parse tree, appropriate for simulation like applications. RTL elaboration is limited to the synthesizable subset of the language. In addition to the static elaboration tasks for this subset, it generates sequential networks through flipflop and latch detection, and Boolean extraction. The result after RTL elaboration is a netlist, appropriate to applications such as logic synthesis and formal verification.
For more information on our SystemVerilog, VHDL, Verilog, and PSL parsers, as well as other HDL software components, follow the hyperlinks below:
SystemVerilog - Verilog - VHDL - PSL - EDIF - Liberty - SDF