Verific’s UPF parser supports the entire IEEE 1801 standard (UPF 1.0, 2.0, 2.1, 3.0) and creates a UPF data model. It performs syntax and semantic checking.
The UPF Parser is an integral component of Verific’s Parser Platform and interacts seamlessly with Verific’s standard SystemVerilog and VHDL parsers. It queries parse trees or netlists where applicable and can be queried from Verific’s SystemVerilog or VHDL parse trees, as well as its netlist database. Complete file / line / column information on UPF descriptions is maintained and Verific’s comprehensive error handler is included.
Verific’s UPF parser is also easily integrated with external (non-Verific) data structures.