PSL Parser

Verific’s PSL (Property Specification Language) parser is an add-on to the regular VHDL and Verilog parsers. It supports the entire PSL specification language and synthesizes it into PSL boxes in the netlist, available to the end-application.

Highlights:

• PSL 1.0 support



• Support for in-line assertions



• Support for external assertions



• 100% language coverage



• Assertions are synthesized into PSL boxes represented in the netlist

Testimonial

“The PSL/Sugar Consortium is pleased that Verific is offering assertion-based specifications within its HDL component software packages. This allows EDA companies to swiftly introduce native PSL/Sugar support in their verification tools. We were waiting for something like this to happen.”

- Harry Foster, formal verification technical committee chair, Accelera.

SystemVerilog - Verilog - Verilog Netlist Only - VHDL - PSL - EDIF - Liberty - SDF