Verific Design Automation (Verilog/VHDL frontends/compilers/analyzers/elaborators)

SystemVerilog Parser

Verific’s SystemVerilog parser is built on top of the existing Verilog 95/2001 parser, and the entire Verilog 95 and 2001 languages are still parsed as normal, even with SystemVerilog language enabled. The parser supports static elaboration as well RTL elaboration, and is integrated with a language-independent database common to all parsers.

Highlights

Supports full SystemVerilog IEEE 1800, including assertions (SVA) and test benches
Includes support for Verilog 2001 and Verilog 1995
100% language coverage for analysis
Static and RTL elaboration modules
Preservation of line/file/column origination into database.

Database

The database stores RTL and netlist designs in a language-independent simple model. The database is common to all readers and has an efficient and clean API for easy integration into your existing database or object model.

Very memory efficient. Average overall memory usage just 300 bytes/gate.

Fast database traversal due to optimal container/pointer organization between database objects.

Full hierarchy support, with grouping/ungrouping, etc.

Full support for any number of libraries, and no restrictions on library interaction (instantiations across different libraries).

Support for buses.

Compact storage of line/file origination info from RTL Readers.

Simple and clean data model and Procedural Interface for easy integration with your existing database.

SystemVerilog - Verilog - Verilog Netlist Only - VHDL - PSL - EDIF - Liberty - SDF