To view some of the EDA products you can find us in, click here
“Selecting Verific’s parser and elaborator was a strategic decision that will ensure the Efinity IDE has a high-quality front end. Equally important, we save years of development time.”
-Sammy Cheung, chief executive officer
“Based on my prior experience at Carbon Design Systems, I knew Verific’s front-end products were the best choice for Baum. In fact, Verific clearly qualifies for the Semiconductor Industry’s Top Vendor for Support and Service award.”
-Andy Ladd, chief executive officer.
“The completeness of Verific’s Parser Platform and support infrastructure enabled us to fully concentrate our efforts on our expertise, functional safety. We were able to leave concerns about quality parsers to Verific and develop our tools serving the automotive, medical, industrial and enterprise markets quickly and cost effectively.”
-Sanjay Pillay, chief executive officer.
“Verific has been an exceptional technology partner with a team whose expertise we value. Verific has delivered high-quality RTL front-end software to help us differentiate ISE Design Suite’s superior capabilities and benefits and allow us to focus on our core competencies.”
– Dan Gibbons, Vice President, FPGA Software, Xilinx.
“Verific continues to provide the best SystemVerilog and VHDL parsers in the EDA industry. We have had a long and valued partnership with Verific and it was reinforced by its strong support as we begin using SystemVerilog.
– Mon-Ren Chene, chief technology officer.
“We have never worked with a vendor that was so responsive to all our needs and delivered so promptly with such high quality.”
– Leon Stok, Vice President, Electronic Design Automation.
“We were able to save countless hours by partnering with Verific. We used its thoroughly tested parsers and were able to focus on developing Prospect, our software tool that identifies security vulnerabilities in hardware designs.”
– Jason Oberg, chief executive officer.
“Verific’s reputation is well known throughout the semiconductor and EDA industry, and is well deserved. Its parsers easily integrated with our functional verification platform, saving us time and resources that could be deployed elsewhere.”
– Hagai Arbel, chief executive officer.
“Verific has been an outstanding partner. Its software is high quality, as is the support and service. I can’t think of a more responsive and supportive EDA vendor.”
– Uri Tal, chief executive officer (acquired by Cadence).
“Verific was an easy choice for us. Its reputation for high-quality software and superior support and service is unmatched.”
– Hayder Mrabet, chief executive officer (acquired by Mentor Graphics).
“Verific has proven to be the best EDA partner and supplier any company can hope to work with, offering first-rate technology and outstanding support.”
– Laurent Rougé, chief executive officer.
“Quartus II, Altera’s flagship design software includes integrated VHDL and SystemVerilog technology from Verific. Verific’s software meets the high standard of quality our customers have come to expect from us.”
– Premal Buch, VP Software Engineering.
“Verific and Calypto have been development partners for many years. Verific’s team is exceptional and its support is unmatched. Our experience working with Verific has been excellent.”
– Nikhil Sharma, vice president of engineering (acquired by Mentor Graphics).
“Real Intent knows first hand why Verific is successful. We have enjoyed a long-term winning collaboration with them and Verific continues to keep us up to date with the latest developments in SystemVerilog.”
– Graham Bell, VP of Marketing.
“Verific’s SystemVerilog and VHDL parsers are among the best architected and implemented software packages in EDA.”
– Karen Pieper, director of software.
“We have employed Verific’s SystemVerilog parser for several years within our internally developed EDA tools. There is no way we could have developed this ourselves cost-effectively. The large number of users across the industry and responsiveness of the Verific engineers have ensured a mature and robust product.”
– Dan Smith, senior director, hardware engineering.
“Full language support (including SystemVerilog), well-tested software and outstanding customer support made integration with the Verific compiler an easy choice to simplify the design setup flow for HES-DVM.”
– Zibi Zalewski, general manager hardware division.
“Selecting Verific’s front-end software enabled us to focus on our core competency and get our products to market much faster. Its reputation for quality, reliable software and excellent support is well earned.”
– Peter Petrov, founder and chief executive officer.
Blue Pearl Software
“It was logical to us to choose Verific Design Automation for our 6.0 version since Verific is an instantly recognizable brand-name provider of Verilog, SystemVerilog and VHDL parsers. Design teams applauded us when we selected Verific as the front-end for our Blue Pearl Software Suite.”
– Scott Bloom, vice president engineering.
“We had an excellent experience with the integration of Verific’s front-end tools into our tools. Full-scale integration took us one month, thanks both to Verific technology and Verific support. We have found Verific to be the most advanced company in the field. The fast integration allowed us to significantly shorten the time to market for our products.”
– Reuven Dobkin, chief technology officer.
“When we looked for a platform for RTL analysis, we quickly realized that the only answer was Verific. I can say without hesitation that this was a good move. Our customers know and recognize the value of Verific technology. Verific has been an exceptionally responsive vendor and the platforms it develops are top rate.”
– Sam Appleton, chief executive officer.
“Verific’s SystemVerilog solution was referred to us by one of our key strategic accounts. We have been impressed with Verific’s SystemVerilog solution and its technical support team. Our assertion technology requires extensive language elaboration, all of which Verific fully supports.”
– Yunshan Zhu, chief executive officer (acquired by Atrenta acquired by Synopsys).
“By leveraging Verific’s software, we have been able to focus on developing the key value-add technologies for our customers. Their software and support is excellent.”
– Dr. Brad Quinton, chief technical officer and founder (acquired by Mentor Graphics).
Forte Design Systems
“Verific’s reputation for solid product offerings and strong customer support are well earned. We’ve been impressed with Verific’s willingness to work with us through the transition and its commitment to making CellMath Designer a ‘must-have’ datapath synthesis tool.
– Sean Dart, chief executive officer (acquired by Cadence).
“Verific is a company with first-rate products and excellent support. Parallel Engines will utilize Verific in its upcoming IP/RT Level, web-enabled floorplanner, aiding designers in physical semiconductor-IP integration.”
– George Janac, chief executive officer.
“Verific’s software is robust and dependable, which allows our engineers to focus on our core expertise, automated debugging, On the business side, Verific has been an extremely supportive business partner from our university spin-off days to today.”
– Dr. Sean Safarpour, vice president of engineering.
“Integrating Verific’s software with RealTime Designer had been a part of our product planning and development from the beginning because of its superior quality. Verific’s customer support group has a reputation for outstanding service and each member lived up to that reputation.”
– Paul van Besouw, chief executive officer (acquired by Mentor Graphics).
“Verific’s software serves as an essential component of our product development plan and gave us an immediate head start on worldwide product deployment.”
– Serge Maginot, chief executive officer.
“I am pleased with Verific’s software. Using the netlist parser and data structures enabled us to kick-start our development and focus on our core technology early on. It is well structured, easy to understand and efficient.”
– Dr. Emre Tuncer, vice president of engineering.
“Building ACE leveraging Verific’s netlist parser and datastructures saved us a significant amount of time and effort. Their industry-proven software and customer support enabled us to focus on developing our own key software capabilities.”
– Raymond Nijssen, chief software architect.
“Soft Errors are affecting more electronic systems in advanced technologies than ever. iRoC Technologies provides design solutions and EDA tools to measure, analyze and fix the problem of soft errors in modern integrated circuits. And when iRoC needed support for Verilog RTL, we selected Verific Design Automation as our partner.”
– Eric Dupont, CEO.
“Through a tight integration of Verific’s front-end software with Libero, designers are able to create and automatically abstract block-based system designs into synthesis-ready VHDL or Verilog components. Verific’s goal to provide quality products and exceptional support is perfectly in tune with our way of thinking that keeps us innovating to ease design challenges.”
– Ken Joyner, director of engineering (acquired by Microsemi).
“Certitude has already been implemented by 50 design teams worldwide and many have given us high marks for our HDL capabilities. We credit Verific for quality products and highly professional support and service, making it a vendor we’ve enjoyed as a business partner.”
– Michel Courtoy, chief executive officer (acquired by Springsoft acquired by Synopsys).
“With next-generation tools such as Amber, only the best-in-class software like those from Verific will help us meet complex design challenges. We found that the Verific HDL Component Software had the capacity and performance our customers require for their designs.”
– Isadore Katz, president and CEO.
“We were immediately impressed with the range of Verific’s customers, many of whom are our EDA partners. It became clear early in our relationship that Verific’s products and support team are equally impressive. It’s been an extremely rewarding joint technical development effort.”
– Philippe Duchene, vice president of engineering.
“We are offering the best solution to address an acute debugging and verification problem and Verific is the only EDA tool provider that can meet our rigorous requirements. I’ve worked with Verific and know the team to be highly competent and customer focused. It was an easy choice for us.”
– Dave Orecchio, president and CEO.
“We are happy working with Verific, as utilizing SystemVerilog represents a cornerstone of our configurable IP strategy. Incorporating its tool into our flows saves us valuable time and resources. We find Verific’s customer support and service to be exceptional.”
– Brian Gardner, vice president of IP products (acquired by Cadence).
“Verific’s HDL Component Software is a comprehensive tool that Lattice has leveraged in its development of our HDL Explorer tool, a significant new capability that enables FPGA designers to more effectively and quickly complete their designs.”
– Chris Fanning, corporate vice president of software and IP solutions.
“When looking for software to serve as a front end to EDA design tools, Verific is the first name that comes up every time. And, for good reason — its products are easy to integrate and offer good value. With Verific serving as MVSIM’s front end, users can be assured quality and high performance verification.”
– Pratap Reddy, CEO and Chairman (acquired by Synopsys).
“Quartz Formal, our state-of-the-art equivalence checker, required a language front-end that would match its quality and performance. We found all that and more in Verific’s Verilog, VHDL, and SystemVerilog parsers / elaborators. Their software is great and matched with excellent support.”
– Rajeev Madhavan, Chairman & CEO (acquired by Synopsys).
“Liga Systems turned to Verific for its industry-leading HDL Component Software because it helped us save invaluable time and effort. Our team has found the Verific code to be very clear, providing good value as we extend its use for simulation. Using Verific’s front-end technology, we were able to bring up a complex Verilog RTL compiler quickly, reducing our time to market, while achieving a high quality product.”
– Henry Verheyen, Chief Executive Officer.
“We relied on Verific to help us meet our product plan to link code with interactive graphic fragments. This partnership is effective and one that we see lasting for a long time.”
– Gerhard Angst, president and CEO.
“We are committed to increasing our customers’ profitability through software solutions that accelerate system design. Verific’s HDL Component Software was instrumental in us being able to more quickly support our customer’s needs.”
– Dr. Jeremy Bennett, Chief Technology Officer (acquired by ARC acquired by Synopsys).
“We looked no further than Verific when we sought out a front-end development partner. With the integration of Verific’s HDL Component Software we could expand the capabilities of our CHIPit systems, especially for the transaction-based verification Verific offers an exceptional package of production-proven, quality software, along with excellent support and service.”
– Gunnar Scholl, director of Marketing and Business Development (business unit acquired by Synopsys).
“Verific’s HDL Component Software has become the industry standard and for good reason. The software is first rate and the support is outstanding. Verific is an excellent development partner.”
– Dr. Luc Burgun, CEO and president (acquired by Synopsys).
“Verific’s commitment to customer support by the R&D team is commendable. Their dedication ensured that we got the features we needed, and made a significant impact with us.”
– Keiichi Suzuki, senior engineer.
“Without Verific, an internal SystemVerilog development effort would have been a long, difficult process. Verific’s language solutions, combined with Jasper’s leading assertion synthesis technology, have contributed to our leading position in formal verification for standard assertion and design languages. Verific is a superior business partner and we commend them for being responsive and committed to the current market success of JasperGold Verification System.”
– Dr. Claudionor Coelho, Vice President of Engineering (acquired by Cadence).
“We felt that it was crucial to provide strong support for Verilog within Nexar. Rather than developing our own parsers and analyzers, we found that Verific’s well-engineered and reliable HDL Component Software was the right fit for our needs. We can focus on other aspects of Nexar, and strengthen its position as the universal design system of choice for FPGA-based systems development.”
– Nick Martin, founder and joint CEO.
“The runtime and memory footprint is vastly superior to all other parsers that we evaluated. Support has been superb as well. No issue took longer then three days to have a workaround, and all enhancement requests were granted.”
– Scott Bloom, vice president of engineering (acquired by Lattice Semiconductor).
“Verific’s technology is enabling us to develop our product with full multi-language support and proven Verilog and VHDL language compatibility. Working with the Verific software team, we have enjoyed a productive development relationship and appreciate their excellent responsiveness and support.”
– Dave Miller, vice president of engineering.
“We replaced our existing Verilog and VHDL parsers and elaborator with Verific’s solution. This solution has resulted in significant improvements in the performance and accuracy of the language front-end to Powertheater. Our partnership with Verific will be of great benefit to all our PowerTheater customers.”
– Tom Miller, VP of Engineering (acquired by Apache Design Solutions acquired by Ansys).
“NEC spends significant resources in advancing state-of-the-art EDA research to maintain its leadership position in SOC design. Using Verific’s software fits right into our best-in-class strategy. We very much like that Verific provides us with source code. In addition, support and training so far have been excellent.”
– Dr. Masao Fukuma, vice president and general manager of NEC System Devices Research Laboratories.
“2.5 hours after receiving the code, we were fully up and running, including invoking the Verific makefile from our own compilation flow. We had a seamless migration from using the Verific evaluation binaries to using the real source code. We, and Infineon, are very happy with the quality of your deliverables.”
– Peter Jensen, Sysosil Consulting / Infineon.
“Verific’s tool does exactly what we need to improve our design flow for mixed-signal chips. As a result, Verific has become an important design tool partner, helping us to construct an integrated tool set for mixed-signal design.”
– Jim Reid, Chief Technical Officer (acquired by Cirrus Logic)
“As a performance leader in Hardware Acceleration, Tharas was pushed by its customers to add VHDL support. To accelerate time to market, Tharas decided to look at 3rd party VHDL front-ends. Ater extensive evaluations, we chose Verific as our VHDL front-end. The quality and accessibility of the source code makes it far superior over its competitors. Verific has provided outstanding support, and has proved to be a great R&D partner.”
– Ramesh Narayanaswamy, VP engineering (acquired by EVE acquired by Synopsys).
“So far, we have used Verific’s Verilog and VHDL front-ends for a DFT rule checker and a Logic Equivalence checker. Both products are in production use with our internal customers. We, as well as our end-users, are very impressed with the language support, overall quality and speed of the software. It would have taken us at least 2 years of development and debug time to get to the same results. With Verific’s language front-ends our development team can now focus on its core competency and the actual design problems of our customers.”
– Mario Konijnenburg, Research Scientist and Software Engineer.
“We chose Verific Design Automation as our Verilog and VHDL front-end provider, since they offered the best solution in terms of maturity, language coverage and source code access. Verific has been a great company to work with, they offer excellent technical support, and they have a strong product road map going forward.”
– Arne Boralv, CTO (acquired by Jasper acquired by Cadence).
“Our products require push-button import of legacy Verilog and VHDL designs with syntax checking. Rather than developing our own parsers and analysers, we chose to purchase software from Verific Design Automation for reasons of product quality and time to market. We found the software well architected and very reliable and as a result, we easily saved 12 months of engineering development time.”
– Willem Gruter, founder and president.