Verific Design Automation (Verilog/VHDL frontends/compilers/analyzers/elaborators)

Verilog Reader

Verific’s Verilog reader is built for high-speed parsing, analysis, and elaboration. It supports static elaboration as well RTL elaboration. It is integrated with a language-independent database common to all readers.

Highlights

Fastest Verilog reader available: Parses, analyses and elaborates 15,000 lines/second RTL, 30,000 lines/second flat-netlist code. (Average throughput, 2 Ghz Xeon, Red Hat Linux 8.0)

Verilog 1995/2001 and AMS support.

RTL synthesis subset semantic checking.

FSM and RAM extraction/recognition from RTL.

Built-in Verilog pre-processor.

100% Language coverage supported for analysis.

Wide language subset supported for elaboration, including memory, named ports, tasks, functions, variable-indexing, string constants, UDP tables, etc.

Verilog XL compliance with unknown module instantiation, and -y/-v file search mechanisms.

WYSIWYG or optimized netlist creation.

Preservation of line/file origination into database.

Database

The database stores RTL and netlist designs in a language-independent simple model. The database is common to all readers and has an efficient and clean API for easy integration into your existing database or object model.

Very memory efficient. Average overall memory usage just 300 bytes/gate.

Fast database traversal due to optimal container/pointer organization between database objects.

Full hierarchy support, with grouping/ungrouping, etc.

Full support for any number of libraries, and no restrictions on library interaction (instantiations across different libraries).

Support for buses.

Compact storage of line/file origination info from RTL Readers.

Simple and clean data model and Procedural Interface for easy integration with your existing database.

SystemVerilog - Verilog - Verilog Netlist Only - VHDL - PSL - EDIF - Liberty - SDF