Verific Design Automation (Verilog/VHDL frontends/compilers/analyzers/elaborators)

VHDL Reader

Verific’s VHDL reader is built for widest RTL synthesis language subset support and speedy reading of large files. It is integrated with a language-independent database common to all readers.

Highlights

Fastest VHDL reader available: Parses, analyses and elaborates 10,000 lines/second RTL, 30,000 lines/second flat-netlist code. (Average throughput, 2 Ghz Xeon, Red Hat Linux 8.0).
VHDL 93 as well as VHDL 87 support.
RTL synthesis subset semantic checking.
FSM and RAM extraction/recognition from RTL.
100% language coverage supported for analysis.
Wide language subset supported for elaboration, including IEEE 1164, unrestricted multiple libraries, records, multi-dimensional arrays, arrays of anything, generics, configurations, user-defined and overloaded functions/procedures/enumeration types, variable-indexing etc.
Support for all standard and de-facto standard synthesis packages.
Support for all Exemplar, Synopsys, Synplicity pragmas and synthesis directives.
WYSIWYG netlist or optimized netlist creation.
Preservation of line/file origination into database.

Database

The database stores RTL and netlist designs in a language-independent simple model. The database is common to all readers and has an efficient and clean API for easy integration into your existing database or object model.

Very memory efficient. Average overall memory usage just 300 bytes/gate.
Fast database traversal due to optimal container/pointer organization between database objects.
Full hierarchy support, with grouping/ungrouping, etc.
Full support for any number of libraries, and no restrictions on library interaction (instantiations across different libraries).
Support for buses.
Compact storage of line/file origination info from RTL Readers.
Simple and clean data model and Procedural Interface for easy integration with your existing database.

SystemVerilog - Verilog - Verilog Netlist Only - VHDL - PSL - EDIF - Liberty - SDF