Verific Design Automation FAQ - User contributions [en]

Main Page

2024-02-28T05:25:55Z

Alice:

'''General'''
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
* [[Source code customization & Stable release services | Source code customization & Stable release services]]
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]
* [[Release version | How do I tell the version of a Verific software release? ]]
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
* [[LineFile data from input files | LineFile data from input files]]
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]
* [[Preserving user nets - preventing nets from being optimized away | Preserving user nets - preventing nets from being optimized away]]
* [[Python pretty-printer for gdb | Python pretty-printer for gdb]]

'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Port Expressions]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[Modules with '_1' '_2' suffix in their names | Verilog: After static elaboration, there are modules with "_1", "_2", ..., suffix in their names. Why?]]
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
* [[Notes on analysis | SystemVerilog: Notes on analysis]]
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units/interfaces with "_default" suffix in their names. Why? And what are they?]]
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
'''Netlist Database'''
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]
* [[System attributes | Netlist Database: System attributes]]

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''Scripting languages: TCL, Perl, Python'''
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]

'''Code examples'''
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]
* [[How to use MessageCallBackHandler Class | Util/C++: How to use MessageCallBackHandler Class]]
* [[How to use RegisterPragmaRefCallBack() | Util/C++: How to use RegisterPragmaRefCallBack()]]
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
* [[Extract clock enable | Database/C++: Extract clock enable]]
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
* [[Post processing port resolution of black boxes | Database/C++: Post processing port resolution of black boxes]]
* [[Finding hierarchical paths of a Netlist | Database/C++: Finding hierarchical paths of a Netlist]]
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
* [[Type Range example | Verilog/C++: Type Range example (simple)]]
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
* [[How to ignore certain modules while analyzing input RTL files | Verilog/C++: How to ignore certain modules while analyzing input RTL files]]
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
* [[In Verilog parsetree adding names to unnamed instances | Verilog/C++: In Verilog parsetree adding names to unnamed instances]]
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]
* [[Parse select modules only and ignore the rest | Verilog/C++: Parse select modules only and ignore the rest]]
* [[Create DOT diagram of parse tree | Verilog/C++: Create DOT diagram of a parse tree]]
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
* [[Evaluate 'for-generate' loop | Verilog/C++: Evaluate 'for-generate' loop]]
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
* [[Simple examples of VHDL visitor pattern | VHDL/C++: Simple examples of VHDL visitor pattern]]
* [[Traverse instances in parsetree | VHDL/C++: Traverse instances in parsetree]]
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]

Post processing port resolution of black boxes

2024-02-20T00:44:21Z

Alice:

C++ example:
<nowiki>
#include "Map.h"
#include "Message.h"
#include "veri_file.h"
#include "DataBase.h"
#include "VeriWrite.h"
#include "RuntimeFlags.h"
#include <iostream>

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main(int argc, char **argv)
{
if (argc < 2) {
Message::PrintLine("Default input file: test.v. Specify command line argument to override") ;
}

const char *file_name = 0 ;

if (argc>1) {
file_name = argv[1] ; // Set the file name as specified by the user
} else {
file_name = "test.v" ;
}

if (!veri_file::Analyze(file_name, veri_file::SYSTEM_VERILOG)) return 1 ;
if (!veri_file::ElaborateAll()) return 1 ;

Netlist *top = Netlist::PresentDesign() ;

VeriWrite vw ;
RuntimeFlags::SetVar("db_verilog_writer_write_blackboxes", 2) ;
vw.WriteFile ("netlist_before.v", top) ;

// Lets accumulate all netlist
Set netlists(POINTER_HASH) ;
top->Hierarchy(netlists, 0 /* bottom to top */) ;

Netlist *netlist ;
SetIter si ;

unsigned changed = 0 ;
unsigned pass = 1 ;
do { // do this until there are no changes in port directions of 'unknown' modules
std::cout << std::endl << "=> Pass " << pass++ << std::endl ;
changed = 0 ;
FOREACH_SET_ITEM(&netlists, si, &netlist) {
if (!netlist->GetAtt(" unknown_design")) continue ; // Skip if not 'unknown'
Instance *instance ;
SetIter si2 ;
// Iterate over all references (Instances) of this Netlist
FOREACH_REFERENCE_OF_NETLIST(netlist, si2, instance) {
std::cout << "===> Instance '" << instance->Name() << "' of unknown module '"
<< netlist->Owner()->Name() << "'"<< std::endl ;
MapIter mi2 ;
PortRef *portref ;
FOREACH_PORTREF_OF_INST(instance, mi2, portref) {
Port *port = portref->GetPort() ;
if (!port->IsInout()) continue ; // Only look at inout ports
unsigned dir_known = 0 ;
std::cout << "===> Port: '" << port->Name() << "'"<< std::endl ;
Net *net = portref->GetNet() ;
if (!net) {
std::cout << "===> Does not connect to any Net" << std::endl ;
continue ;
}
// Is this port connected to any Port?
Port *port2 ;
SetIter si ;
FOREACH_PORT_OF_NET(net, si, port2) {
if (port2->IsInput()) {
std::cout << "===> Connected to input port '" << port2->Name() << "' of owning Netlist" << std::endl ;
std::cout << "===> Set port '" << port->Name() << "' to input" << std::endl ;
netlist->GetPort(port->Name())->SetDir(DIR_IN) ;
dir_known = 1 ;
changed = 1 ;
} else if (port2->IsOutput()) {
if (net->NumOfPortRefs() == 1 ) { // does not connected to any other instance
std::cout << "===> Only connected to output port '" << port2->Name() << "' of owning Netlist" << std::endl ;
std::cout << "===> Set port '" << port->Name() << "' to output" << std::endl ;
netlist->GetPort(port->Name())->SetDir(DIR_OUT) ;
dir_known = 1 ;
changed = 1 ;
}
}
}
// If still don't know direction, check other connections
if (!dir_known) {
PortRef *portref2 ;
SetIter si2 ;
FOREACH_PORTREF_OF_NET(net, si2, portref2) {
if (portref2 == portref) continue ; // not checking self
if (portref2->IsOutput()) { // connected to an output portref, must be an input port
Instance *instance2 = portref2->GetInst() ;
Port *port3 = portref2->GetPort() ;
std::cout << "===> Connected to output port '" << port3->Name()
<< "' of instance ' " << instance2->Name() << "'" << std::endl ;
std::cout << "===> Set port '" << port->Name() << "' to input" << std::endl ;
netlist->GetPort(port->Name())->SetDir(DIR_IN) ;
dir_known = 1 ;
changed = 1 ;
break ;
} else if (portref2->IsInout()) { // connected to an inout portref, still don't know direction
break ;
} else { // all portrefs are inputs, must be an output port
std::cout << "===> All other PortRefs are inputs" << std::endl ;
std::cout << "===> Set port '" << port->Name() << "' to output" << std::endl ;
netlist->GetPort(port->Name())->SetDir(DIR_OUT) ;
dir_known = 1 ;
changed = 1 ;
}
}
}
if (!dir_known) { // Still clueless
std::cout << "===> Not enough data, remains inout" << std::endl ;
}
}
}
}
} while (changed) ;

vw.WriteFile ("netlist_after.v", top) ;

return 0 ;
}
</nowiki>

------------------------------------------------------------------------

Run:
<nowiki>
-- Default input file: test.v. Specify command line argument to override
-- Analyzing Verilog file 'test.v' (VERI-1482)
test.v(1): INFO: compiling module 'top' (VERI-1018)
test.v(11): INFO: compiling module 'known1' (VERI-1018)
test.v(14): INFO: compiling module 'known2' (VERI-1018)
test.v(5): WARNING: instantiating unknown module 'unknown1' (VERI-1063)
test.v(6): WARNING: instantiating unknown module 'unknown2' (VERI-1063)
-- Writing netlist 'top' to Verilog file 'netlist_before.v' (VDB-1030)

=> Pass 1
===> Instance 'iu1' of unknown module 'unknown1'
===> Port: 'p1'
===> Connected to output port 'o' of instance ' ik1'
===> Set port 'p1' to input
===> Port: 'p2'
===> Connected to input port 'i2' of owning Netlist
===> Set port 'p2' to input
===> Port: 'p3'
===> Not enough data, remains inout
===> Port: 'p4'
===> All other PortRefs are inputs
===> Set port 'p4' to output
===> Port: 'p5'
===> Only connected to output port 'o3' of owning Netlist
===> Set port 'p5' to output
===> Port: 'p6'
===> Not enough data, remains inout
===> Port: 'p7'
===> Not enough data, remains inout
===> Instance 'iu2a' of unknown module 'unknown2'
===> Port: 'p1'
===> Not enough data, remains inout
===> Port: 'p2'
===> Not enough data, remains inout
===> Port: 'p3'
===> Connected to input port 'i3' of owning Netlist
===> Set port 'p3' to input
===> Instance 'iu2b' of unknown module 'unknown2'
===> Port: 'p1'
===> Connected to input port 'i1' of owning Netlist
===> Set port 'p1' to input
===> Port: 'p2'
===> Not enough data, remains inout
===> Instance 'iu2c' of unknown module 'unknown2'
===> Port: 'p2'
===> Only connected to output port 'o4' of owning Netlist
===> Set port 'p2' to output

=> Pass 2
===> Instance 'iu1' of unknown module 'unknown1'
===> Port: 'p3'
===> Connected to output port 'p2' of instance ' iu2a'
===> Set port 'p3' to input
===> Port: 'p6'
===> All other PortRefs are inputs
===> Set port 'p6' to output
===> Port: 'p7'
===> Not enough data, remains inout
===> Instance 'iu2a' of unknown module 'unknown2'
===> Instance 'iu2b' of unknown module 'unknown2'
===> Instance 'iu2c' of unknown module 'unknown2'

=> Pass 3
===> Instance 'iu1' of unknown module 'unknown1'
===> Port: 'p7'
===> Not enough data, remains inout
===> Instance 'iu2a' of unknown module 'unknown2'
===> Instance 'iu2b' of unknown module 'unknown2'
===> Instance 'iu2c' of unknown module 'unknown2'
-- Writing netlist 'top' to Verilog file 'netlist_after.v' (VDB-1030)
</nowiki>

------------------------------------------------------------------------

netlist_before.v
<nowiki>
module top (i1, i2, i3, o1, o2, o3, o4) ; // test.v(1)
input i1; // test.v(1)
input i2; // test.v(1)
input i3; // test.v(1)
output o1; // test.v(1)
output o2; // test.v(1)
output o3; // test.v(1)
output o4; // test.v(1)

wire t1; // test.v(2)
wire t2; // test.v(2)
wire t3; // test.v(2)
wire t4; // test.v(2)
wire t5; // test.v(2)
wire t6; // test.v(2)

known1 ik1 (.i1(i3), .i2(t2), .o(t3)); // test.v(3)
known2 ik2 (.i1(i1), .i2(t1), .o(o2)); // test.v(4)
unknown1 iu1 (.p1(t3), .p2(i2), .p3(t2), .p4(t1), .p5(o3), .p6(t4),
.p7(t5)); // test.v(5)
unknown2 iu2a (.p1(t4), .p2(t2), .p3(i3)); // test.v(6)
unknown2 iu2b (.p1(i1), .p2(t2), .p3(i3)); // test.v(7)
unknown2 iu2c (.p1(t6), .p2(o4), .p3(i3)); // test.v(8)

endmodule

module known1 (i1, i2, o) ; // test.v(11)
input i1; // test.v(11)
input i2; // test.v(11)
output o; // test.v(11)
endmodule

module known2 (i1, i2, o) ; // test.v(14)
input i1; // test.v(14)
input i2; // test.v(14)
output o; // test.v(14)
endmodule

module unknown1 (p1, p2, p3, p4, p5, p6, p7) ;
inout p1;
inout p2;
inout p3;
inout p4;
inout p5;
inout p6;
inout p7;
endmodule

module unknown2 (p1, p2, p3) ;
inout p1;
inout p2;
inout p3;
endmodule
</nowiki>

netlist_after.v
<nowiki>
module top (i1, i2, i3, o1, o2, o3, o4) ; // test.v(1)
input i1; // test.v(1)
input i2; // test.v(1)
input i3; // test.v(1)
output o1; // test.v(1)
output o2; // test.v(1)
output o3; // test.v(1)
output o4; // test.v(1)

wire t1; // test.v(2)
wire t2; // test.v(2)
wire t3; // test.v(2)
wire t4; // test.v(2)
wire t5; // test.v(2)
wire t6; // test.v(2)

known1 ik1 (.i1(i3), .i2(t2), .o(t3)); // test.v(3)
known2 ik2 (.i1(i1), .i2(t1), .o(o2)); // test.v(4)
unknown1 iu1 (.p1(t3), .p2(i2), .p3(t2), .p4(t1), .p5(o3), .p6(t4),
.p7(t5)); // test.v(5)
unknown2 iu2a (.p1(t4), .p2(t2), .p3(i3)); // test.v(6)
unknown2 iu2b (.p1(i1), .p2(t2), .p3(i3)); // test.v(7)
unknown2 iu2c (.p1(t6), .p2(o4), .p3(i3)); // test.v(8)

endmodule

module known1 (i1, i2, o) ; // test.v(11)
input i1; // test.v(11)
input i2; // test.v(11)
output o; // test.v(11)
endmodule

module known2 (i1, i2, o) ; // test.v(14)
input i1; // test.v(14)
input i2; // test.v(14)
output o; // test.v(14)
endmodule

module unknown1 (p1, p2, p3, p4, p5, p6, p7) ;
input p1;
input p2;
input p3;
output p4;
output p5;
output p6;
inout p7;
endmodule

module unknown2 (p1, p2, p3) ;
input p1;
output p2;
input p3;
endmodule
</nowiki>

------------------------------------------------------------------------

test.v
<nowiki>
module top (input i1, i2, i3, output o1, o2, o3, o4);
wire t1, t2, t3, t4, t5, t6;
known1 ik1 (.i1(i3), .i2(t2), .o(t3));
known2 ik2 (.i1(i1), .i2(t1), .o(o2));
unknown1 iu1 (.p1(t3), .p2(i2), .p3(t2), .p4(t1), .p5(o3), .p6(t4), .p7(t5));
unknown2 iu2a (.p1(t4), .p2(t2), .p3(i3));
unknown2 iu2b (.p1(i1), .p2(t2), .p3(i3));
unknown2 iu2c (.p1(t6), .p2(o4), .p3(i3));
endmodule

module known1 (input i1, i2, output o);
endmodule

module known2 (input i1, i2, output o);
endmodule
</nowiki>

Main Page

2024-02-18T03:59:13Z

Alice:

'''General'''
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
* [[Source code customization & Stable release services | Source code customization & Stable release services]]
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]
* [[Release version | How do I tell the version of a Verific software release? ]]
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
* [[LineFile data from input files | LineFile data from input files]]
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]
* [[Preserving user nets - preventing nets from being optimized away | Preserving user nets - preventing nets from being optimized away]]
* [[Python pretty-printer for gdb | Python pretty-printer for gdb]]

'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Port Expressions]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[Modules with '_1' '_2' suffix in their names | Verilog: After static elaboration, there are modules with "_1", "_2", ..., suffix in their names. Why?]]
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
* [[Notes on analysis | SystemVerilog: Notes on analysis]]
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units/interfaces with "_default" suffix in their names. Why? And what are they?]]
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
'''Netlist Database'''
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]
* [[System attributes | Netlist Database: System attributes]]

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''Scripting languages: TCL, Perl, Python'''
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]

'''Code examples'''
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]
* [[How to use MessageCallBackHandler Class | Util/C++: How to use MessageCallBackHandler Class]]
* [[How to use RegisterPragmaRefCallBack() | Util/C++: How to use RegisterPragmaRefCallBack()]]
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
* [[Extract clock enable | Database/C++: Extract clock enable]]
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
* [[Finding hierarchical paths of a Netlist | Database/C++: Finding hierarchical paths of a Netlist]]
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
* [[Type Range example | Verilog/C++: Type Range example (simple)]]
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
* [[How to ignore certain modules while analyzing input RTL files | Verilog/C++: How to ignore certain modules while analyzing input RTL files]]
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
* [[In Verilog parsetree adding names to unnamed instances | Verilog/C++: In Verilog parsetree adding names to unnamed instances]]
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]
* [[Parse select modules only and ignore the rest | Verilog/C++: Parse select modules only and ignore the rest]]
* [[Create DOT diagram of parse tree | Verilog/C++: Create DOT diagram of a parse tree]]
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
* [[Evaluate 'for-generate' loop | Verilog/C++: Evaluate 'for-generate' loop]]
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
* [[Simple examples of VHDL visitor pattern | VHDL/C++: Simple examples of VHDL visitor pattern]]
* [[Traverse instances in parsetree | VHDL/C++: Traverse instances in parsetree]]
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]

Main Page

2024-02-17T02:58:09Z

Alice:

'''General'''
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
* [[Source code customization & Stable release services | Source code customization & Stable release services]]
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]
* [[Release version | How do I tell the version of a Verific software release? ]]
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
* [[LineFile data from input files | LineFile data from input files]]
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]
* [[Preserving user nets - preventing nets from being optimized away | Preserving user nets - preventing nets from being optimized away]]
* [[Python pretty-printer for gdb | Python pretty-printer for gdb]]

'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Port Expressions]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[Modules with '_1' '_2' suffix in their names | Verilog: After static elaboration, there are modules with "_1", "_2", ..., suffix in their names. Why?]]
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
* [[Notes on analysis | SystemVerilog: Notes on analysis]]
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units/interfaces with "_default" suffix in their names. Why? And what are they?]]
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
'''Netlist Database'''
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]
* [[System attributes | Netlist Database: System attributes]]

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''Scripting languages: TCL, Perl, Python'''
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]

'''Code examples'''
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]
* [[How to use MessageCallBackHandler Class | Util/C++: How to use MessageCallBackHandler Class]]
* [[How to use RegisterPragmaRefCallBack() | Util/C++: How to use RegisterPragmaRefCallBack()]]
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
* [[Extract clock enable | Database/C++: Extract clock enable]]
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
* [[Post processing port resolution of black boxes | Database/Verilog/C++: Post processing port resolution of black boxes]]
* [[Finding hierarchical paths of a Netlist | Database/C++: Finding hierarchical paths of a Netlist]]
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
* [[Type Range example | Verilog/C++: Type Range example (simple)]]
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
* [[How to ignore certain modules while analyzing input RTL files | Verilog/C++: How to ignore certain modules while analyzing input RTL files]]
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
* [[In Verilog parsetree adding names to unnamed instances | Verilog/C++: In Verilog parsetree adding names to unnamed instances]]
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]
* [[Parse select modules only and ignore the rest | Verilog/C++: Parse select modules only and ignore the rest]]
* [[Create DOT diagram of parse tree | Verilog/C++: Create DOT diagram of a parse tree]]
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
* [[Evaluate 'for-generate' loop | Verilog/C++: Evaluate 'for-generate' loop]]
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
* [[Simple examples of VHDL visitor pattern | VHDL/C++: Simple examples of VHDL visitor pattern]]
* [[Traverse instances in parsetree | VHDL/C++: Traverse instances in parsetree]]
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]

Post processing port resolution of black boxes

2024-02-17T02:56:29Z

Alice: Created page with "C++ example: <nowiki> #include "Map.h" #include "Message.h" #include "veri_file.h" #include "DataBase.h" #include "VeriWrite.h" #include "Run..."

C++ example:
<nowiki>
#include "Map.h"
#include "Message.h"
#include "veri_file.h"
#include "DataBase.h"
#include "VeriWrite.h"
#include "RuntimeFlags.h"
#include <iostream>

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main(int argc, char **argv)
{
if (argc < 2) {
Message::PrintLine("Default input file: test.v. Specify command line argument to override") ;
}

const char *file_name = 0 ;

if (argc>1) {
file_name = argv[1] ; // Set the file name as specified by the user
} else {
file_name = "test.v" ;
}

if (!veri_file::Analyze(file_name, veri_file::SYSTEM_VERILOG)) return 1 ;
if (!veri_file::ElaborateAll()) return 1 ;

Netlist *top = Netlist::PresentDesign() ;

VeriWrite vw ;
RuntimeFlags::SetVar("db_verilog_writer_write_blackboxes", 2) ;
vw.WriteFile ("netlist_before.v", top) ;

MapIter mi ;
Instance * instance ;
FOREACH_INSTANCE_OF_NETLIST(top, mi, instance) {
Netlist *view = instance->View() ;
if (!view) continue ;
if (view->GetAtt(" unknown_design")) {
std::cout << "===> Instance '" << instance->Name() << "' is of unknown module '"
<< instance->View()->Owner()->Name() << "'"<< std::endl ;
MapIter mi2 ;
PortRef *portref ;
FOREACH_PORTREF_OF_INST(instance, mi2, portref) {
unsigned dir_known = 0 ;
Port *port = portref->GetPort() ;
std::cout << "===> Port: '" << port->Name() << "'"<< std::endl ;
Net *net = portref->GetNet() ;
if (!net) {
std::cout << "===> Does not connect to any Net" << std::endl ;
continue ;
}
// Is this port connected to any Port?
Port *port2 ;
SetIter si ;
FOREACH_PORT_OF_NET(net, si, port2) {
if (port2->IsInput()) {
std::cout << "===> Connected to input port '" << port2->Name() << "' of owning Netlist" << std::endl ;
std::cout << "===> Set port '" << port->Name() << "' to input" << std::endl ;
view->GetPort(port->Name())->SetDir(DIR_IN) ;
dir_known = 1 ;
} else if (port2->IsOutput()) {
if (net->NumOfPortRefs() == 1 ) { // does not connected to any other instance
std::cout << "===> Only connected to output port '" << port2->Name() << "' of owning Netlist" << std::endl ;
std::cout << "===> Set port '" << port->Name() << "' to output" << std::endl ;
view->GetPort(port->Name())->SetDir(DIR_OUT) ;
dir_known = 1 ;
}
}
}
// If still don't know direction, check other connections
if (!dir_known) {
PortRef *portref2 ;
SetIter si2 ;
FOREACH_PORTREF_OF_NET(net, si2, portref2) {
if (portref2 == portref) continue ; // not checking self
if (portref2->IsOutput()) { // connected to an output portref, must be an input port
Instance *instance2 = portref2->GetInst() ;
Port *port3 = portref2->GetPort() ;
std::cout << "===> Connected to output port '" << port3->Name()
<< "' of instance ' " << instance2->Name() << "'" << std::endl ;
std::cout << "===> Set port '" << port->Name() << "' to input" << std::endl ;
view->GetPort(port->Name())->SetDir(DIR_IN) ;
dir_known = 1 ;
break ;
} else if (portref2->IsInout()) { // connected to an inout portref, still don't know direction
break ;
} else { // all portrefs are inputs, must be an output port
std::cout << "===> All other PortRefs are inputs" << std::endl ;
std::cout << "===> Set port '" << port->Name() << "' to output" << std::endl ;
view->GetPort(port->Name())->SetDir(DIR_OUT) ;
dir_known = 1 ;
}
}
}
if (!dir_known) { // Still clueless
std::cout << "===> Not enough data, remains inout" << std::endl ;
}
}
}
}

vw.WriteFile ("netlist_after.v", top) ;

return 0 ;
}
</nowiki>

------------------------------------------------------------------------

Run:
<nowiki>
-- Default input file: test.v. Specify command line argument to override
-- Analyzing Verilog file 'test.v' (VERI-1482)
test.v(1): INFO: compiling module 'top' (VERI-1018)
test.v(9): INFO: compiling module 'known1' (VERI-1018)
test.v(12): INFO: compiling module 'known2' (VERI-1018)
test.v(5): WARNING: instantiating unknown module 'unknown1' (VERI-1063)
test.v(6): WARNING: instantiating unknown module 'unknown2' (VERI-1063)
-- Writing netlist 'top' to Verilog file 'netlist_before.v' (VDB-1030)
===> Instance 'iu1' is of unknown module 'unknown1'
===> Port: 'p1'
===> Connected to output port 'o' of instance ' ik1'
===> Set port 'p1' to input
===> Port: 'p2'
===> Connected to input port 'i2' of owning Netlist
===> Set port 'p2' to input
===> Port: 'p3'
===> Not enough data, remains inout
===> Port: 'p4'
===> All other PortRefs are inputs
===> Set port 'p4' to output
===> Port: 'p5'
===> Only connected to output port 'o3' of owning Netlist
===> Set port 'p5' to output
===> Port: 'p6'
===> Not enough data, remains inout
===> Port: 'p7'
===> Not enough data, remains inout
===> Instance 'iu2' is of unknown module 'unknown2'
===> Port: 'p1'
===> Not enough data, remains inout
===> Port: 'p2'
===> Not enough data, remains inout
===> Port: 'p3'
===> Connected to input port 'i3' of owning Netlist
===> Set port 'p3' to input
-- Writing netlist 'top' to Verilog file 'netlist_after.v' (VDB-1030)
</nowiki>

------------------------------------------------------------------------

netlist_before.v
<nowiki>
module top (i1, i2, i3, o1, o2, o3) ; // test.v(1)
input i1; // test.v(1)
input i2; // test.v(1)
input i3; // test.v(1)
output o1; // test.v(1)
output o2; // test.v(1)
output o3; // test.v(1)

wire t1; // test.v(2)
wire t2; // test.v(2)
wire t3; // test.v(2)
wire t4; // test.v(2)
wire t5; // test.v(2)

known1 ik1 (.i1(i3), .i2(t2), .o(t3)); // test.v(3)
known2 ik2 (.i1(i1), .i2(t1), .o(o2)); // test.v(4)
unknown1 iu1 (.p1(t3), .p2(i2), .p3(t2), .p4(t1), .p5(o3), .p6(t4),
.p7(t5)); // test.v(5)
unknown2 iu2 (.p1(t4), .p2(t2), .p3(i3)); // test.v(6)
endmodule

module known1 (i1, i2, o) ; // test.v(9)
input i1; // test.v(9)
input i2; // test.v(9)
output o; // test.v(9)
endmodule

module known2 (i1, i2, o) ; // test.v(12)
input i1; // test.v(12)
input i2; // test.v(12)
output o; // test.v(12)
endmodule

module unknown1 (p1, p2, p3, p4, p5, p6, p7) ;
inout p1;
inout p2;
inout p3;
inout p4;
inout p5;
inout p6;
inout p7;
endmodule

module unknown2 (p1, p2, p3) ;
inout p1;
inout p2;
inout p3;
endmodule

</nowiki>

netlist_after.v
<nowiki>
module top (i1, i2, i3, o1, o2, o3); // test.v(1)
input i1; // test.v(1)
input i2; // test.v(1)
input i3; // test.v(1)
output o1; // test.v(1)
output o2; // test.v(1)
output o3; // test.v(1)

wire t1; // test.v(2)
wire t2; // test.v(2)
wire t3; // test.v(2)
wire t4; // test.v(2)
wire t5; // test.v(2)

known1 ik1 (.i1(i3), .i2(t2), .o(t3)); // test.v(3)
known2 ik2 (.i1(i1), .i2(t1), .o(o2)); // test.v(4)
unknown1 iu1 (.p1(t3), .p2(i2), .p3(t2), .p4(t1), .p5(o3), .p6(t4),
.p7(t5)); // test.v(5)
unknown2 iu2 (.p1(t4), .p2(t2), .p3(i3)); // test.v(6)
endmodule

module known1 (i1, i2, o) ; // test.v(9)
input i1; // test.v(9)
input i2; // test.v(9)
output o; // test.v(9)
endmodule

module known2 (i1, i2, o) ; // test.v(12)
input i1; // test.v(12)
input i2; // test.v(12)
output o; // test.v(12)
endmodule

module unknown1 (p1, p2, p3, p4, p5, p6, p7) ;
input p1;
input p2;
inout p3;
output p4;
output p5;
inout p6;
inout p7;
endmodule

module unknown2 (p1, p2, p3) ;
inout p1;
inout p2;
input p3;
endmodule
</nowiki>

------------------------------------------------------------------------

test.v
<nowiki>
module top (input i1, i2, i3, output o1, o2, o3);
wire t1, t2, t3, t4, t5;
known1 ik1 (.i1(i3), .i2(t2), .o(t3));
known2 ik2 (.i1(i1), .i2(t1), .o(o2));
unknown1 iu1 (.p1(t3), .p2(i2), .p3(t2), .p4(t1), .p5(o3), .p6(t4), .p7(t5));
unknown2 iu2 (.p1(t4), .p2(t2), .p3(i3));
endmodule

module known1 (input i1, i2, output o);
endmodule

module known2 (input i1, i2, output o);
endmodule
</nowiki>

Create a Netlist Database from scratch (not from RTL elaboration)

2023-09-20T19:20:47Z

Alice: Included equivalent python script

Perl script:
<nowiki>
#!/usr/bin/perl
use strict;

push (@INC,"../../../extra_tests/pm");
require "Verific.pm";

# The global Libset is already at the top of the netlist database.
# No need to create, just get a handle to it.
my $libset = Verific::Libset::Global();

# Add new library. If RTL elaboration has been run, a library has been created
# already. The default library is "work".
my $lib = Verific::Library->new("mylib");
$libset->Add($lib);

# Add cell to the library. In the Verilog netlist output, the cell name is the
# same as the module name.
my $cell = Verific::Cell->new("mycell");
$lib->Add($cell);

# Add netlist to cell. In the Verilog netlist output, the netlist name doesn't matter.
my $netlist = Verific::Netlist->new("mynetlist");
$cell->Add($netlist);

# Add ports to netlist
my $inport = Verific::Port->new("in", $Verific::DIR_IN);
$netlist->Add($inport);
my $outport = Verific::Port->new("out", $Verific::DIR_OUT);
$netlist->Add($outport);

# Add nets (Verilog: wire) to netlist
my $net1 = Verific::Net->new("in");
$netlist->Add($net1);
$net1->Connect($inport);

my $net2 = Verific::Net->new("out");
$netlist->Add($net2);
$net2->Connect($outport);

my $net3 = Verific::Net->new("n1");
$netlist->Add($net3);

# Add new library
my $primlib = Verific::Library->new("myprimitives");
$libset->Add($primlib);
# Create primitive inv
my $invcell = Verific::Cell->new("inv");
$primlib->Add($invcell);
my $invnetlist = Verific::Netlist->new("primitive");
$invcell->Add($invnetlist);
my $Ainport = Verific::Port->new("A", $Verific::DIR_IN);
$invnetlist->Add($Ainport);
my $Zoutport = Verific::Port->new("Z", $Verific::DIR_OUT);
$invnetlist->Add($Zoutport);
# Create primitive buff
my $buffcell = Verific::Cell->new("buff");
$primlib->Add($buffcell);
my $buffnetlist = Verific::Netlist->new("primitive");
$buffcell->Add($buffnetlist);
$Ainport = Verific::Port->new("A", $Verific::DIR_IN);
$buffnetlist->Add($Ainport);
$Zoutport = Verific::Port->new("Z", $Verific::DIR_OUT);
$buffnetlist->Add($Zoutport);

# Instantiate inv in mynetlist
my $inst = $netlist->Add(Verific::Instance->new("inv1", $invnetlist));
if ($inst) {
my $port = $invnetlist->GetPort("A");
if ($port) {$net1->Connect($inst, $port);}
$port = $invnetlist->GetPort("Z");
if ($port) {$net3->Connect($inst, $port);}
}

# Instantiate buff in mynetlist
$inst = $netlist->Add(Verific::Instance->new("buff2", $buffnetlist));
if ($inst) {
my $port = $buffnetlist->GetPort("A");
if ($port) {$net3->Connect($inst, $port);}
$port = $buffnetlist->GetPort("Z");
if ($port) {$net2->Connect($inst, $port);}
}

# write netlist
my $veriWriter = Verific::VeriWrite->new();
$veriWriter->WriteFile(sprintf("%s.v",$netlist->Owner->Name()), $netlist);

exit(1);

# moved this to a subroutine to keep above code clean,
# this subroutine shows how to resolve linefile information
sub vfcprintf {
my ($format) = (@_[0]);
my ($lf) = (@_[1]);
my @PARAMS;
for (my $i = 2; $i < scalar(@_); $i++) {
push(@PARAMS,"@_[$i]");
}
my $lf_format = "";
if (Verific::LineFile::GetFileName($lf) && Verific::LineFile::GetLineNo($lf)) {
my $lf_format = sprintf("%s(%s)",Verific::LineFile::GetFileName($lf), Verific::LineFile::GetLineNo($lf));
printf "%s: $format\n",$lf_format,@PARAMS;
} else {
printf "$format\n",@PARAMS;
}

return 0;
}
</nowiki>
Equivalent TCL script:
<nowiki>
# The global Libset is already at the top of the netlist database.
# No need to create, just get a handle to it.
set libset [Libset_Global];

# Add new library. If RTL elaboration has been run, a library has been created
# already. The default library is "work".
set lib [new_Library "mylib"];
Libset_Add $libset $lib;

# Add cell to the library. In the Verilog netlist output, the cell name is the
# same as the module name.
set cell [new_Cell "newcell"];
Library_Add $lib $cell;

# Add netlist to cell. In the Verilog netlist output, the netlist name doesn't matter.
set netlist [new_Netlist "mynetlist"];
Cell_Add $cell $netlist;

# Set the new netlist as present design
Netlist_SetPresentDesign $netlist;

# Add ports to netlist
set inport [new_Port "in" $DIR_IN];
Netlist_Add $netlist $inport;
set outport [new_Port "out" $DIR_OUT];
Netlist_Add $netlist $outport;

# Add nets (Verilog: wire) to netlist
set net1 [new_Net "in"];
Netlist_Add $netlist $net1;
Net_Connect $net1 $inport;

set net2 [new_Net "out"];
Netlist_Add $netlist $net2;
Net_Connect $net2 $outport;

set net3 [new_Net "n1"];
Netlist_Add $netlist $net3;

# Add new library
set primlib [new_Library "myprimitives"];
Libset_Add $libset $primlib;

# Create primitive inv
set invcell [new_Cell "inv"];
Library_Add $primlib $invcell;
set invnetlist [new_Netlist "primitive"]
Cell_Add $invcell $invnetlist;
set Ainport [new_Port "A" $DIR_IN];
Netlist_Add $invnetlist $Ainport
set Zinport [new_Port "Z" $DIR_OUT];
Netlist_Add $invnetlist $Zinport

# Create primitive buff
set buffcell [new_Cell "buff"];
Library_Add $primlib $buffcell;
set buffnetlist [new_Netlist "primitive"];
Cell_Add $buffcell $buffnetlist
set Ainport [new_Port "A" $DIR_IN];
Netlist_Add $buffnetlist $Ainport
set Zinport [new_Port "Z" $DIR_OUT];
Netlist_Add $buffnetlist $Zinport

# Instantiate inv in mynetlist
set inst [Netlist_Add $netlist [new_Instance "inv1" $invnetlist]];
if {$inst!=0} {
set port [Netlist_GetPort $invnetlist "A"];
if {$port!=0} {Net_Connect $net1 $inst $port};
set port [Netlist_GetPort $invnetlist "Z"];
if {$port!=0} {Net_Connect $net3 $inst $port};
}

# Instantiate buff in mynetlist
set inst [Netlist_Add $netlist [new_Instance "buff2" $buffnetlist]];
if {$inst!=0} {
set port [Netlist_GetPort $buffnetlist "A"];
if {$port!=0} {Net_Connect $net3 $inst $port};
set port [Netlist_GetPort $buffnetlist "Z"];
if {$port!=0} {Net_Connect $net2 $inst $port};
}

# Write output netlist
set cellname [DesignObj_Name [Netlist_Owner $netlist]];
set outfilename [append cellname ".v"];
write -format verilog $outfilename;

exit;
</nowiki>
Equivalent Python script:
<nowiki>
#!/usr/bin/python

import sys
sys.path.append('../py')

import Verific

# The global Libset is already at the top of the netlist database.
# No need to create, just get a handle to it.
libset = Verific.Libset_Global()

# Add library. If RTL elaboration has been run, a library has been created
# already. The default library is "work".
lib = Verific.Library("mylib")
lib.thisown = 0
libset.Add(lib)

# Add cell to the library. In the Verilog netlist output, the cell name is the
# same as the module name.
cell = Verific.Cell("mycell")
cell.thisown = 0
lib.Add(cell)

# Add netlist to cell. In the Verilog netlist output, the netlist name doesn't matter.
netlist = Verific.Netlist("mynetlist")
netlist.thisown = 0
cell.Add(netlist)

# Add ports to netlist
inport = Verific.Port("in", Verific.DIR_IN)
inport.thisown = 0
netlist.Add(inport)
outport = Verific.Port("out", Verific.DIR_OUT)
outport.thisown = 0
netlist.Add(outport)

# Add nets (Verilog: wire) to netlist
net1 = Verific.Net("in")
net1.thisown = 0
netlist.Add(net1)
net1.Connect(inport)

net2 = Verific.Net("out")
net2.thisown = 0
netlist.Add(net2)
net2.Connect(outport)

net3 = Verific.Net("n1")
net3.thisown = 0
netlist.Add(net3)

# Add library
primlib = Verific.Library("myprimitives")
primlib.thisown = 0
libset.Add(primlib)

# Create primitive inv
invcell = Verific.Cell("inv")
invcell.thisown = 0
primlib.Add(invcell)
invnetlist = Verific.Netlist("primitive")
invnetlist.thisown = 0
invcell.Add(invnetlist)
Ainport = Verific.Port("A", Verific.DIR_IN)
Ainport.thisown = 0
invnetlist.Add(Ainport)
Zoutport = Verific.Port("Z", Verific.DIR_OUT)
Zoutport.thisown = 0
invnetlist.Add(Zoutport)

# Create primitive buff
buffcell = Verific.Cell("buff")
buffcell.thisown = 0
primlib.Add(buffcell)
buffnetlist = Verific.Netlist("primitive")
buffnetlist.thisown = 0
buffcell.Add(buffnetlist)
Ainport = Verific.Port("A", Verific.DIR_IN)
Ainport.thisown = 0
buffnetlist.Add(Ainport)
Zoutport = Verific.Port("Z", Verific.DIR_OUT)
Zoutport.thisown = 0
buffnetlist.Add(Zoutport)

# Instantiate inv in mynetlist
inst = Verific.Instance("inv1", invnetlist)
inst.thisown = 0
netlist.Add(inst)
if (inst) :
port = invnetlist.GetPort("A")
if (port) :
net1.Connect(inst, port)
port = invnetlist.GetPort("Z")
if (port) :
net3.Connect(inst, port)

# Instantiate buff in mynetlist
inst = Verific.Instance("buff2", buffnetlist)
inst.thisown = 0
netlist.Add(inst)
if (inst) :
port = buffnetlist.GetPort("A")
if (port) :
net3.Connect(inst, port)
port = buffnetlist.GetPort("Z")
if (port) :
net2.Connect(inst, port)

# write netlist
veriWriter = Verific.VeriWrite()
veriWriter.thisown = 0
veriWriter.WriteFile(netlist.Owner().Name()+".v", netlist)

sys.exit(0)
</nowiki>
Output netlist:
<nowiki>
//
// Verific Verilog Description of module newcell
//

module newcell (in, out);
input in;
output out;

wire n1;

inv inv1 (in, n1);
buff buff2 (n1, out);

endmodule

//
// Verific Verilog Description of module inv
//

module inv (A, Z);
input A;
output Z;

endmodule

//
// Verific Verilog Description of module buff
//

module buff (A, Z);
input A;
output Z;

endmodule
</nowiki>

Static elaboration

2023-09-14T21:55:18Z

Alice: Reorganize for clarity

'''Q: What does 'static elaboration' do?'''

Static elaboration runs after analysis. It modifies the parsetree. During static elaboration:

* Identify top-level modules and tree of instantiations under this.
* Defparam statements and module instantiations are processed to calculate the parameter values of the modules for every instantiation.
* Hierarchical names are checked for their validity and usage. These hierarchical names remain in designs.
* Generate statements are processed. For generate unrolled, if/case generate selects the correct concurrent statements to be present in the module.
* Instance arrays are flattened.
* Depending on hierarchical name usage and defparam values the same module gets different signatures. They are replicated and proper values are passed within them hierarchically before attaching them to the corresponding instantiations.
* In each module, parameter values are replaced with constant values by evaluating the constant expression assigned to them. Constant expressions include constant function calls, some system function calls AMS function calls and all operators.
* Function and task calls are checked for their validity (if they are defined in higher level of hierarchy and used in lower level).

Sequential code, blocking assignments, tasks and functions are left as is because they are not part of any static context. Only exception are constant function calls - they are replaced with their return values.

If the purpose of the application is to synthesize the design (RTL elaboration), static elaboration is not needed.

Runtime flag 'veri_replace_const_exprs' when set to 1 is to replace following constant expressions with literals:

* Bounds of packed and unpacked ranges in all data declarations.
* Default values of all declared objects if those are constant.
* Delay values
* Reject and error limits of VeriPathPulse values.
* Indexed expressions only if the indexed expression is a bit-select on the LHS of a continuous assignment or output/inout port of module or gate instantiation.

Using 'veri_replace_const_exprs' makes an extra pass on the elaborated parsetree, increasing total time.

There are other runtime flags controlling static elaboration process, e.g.

veri_cleanup_base_modules
veri_copy_top_before_static_elab
veri_do_not_uniquify_interface_instances
veri_preserve_array_instances
veri_preserve_interface_array_instances
vhdl_uniquify_all_instances
vhdl_copy_top_before_static_elab
vhdl_replace_const_exprs
...

Please see vhdl/VhdlRuntimeFlags.h and verilog/VeriRuntimeFlags.h for a complete list and for more details.