Verific Design Automation FAQ - User contributions [en]

Main Page

2019-07-19T21:33:56Z

Amber:

'''General'''
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? ]]
* [[Release version | How do I tell the version of a Verific software release? ]]
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]

'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
* [[How to get library containing nested module | Verilog: How do I get the library that contains the module nested inside another module?]]
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]]
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
'''Netlist Database'''

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''Scripting languages: TCL, Perl, Python'''
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]

'''Code examples'''
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl: Create a Netlist Database from scratch (not from RTL elaboration)]]
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
* [[Extract clock enable | Database/C++: Extract clock enable]]
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
* [[Type Range example | Verilog/C++: Type Range Example]]
* [[Macro Callback example | Verilog/C++: Macro Callback example]]
* [[Test-based design modification | Verilog/C++: Test-based design modification]]
*[[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree]]
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]

Test-based design modification

2019-07-18T21:00:23Z

Amber: Created page with "C++: <nowiki> #include <iostream> #include "veri_file.h" #include "VeriModule.h" #include "VeriStatement.h" #include "Array.h" #include "Strings.h" #include "TextBasedDes..."

C++:
<nowiki>
#include <iostream>

#include "veri_file.h"

#include "VeriModule.h"
#include "VeriStatement.h"

#include "Array.h"

#include "Strings.h"
#include "TextBasedDesignMod.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

void CommentStmtInParseTree(VeriModule *mod)
{
if (!mod) return ;

Array *mod_items = mod->GetModuleItems() ;
unsigned i ;
VeriModuleItem *item ;
FOREACH_ARRAY_ITEM(mod_items, i, item) {
if (!item) continue ;
// Get statement from the module item (initial block)
VeriStatement *stmt = item->GetStmt() ;
if (!stmt) continue ;
// Get all statements from the statement (squential block in initial block)
Array *stmts = stmt->GetStatements() ;
if (stmts) {
unsigned j ;
VeriStatement *child ;
// Iterate over the child statement:
FOREACH_ARRAY_ITEM(stmts, j, child) {
if (!child) continue ;
// Get the string of the statement:
char *tmp = child->GetPrettyPrintedString() ;
// Remove the last new-line:
unsigned len = Strings::len(tmp) ;
if (!tmp || !len) continue ;
if (tmp[len-1] == '\n') tmp[len-1] = '\0' ;
// Comment out the string:
char *str = Strings::save("/* ", tmp, " */") ;
Strings::free(tmp) ;
// Create a null statement:
VeriStatement *new_stmt = new VeriNullStatement() ;
new_stmt->SetLinefile(child->Linefile()) ;
// Create a comment node with the comment string:
VeriCommentNode *comment = new VeriCommentNode(child->Linefile()) ;
comment->AppendComment(str) ;
Strings::free(str) ;
// Add the comment on the null-statement:
Array *comments = new Array(1) ;
comments->InsertLast(comment) ;
new_stmt->AddComments(comments) ;
// Finally replace the original statement with the created null-statement:
if (!stmt->ReplaceChildStmt(child, new_stmt, 1 /* delete old stmt */)) delete new_stmt ;
}
} else {
// Get the string of the statement:
char *tmp = stmt->GetPrettyPrintedString() ;
// Remove the last new-line:
unsigned len = Strings::len(tmp) ;
if (!tmp || !len) continue ;
if (tmp[len-1] == '\n') tmp[len-1] = '\0' ;
// Comment out the string:
char *str = Strings::save("/* ", tmp, " */") ;
Strings::free(tmp) ;
// Create a null statement:
VeriStatement *new_stmt = new VeriNullStatement() ;
new_stmt->SetLinefile(stmt->Linefile()) ;
// Create a comment node with the comment string:
VeriCommentNode *comment = new VeriCommentNode(stmt->Linefile()) ;
comment->AppendComment(str) ;
Strings::free(str) ;
// Add the comment on the null-statement:
Array *comments = new Array(1) ;
comments->InsertLast(comment) ;
new_stmt->AddComments(comments) ;
// Finally replace the original statement with the created null-statement:
if (!item->ReplaceChildStmt(stmt, new_stmt, 1 /* delete old stmt */)) delete new_stmt ;
}
}

veri_file::PrettyPrint("test_pp.v.golden.new", 0) ;
}

void CommentStmtViaTBDM(VeriModule *mod, TextBasedDesignMod &tbdm)
{
if (!mod) return ;

Array *mod_items = mod->GetModuleItems() ;
unsigned i ;
VeriModuleItem *item ;
FOREACH_ARRAY_ITEM(mod_items, i, item) {
if (!item) continue ;
// Get statement from the module item (initial block)
VeriStatement *stmt = item->GetStmt() ;
if (!stmt) continue ;
// Get all statements from the statement (squential block in initial block)
Array *stmts = stmt->GetStatements() ;
if (stmts) {
unsigned j ;
VeriStatement *child ;
// Iterate over the child statement:
FOREACH_ARRAY_ITEM(stmts, j, child) {
if (!child) continue ;
// Comment the whole statement:
tbdm.InsertBefore(child->Linefile(), "; /* ") ;
tbdm.InsertAfter(child->Linefile(), " */") ;
}
} else {
// Comment the whole statement:
tbdm.InsertBefore(stmt->Linefile(), "; /* ") ;
tbdm.InsertAfter(stmt->Linefile(), " */") ;
}
}
}

int main(int argc, const char **argv)
{
if (!veri_file::Analyze("test.v")) return 1 ;

VeriModule *mod = veri_file::GetModule("test") ;
if (!mod) return 2 ;

CommentStmtInParseTree(mod) ;

TextBasedDesignMod tbdm(0) ;
CommentStmtViaTBDM(mod, tbdm) ;
tbdm.WriteFile("test.v", "test_out.v.golden.new") ;

return 0 ;
}
</nowiki>

Input Verilog:
<nowiki>
module test ;
reg A, b ;
initial
A = b ;
initial
begin
A = b ;
end
endmodule
</nowiki>

Output Verilog:

<nowiki>
module test ;
reg A, b ;
initial
; /* A = b ; */
initial
begin
; /* A = b ; */
end
endmodule
</nowiki>

Main Page

2019-07-18T20:55:06Z

Amber:

'''General'''
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? ]]
* [[Release version | How do I tell the version of a Verific software release? ]]
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]

'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
* [[How to get library containing nested module | Verilog: How do I get the library that contains the module nested inside another module?]]
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]]
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
'''Netlist Database'''

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''Scripting languages: TCL, Perl, Python'''
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]

'''Code examples'''
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl: Create a Netlist Database from scratch (not from RTL elaboration)]]
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
* [[Extract clock enable | Database/C++: Extract clock enable]]
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
* [[Type Range example | Verilog/C++: Type Range Example]]
* [[Macro Callback example | Verilog/C++: Macro Callback example]]
* [[test-based design modification | Verilog/C++: test-based design modification]]
*[[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree]]
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]

Type Range example

2019-07-16T23:41:31Z

C++:
<nowiki>
/*
*
* (c) Copyright 1999 - 2019 Verific Design Automation Inc.
* All rights reserved.
*
* This source code belongs to Verific Design Automation Inc.
* It is considered trade secret and confidential, and is not to be used
* by parties who have not received written authorization
* from Verific Design Automation Inc.
*
* Only authorized users are allowed to use, copy and modify
* this software provided that the above copyright notice
* remains in all copies of this software.
*
*
*/

#include "Map.h" // Make associated hash table class Map available
#include "Set.h" // Make associated hash table class Set available

#include "Message.h" // Make message handlers available

#include "veri_file.h" // Make verilog reader available

#include "DataBase.h" // Make (hierarchical netlist) database API available

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main(int argc, char **argv)
{
RuntimeFlags::SetVar("db_add_id_vs_netbus_map", 1) ;

// Now read in top-level design. In case of failure return.
if (!veri_file::Read("test.sv", "work", veri_file::SYSTEM_VERILOG)) {
// Here, design analysis and elaboration failed
return 1 ;
}

// Get a handle to the top-level netlist
Netlist *top = Netlist::PresentDesign() ;
if (!top) {
Message::PrintLine("cannot find any handle to the top-level netlist") ;
return 4 ;
}

// Print out module that we have handle to
Message::Msg(VERIFIC_INFO, 0, top->Linefile(), "top level design is %s(%s)",
top->Owner()->Name(), top->Name()) ;

// Get the id_vs_netbus table
const Set *out_nets = top->GetIdNets("out") ;
if (!out_nets) {
Message::PrintLine("No nets associated with identifier out") ;
return 5 ;
}

SetIter si ;
DesignObj *net_obj ;
FOREACH_SET_ITEM(out_nets, si, &net_obj) {
if (!net_obj) continue ;
net_obj->Info("Net object name: %s, %s", net_obj->Name(), net_obj->IsNet() ? "net" : "netbus") ;
}

// All done. Wasn't that easy ?
return 0 ;
}
</nowiki>

Input Verilog:
<nowiki>
module struct_test(in, clk, out);
typedef struct {
logic a;
logic b;
logic [5:4] c [4:0];
} my_struct;

input my_struct in [2:0];
output my_struct out [2:0];
input clk;

my_struct r [2:0];
always@(posedge clk)
r <= in;
assign out = r;
endmodule

</nowiki>

Run:
<nowiki>
-- Analyzing Verilog file 'test.sv' (VERI-1482)
test.sv(1): INFO: compiling module 'struct_test' (VERI-1018)
test.sv(1): INFO: top level design is struct_test()
test.sv(9): INFO: Net object name: out[2].a, net
test.sv(9): INFO: Net object name: out[2].b, net
test.sv(9): INFO: Net object name: out[2].c[4], netbus
test.sv(9): INFO: Net object name: out[2].c[3], netbus
test.sv(9): INFO: Net object name: out[2].c[2], netbus
test.sv(9): INFO: Net object name: out[2].c[1], netbus
test.sv(9): INFO: Net object name: out[2].c[0], netbus
test.sv(9): INFO: Net object name: out[1].a, net
test.sv(9): INFO: Net object name: out[1].b, net
test.sv(9): INFO: Net object name: out[1].c[4], netbus
test.sv(9): INFO: Net object name: out[1].c[3], netbus
test.sv(9): INFO: Net object name: out[1].c[2], netbus
test.sv(9): INFO: Net object name: out[1].c[1], netbus
test.sv(9): INFO: Net object name: out[1].c[0], netbus
test.sv(9): INFO: Net object name: out[0].a, net
test.sv(9): INFO: Net object name: out[0].b, net
test.sv(9): INFO: Net object name: out[0].c[4], netbus
test.sv(9): INFO: Net object name: out[0].c[3], netbus
test.sv(9): INFO: Net object name: out[0].c[2], netbus
test.sv(9): INFO: Net object name: out[0].c[1], netbus
test.sv(9): INFO: Net object name: out[0].c[0], netbus
</nowiki>

Main Page

2019-07-16T23:34:57Z

Amber:

'''General'''
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? ]]
* [[Release version | How do I tell the version of a Verific software release? ]]
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]

'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
* [[How to get library containing nested module | Verilog: How do I get the library that contains the module nested inside another module?]]
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]]
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
'''Netlist Database'''

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''Scripting languages: TCL, Perl, Python'''
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]

'''Code examples'''
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl: Create a Netlist Database from scratch (not from RTL elaboration)]]
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
* [[Extract clock enable | Database/C++: Extract clock enable]]
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
* [[Type Range example | Verilog/C++: Type Range Example]]
* [[Macro Callback example | Verilog/C++: Macro Callback example]]
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree]]
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]

Macro Callback example

2019-07-16T23:30:27Z

Amber: Created page with "C++: <nowiki> #include <iostream> #include "veri_file.h" #include "VeriModule.h" #include "VeriVisitor.h" #include "Strings.h" #include "LineFile.h" #include "Message.h" #i..."

C++:
<nowiki>
#include <iostream>

#include "veri_file.h"
#include "VeriModule.h"
#include "VeriVisitor.h"

#include "Strings.h"
#include "LineFile.h"
#include "Message.h"
#include "TextBasedDesignMod.h"

#include "Array.h"
#include "Map.h"
#include "Set.h"

using namespace std ;

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

class MyMacroCallBack : public MacroCallBackHandler
{
public:
MyMacroCallBack() : MacroCallBackHandler(), _last_active_line(0), _last_inactive_line(0) { }
virtual ~MyMacroCallBack() { ReportInactiveArea() ; }

public:
void ReportInactiveArea()
{
if (!_last_active_line || !_last_inactive_line || (_last_active_line > _last_inactive_line)) return ;

Message::Msg(VERIFIC_INFO, 0, 0, "Inactive area [%d-%d]", _last_active_line, _last_inactive_line) ;

_last_active_line = 0 ;
_last_active_line = 0 ;
}

virtual void PredefinedMacroRef(const char *macro_name, unsigned from_active_area, const linefile_type lf)
{
//Message::Msg(VERIFIC_INFO, 0, lf, "Macro %s is being refrenced from %s area", macro_name, ((from_active_area)?"ACTIVE":"INACTIVE")) ;
if (from_active_area) {
if (_last_inactive_line) ReportInactiveArea() ;
_last_active_line = LineFile::GetLineNo(lf) ;
} else if (_last_active_line) {
_last_inactive_line = LineFile::GetLineNo(lf) ;
}
}

protected:
unsigned _last_active_line ;
unsigned _last_inactive_line ;
} ;

int main(int argc, const char **argv)
{
MyMacroCallBack mc ;
veri_file::RegisterCallBackMacro(&mc) ;

veri_file::DefineCmdLineMacro("FORCE_STR") ;

Array files(1) ;
files.Insert("test.v") ;
if (!veri_file::AnalyzeMultipleFiles(&files)) return 1 ;

return 0 ;
}
</nowiki>

Input Verilog:
<nowiki>
module test (in, sel, clk, out);
input [1:0] in;
input clk,sel;
output [1:0] out;

`ifdef FORCE_STR
reg [1:0] a0;
reg [1:0] a1;
always @(posedge clk)
begin
a0 <= in+1;
a1 <= in-1;
end
assign out = sel?a0:a1;

`else
reg [1:0] b0;
reg [1:0] b1;
always @(posedge clk)
begin
b0 <= in+2;
b1 <= in-2;
end
assign out = sel?b0:b1;

`endif

`ifndef FORCE_STR

`else

`endif

endmodule
</nowiki>

Run:

<nowiki>
-- Analyzing Verilog file 'test.v' (VERI-1482)
INFO: Inactive area [16-26]
INFO: Inactive area [28-32]
</nowiki>

Main Page

2019-07-16T23:22:17Z

Amber:

'''General'''
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? ]]
* [[Release version | How do I tell the version of a Verific software release? ]]
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]

'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
* [[How to get library containing nested module | Verilog: How do I get the library that contains the module nested inside another module?]]
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]]
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
'''Netlist Database'''

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''Scripting languages: TCL, Perl, Python'''
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]

'''Code examples'''
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl: Create a Netlist Database from scratch (not from RTL elaboration)]]
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
* [[Extract clock enable | Database/C++: Extract clock enable]]
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
* [[Macro Callback example | Verilog/C++: Macro Callback example]]
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree]]
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]