Verific Design Automation FAQ - User contributions [en]

Modules/design units with " default" suffix in their names

2026-03-11T22:25:39Z

Hoa:

<pre style="color: red"> This article is currently under construction </pre>

'''Q: After static elaboration, there are modules/design units with "_default" or "_1, _2" suffix in their names. Why? And what are they? '''

==== Modules with "_default" suffix ====

Static elaboration process is a multiple-iteration process and modules/design units may be modified differently in each iteration.

We need to keep original version of modules/design units as they are immediately after analysis so that they can be copied for different parameter/generic settings in each iteration and body of copied modules/design units can be elaborated (generate unroll, array instance processing, etc.) differently for each parameter/generic setting.

Another reason to copy instantiated modules/design units with "_default" name is in mixed language elaboration. Here a Verilog module may instantiate a VHDL entity which has been elaborated earlier with different generic values. In that case during Verilog elaboration we will not get original contents of instantiated entity.

Moreover, to support incremental elaboration we need to keep original modules/design units, as lower level units can be elaborated earlier.

In Verilog, we have a runtime-flag "veri_remove_suffix_default_from_copied_module_names" to rename modules from "<orig_name>_default" to "<orig_name>". This will work only when runtime-flag "veri_cleanup_base_modules" is set.

The flag "veri_remove_suffix_default_from_copied_module_names" does not apply to interfaces, packages, and checkers.

==== Interfaces with "_default" suffix ====

SystemVerilog interfaces can be used in any of the following ways :

* As interface instantiations.
* As interface ports.
* As virtual interfaces.
* As hierarchical names.

Interface is always copied with '_default' suffix since we do not know for sure if there is a virtual interface in the hierarchy below which is yet to be processed.

The copied interface (with '_default' suffix) will be the one that is elaborated and specified in the virtual interface declaration, interface instance, or top-level module port. Every instantiated module containing interface type ports will also be copied during static elaboration since its interface port names may have been modified as well.

Virtual interfaces can appear in many different parts of a design, and may or may not be associated with interface instances. Virtual interfaces are not stored in Verific's pseudo-tree, so after static elaboration we do not know whether an interface is used as a virtual interface or not, or where it is being used. Without this knowledge, we cannot arbitrarily change all the references of an interface from '<interface_name>_default' to '<interface_name> because the references may become invalid. Because of this, we do not have flags to remove the '_default' from the interface names as we do for modules.

The '_default_<n>' suffix may also be added due to the presence of hierarchical references in an interface or bind statements containing interface instantiations.

Verific VIPER #19809 has more details.

==== Modules with "_<N>" suffix ====

Modules can be copied with _<N> suffix for hier-ref present/going via them.

Example:
<nowiki>
module top ;
test t () ;
test #(0) t0 () ;
test #(1) t1 () ;
test #(2) t2 () ;
endmodule

module test ;
parameter P = 0 ;
wire [P:0] sig ;
bot b1 () ;
endmodule

module bot ;
initial $display(test.sig) ;
endmodule
</nowiki>

Here "bot" has to be copied 3 times with _<N> suffix so that they can point to 3 different "sig" of 3 different sizes.
The same can happen for bind statements as well. Different bind instances can be added to different instances of the same module.

==== Modules with "_copy<N>" suffix ====

Modules can be copied with _copy<N> suffix when a module with _<N> is already present in the same library.

Example:
<nowiki>
module top ;
test t () ;
test #(0) t0 () ;
test #(1) t1 () ;
test #(2) t2 () ;
endmodule

module test ;
parameter P = 0 ;
wire [P:0] sig ;
bot b1 () ;
endmodule

module bot ;
initial $display(test.sig) ;
endmodule

module bot_2 ;
endmodule
</nowiki>

Here "bot_2" already exists and hence the copied "bot" which we wanted to name "bot_2" is renamed to "bot_copy<N>".

==== Modules with "_<N>_<M>" suffix ====

Modules can even be copied with _<N>_<M> suffix in some corner cases with name conflict as well as hier-refs.

Example:
<nowiki>
module top ;
test t () ;
test #(0) t0 () ;
test #(1) t1 () ;
test #(2) t2 () ;
bot_2 b1 () ;
endmodule

module test ;
parameter P = 0 ;
wire [P:0] sig ;
bot b1 () ;
endmodule

module bot ;
initial $display(test.sig) ;
endmodule

module bot_2 ;
generate
test #(2) t1 () ;
endgenerate
endmodule
</nowiki>

Here instead of "bot_copy<N>", one of the elaborated versions of "bot" which is to be renamed to "bot_2" is actually named as "bot_2_1".

==== How to get the original name or the original module ====

APIs to retrieve the original name of the module or to get the original module itself (only when the original module is available):

<nowiki>
VeriModule::GetOriginalModuleName()
VeriModule::GetOriginalModule()
</nowiki>

Modules/design units with " default" suffix in their names

2026-03-11T22:25:17Z

Hoa:

<pre style="color: red"> This article is currently under construction </pre>

'''Q: After static elaboration, there are modules/design units with "_default" or "_1, _2" suffix in their names. Why? And what are they? '''

==== Modules with "_default" suffix ====

Static elaboration process is a multiple-iteration process and modules/design units may be modified differently in each iteration.

We need to keep original version of modules/design units as they are immediately after analysis so that they can be copied for different parameter/generic settings in each iteration and body of copied modules/design units can be elaborated (generate unroll, array instance processing, etc.) differently for each parameter/generic setting.

Another reason to copy instantiated modules/design units with "_default" name is in mixed language elaboration. Here a Verilog module may instantiate a VHDL entity which has been elaborated earlier with different generic values. In that case during Verilog elaboration we will not get original contents of instantiated entity.

Moreover, to support incremental elaboration we need to keep original modules/design units, as lower level units can be elaborated earlier.

In Verilog, we have a runtime-flag "veri_remove_suffix_default_from_copied_module_names" to rename modules from "<orig_name>_default" to "<orig_name>". This will work only when runtime-flag "veri_cleanup_base_modules" is set. Also, the flag "veri_remove_suffix_default_from_copied_module_names" does not apply to interfaces, packages, and checkers.

==== Interfaces with "_default" suffix ====

SystemVerilog interfaces can be used in any of the following ways :

* As interface instantiations.
* As interface ports.
* As virtual interfaces.
* As hierarchical names.

Interface is always copied with '_default' suffix since we do not know for sure if there is a virtual interface in the hierarchy below which is yet to be processed.

The copied interface (with '_default' suffix) will be the one that is elaborated and specified in the virtual interface declaration, interface instance, or top-level module port. Every instantiated module containing interface type ports will also be copied during static elaboration since its interface port names may have been modified as well.

Virtual interfaces can appear in many different parts of a design, and may or may not be associated with interface instances. Virtual interfaces are not stored in Verific's pseudo-tree, so after static elaboration we do not know whether an interface is used as a virtual interface or not, or where it is being used. Without this knowledge, we cannot arbitrarily change all the references of an interface from '<interface_name>_default' to '<interface_name> because the references may become invalid. Because of this, we do not have flags to remove the '_default' from the interface names as we do for modules.

The '_default_<n>' suffix may also be added due to the presence of hierarchical references in an interface or bind statements containing interface instantiations.

Verific VIPER #19809 has more details.

==== Modules with "_<N>" suffix ====

Modules can be copied with _<N> suffix for hier-ref present/going via them.

Example:
<nowiki>
module top ;
test t () ;
test #(0) t0 () ;
test #(1) t1 () ;
test #(2) t2 () ;
endmodule

module test ;
parameter P = 0 ;
wire [P:0] sig ;
bot b1 () ;
endmodule

module bot ;
initial $display(test.sig) ;
endmodule
</nowiki>

Here "bot" has to be copied 3 times with _<N> suffix so that they can point to 3 different "sig" of 3 different sizes.
The same can happen for bind statements as well. Different bind instances can be added to different instances of the same module.

==== Modules with "_copy<N>" suffix ====

Modules can be copied with _copy<N> suffix when a module with _<N> is already present in the same library.

Example:
<nowiki>
module top ;
test t () ;
test #(0) t0 () ;
test #(1) t1 () ;
test #(2) t2 () ;
endmodule

module test ;
parameter P = 0 ;
wire [P:0] sig ;
bot b1 () ;
endmodule

module bot ;
initial $display(test.sig) ;
endmodule

module bot_2 ;
endmodule
</nowiki>

Here "bot_2" already exists and hence the copied "bot" which we wanted to name "bot_2" is renamed to "bot_copy<N>".

==== Modules with "_<N>_<M>" suffix ====

Modules can even be copied with _<N>_<M> suffix in some corner cases with name conflict as well as hier-refs.

Example:
<nowiki>
module top ;
test t () ;
test #(0) t0 () ;
test #(1) t1 () ;
test #(2) t2 () ;
bot_2 b1 () ;
endmodule

module test ;
parameter P = 0 ;
wire [P:0] sig ;
bot b1 () ;
endmodule

module bot ;
initial $display(test.sig) ;
endmodule

module bot_2 ;
generate
test #(2) t1 () ;
endgenerate
endmodule
</nowiki>

Here instead of "bot_copy<N>", one of the elaborated versions of "bot" which is to be renamed to "bot_2" is actually named as "bot_2_1".

==== How to get the original name or the original module ====

APIs to retrieve the original name of the module or to get the original module itself (only when the original module is available):

<nowiki>
VeriModule::GetOriginalModuleName()
VeriModule::GetOriginalModule()
</nowiki>

Modules/design units with " default" suffix in their names

2026-03-11T22:24:59Z

Hoa:

<pre style="color: red"> This article is currently under construction </pre>

'''Q: After static elaboration, there are modules/design units with "_default" or "_1, _2" suffix in their names. Why? And what are they? '''

==== Modules with "_default" suffix ====

Static elaboration process is a multiple-iteration process and modules/design units may be modified differently in each iteration.

We need to keep original version of modules/design units as they are immediately after analysis so that they can be copied for different parameter/generic settings in each iteration and body of copied modules/design units can be elaborated (generate unroll, array instance processing, etc.) differently for each parameter/generic setting.

Another reason to copy instantiated modules/design units with "_default" name is in mixed language elaboration. Here a Verilog module may instantiate a VHDL entity which has been elaborated earlier with different generic values. In that case during Verilog elaboration we will not get original contents of instantiated entity.

Moreover, to support incremental elaboration we need to keep original modules/design units, as lower level units can be elaborated earlier.

In Verilog, we have a runtime-flag "veri_remove_suffix_default_from_copied_module_names" to rename modules from "<orig_name>_default" to "<orig_name>". This will work only when runtime-flag "veri_cleanup_base_modules" is set. Also, the flag "veri_remove_suffix_default_from_copied_module_names" does not applied to interfaces, packages, and checkers.

==== Interfaces with "_default" suffix ====

SystemVerilog interfaces can be used in any of the following ways :

* As interface instantiations.
* As interface ports.
* As virtual interfaces.
* As hierarchical names.

Interface is always copied with '_default' suffix since we do not know for sure if there is a virtual interface in the hierarchy below which is yet to be processed.

The copied interface (with '_default' suffix) will be the one that is elaborated and specified in the virtual interface declaration, interface instance, or top-level module port. Every instantiated module containing interface type ports will also be copied during static elaboration since its interface port names may have been modified as well.

Virtual interfaces can appear in many different parts of a design, and may or may not be associated with interface instances. Virtual interfaces are not stored in Verific's pseudo-tree, so after static elaboration we do not know whether an interface is used as a virtual interface or not, or where it is being used. Without this knowledge, we cannot arbitrarily change all the references of an interface from '<interface_name>_default' to '<interface_name> because the references may become invalid. Because of this, we do not have flags to remove the '_default' from the interface names as we do for modules.

The '_default_<n>' suffix may also be added due to the presence of hierarchical references in an interface or bind statements containing interface instantiations.

Verific VIPER #19809 has more details.

==== Modules with "_<N>" suffix ====

Modules can be copied with _<N> suffix for hier-ref present/going via them.

Example:
<nowiki>
module top ;
test t () ;
test #(0) t0 () ;
test #(1) t1 () ;
test #(2) t2 () ;
endmodule

module test ;
parameter P = 0 ;
wire [P:0] sig ;
bot b1 () ;
endmodule

module bot ;
initial $display(test.sig) ;
endmodule
</nowiki>

Here "bot" has to be copied 3 times with _<N> suffix so that they can point to 3 different "sig" of 3 different sizes.
The same can happen for bind statements as well. Different bind instances can be added to different instances of the same module.

==== Modules with "_copy<N>" suffix ====

Modules can be copied with _copy<N> suffix when a module with _<N> is already present in the same library.

Example:
<nowiki>
module top ;
test t () ;
test #(0) t0 () ;
test #(1) t1 () ;
test #(2) t2 () ;
endmodule

module test ;
parameter P = 0 ;
wire [P:0] sig ;
bot b1 () ;
endmodule

module bot ;
initial $display(test.sig) ;
endmodule

module bot_2 ;
endmodule
</nowiki>

Here "bot_2" already exists and hence the copied "bot" which we wanted to name "bot_2" is renamed to "bot_copy<N>".

==== Modules with "_<N>_<M>" suffix ====

Modules can even be copied with _<N>_<M> suffix in some corner cases with name conflict as well as hier-refs.

Example:
<nowiki>
module top ;
test t () ;
test #(0) t0 () ;
test #(1) t1 () ;
test #(2) t2 () ;
bot_2 b1 () ;
endmodule

module test ;
parameter P = 0 ;
wire [P:0] sig ;
bot b1 () ;
endmodule

module bot ;
initial $display(test.sig) ;
endmodule

module bot_2 ;
generate
test #(2) t1 () ;
endgenerate
endmodule
</nowiki>

Here instead of "bot_copy<N>", one of the elaborated versions of "bot" which is to be renamed to "bot_2" is actually named as "bot_2_1".

==== How to get the original name or the original module ====

APIs to retrieve the original name of the module or to get the original module itself (only when the original module is available):

<nowiki>
VeriModule::GetOriginalModuleName()
VeriModule::GetOriginalModule()
</nowiki>

Remove Verific data structures

2026-01-14T19:08:44Z

Hoa:

'''Q: How do I remove all Verific data structures in memory?'''

To remove hdl file sorting data:

hdl_file_sort::Reset();

To reset file system cache:

FileSystem::ResetDirectoryCache();

To remove Verilog parsetree:

veri_file::Reset();

To remove VHDL parsetree:

vhdl_file::Reset();

To remove synlib parsetree:

synlib_file::Reset();

To remove hierarchy tree:

hier_tree::DeleteHierarchicalTree() ;

To remove UPF data structures:

upf_file::DeleteAll();

To remove the netlist database:

Libset::Reset();

To remove linefile data (make sure that you've removed all parsetrees and the netlist database):

LineFile::DeleteAllLineFiles();
LineFile::ResetFileIdMaps();
#if defined(VERIFIC_LINEFILE_INCLUDES_COLUMNS) || defined(VERIFIC_LARGE_LINEFILE)
ColLineFile::DeleteAllLineFiles() ;
#endif

To remove message type settings:

Message::Reset();

To reset run-time flags:

RuntimeFlags::DeleteAllFlags();

How to save computer resources

2026-01-12T17:54:21Z

Hoa:

There are compile flags & runtime flags that may help to reduce memory consumption and/or runtime.
Below are some common ones.

- Compile flag "VERIFIC_MEMORY_MANAGER" in util/VerificSystem.h
Highly recommended.

Enables the new, zero-overhead, Verific memory manager. Typically reduces memory usage of the Verific software by an additional 20% over the default system memory manager.
- Compile flag "DB_USE_PORT_ORDERED_PORTREF" in database/DBCompileFlags.h
Highly recommended.

Organizes the PortRef structures in an ordered array rather than a hash table. This saves a significant amount of memory since PortRefs are no longer individually allocated,
and the overhead of a hash table is also saved.

- Compile flag "VERILOG_QUICK_PARSE_V_FILES" in verilog/VeriCompileFlags.h
Normally a -v file may contain multiple module definitions. The Verilog parser is supposed to pick only the required modules from that file.

However, the file may not contain any of the required modules; instead it is a large file containing many other modules of no interest. In such a case, analyzing and creating a parse tree for the full file will consume much time and memory.

To prevent this, we provide this compile flag to quickly parse the file and see if it is actually required or not, without creating the parse tree. If it is not required we will ignore the file, otherwise we will fully parse it and pick the required modules.

- Compile flag "VERIFIC_LINEFILE_INCLUDES_COLUMNS" in util/VerificSystem.h
If you don't need the starting and ending locations including column info, turn this flag off.

For more details, see [[LineFile data from input files|LineFile data from input files]]
- Runtime flag "veri_improve_include_dir_processing_runtime_for_network_file_system"
Adds directory caching for include directories with simple files (files without a directory specification).

We read the contents of the directory on first encountering it while checking for an include file. Subsequent searches will find the file in the cache instead of the actual disk.

The cache is automatically cleared at the end of the veri_file::Analyze() or veri_file::AnalyzeMultipleFiles() calls. Note that we cannot keep it alive after these two analyze calls since there could possibly be a chdir() call which would make the cache invalid.
- Runtime flag "veri_share_nodes_in_static_elab"

Reduces memory and runtime for large designs. This flag will ensure that only one node will be created in static elaboration for each unique signature of a module, regardless of whether it is a top module or instantiated. The number of nodes that can be reduced depends on the nature of the design. For more details on this flag check [https://www.verific.com/faq/index.php?title=Parse_tree_node_sharing_in_Static_Elaboration here]

- Runtime flag "veri_ignore_always_constructs"

This enables a "light-weighed" RTL elaboration. "always" constructs in the input RTL Verilog file will be skipped over.

The output netlist is not complete, but is useful if you are interested only in module interfaces and instantiations.

Note that this flag is active only during RTL elaboration, not analysis. The input files still need to be Verilog-legal.

- Runtime flag "edif_delete_view_contents_after_processing"

For EDIF input.

Highly recommended.

Deletes the "contents" of a "view" after processing it, i.e., after creating the netlist. We still keep the "interface", i.e., ports alive so that the view can be instantiated.

- Runtime flag "edif_link_case_insensitive"

For EDIF input.

EDIF LRM does not define how existing external cells (maybe parsed from another language) should be linked to EDIF cells. We implemented case-insensitive (linear) search for these, which causes an N^2 complexity problem that slows down the reader for very large designs. Switching to case-sensitive search significantly speeds up the process, but there may be incidental cases where the EDIF reader does not link to an existing cell parsed from a different file.

- Runtime flag "edif_keep_existing_view"

For EDIF input.

When stitching designs from multiple files, a view may be defined in more than one file. By default ("edif_keep_existing_view" disabled), the view being currently read survives, replacing the existing view. This may slow down the process because the existing view and all of its references in the Netlist Database has to be updated.

Enabling "edif_keep_existing_view" allows the reader to ignore the (duplicated) view being currently read. All references to the view being ignored will be updated to point to the existing view in the Netlist Database. Only the references to the current view (in the current read operation) need to be updated to point to the existing view.

How to evaluate a Verilog expression

2025-09-03T21:44:48Z

Hoa:

Evaluating a Verilog expression requires 'Static Elaboration' or 'Hierarchy Tree' feature.

In the example below, a, b, and c are declared in the Verilog module. There is no need to run static elaboration on the whole module. But 'Static Elaboration' feature is still required because the API VeriExpression::StaticEvaluate() is available only with 'Static Elaboration' feature.

C++:
<nowiki>
#include "veri_file.h"
#include "VeriExpression.h"
#include "VeriModule.h"
#include "VeriBaseValue_Stat.h"

#include "Strings.h"
#include "Array.h"
#include "Map.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main(int argc, const char **argv)
{
const char *file_name = (argc > 1) ? argv[1] : "test.v" ;
const char *module_name = (argc > 2) ? argv[2] : "test_module" ;

Array files(1) ;
files.Insert(file_name) ;
if (!veri_file::AnalyzeMultipleFiles(&files, veri_file::SYSTEM_VERILOG)) return 1 ;

const VeriModule *mod = veri_file::GetModule(module_name) ;
if (!mod) return 2 ;

// Apply following known values to evaluate "a[b] + c":
// a = {1'b1, 1'b1}
// b = 2'b00
// c = 2'b01

const char *expr_string = "a[b] + c" ;
Map known_values(STRING_HASH) ;
(void) known_values.Insert("a", "{1'b1, 1'b1}") ;
(void) known_values.Insert("b", "2'b00") ;
(void) known_values.Insert("c", "2'b01") ;

ValueTable df ;

MapIter mi ;
const char *id_name ;
const char *val_str ;
FOREACH_MAP_ITEM(&known_values, mi, &id_name, &val_str) {
if (!id_name || !val_str) continue ;

// Find the identifier:
VeriIdDef *id = mod->FindDeclared(id_name) ;
if (!id) return 3 ;

// Create the expression:
VeriExpression *expr = veri_file::AnalyzeExpr(val_str, veri_file::SYSTEM_VERILOG) ;
if (!expr) return 4 ;

// Evaluate the expression:
// If this is a literal expression, we do not need the value value or Resolve() call or else we need both:
VeriBaseValue *val = expr->StaticEvaluate(0 /* self context */, 0 /* value table */) ;
delete expr ;
if (!val) return 5 ;

// Insert into the table to be used later:
if (!df.Insert(id, val)) {
delete val ;
return 6 ;
}
}

// Now create the expression for to be evaluated:
VeriExpression *expr = veri_file::AnalyzeExpr(expr_string, veri_file::SYSTEM_VERILOG) ;
if (!expr) return 7 ;

// Resolve the expression so that the id-refs are resolved:
expr->Resolve(mod->GetScope(), VeriTreeNode::VERI_UNDEF_ENV) ;

VeriBaseValue *val = expr->StaticEvaluate(0 /* self context */, &df /* use this table with the known values */) ;
delete expr ;
if (!val) return 8 ; // Failed to evaluate

char *image = val->Image() ;
int result = val->GetIntegerValue() ;
mod->Info("Evaluated value: %s (%d)", ((image)?image:""), result) ;
Strings::free(image) ;
delete val ;

return 0 ;
}
</nowiki>

Verilog testcase:

<nowiki>
module test_module;
wire a [1:0];
wire [1:0] b;
wire [1:0] c;
endmodule
</nowiki>

Run:

<nowiki>
$ test-linux
-- Analyzing Verilog file 'test.v' (VERI-1482)
test.v(5): INFO: Evaluated value: 2'b10 (2)
$
</nowiki>

If an element in the expression to be evaluated crosses module boundaries, elaboration needs to be run as in the Verilog testcase below ('my_int' is to be evaluated):

<nowiki>
interface ifc #(int N=10);
logic [N-1:0] data;
endinterface

module test();
ifc #(.N(13)) I();
int my_int = $bits(I.data); // want to evaluated 'my_int' or '$bits(I.data)'
endmodule
</nowiki>

The C++ example below calls static elaboration:

<nowiki>
#include "veri_file.h"
#include "VeriModule.h"
#include "VeriVisitor.h"
#include "VeriExpression.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

class MyVisitor : public VeriVisitor
{
public:
MyVisitor() : VeriVisitor() { }
virtual ~MyVisitor() { }

virtual void VERI_VISIT(VeriExpression, node)
{
char *str = node.GetPrettyPrintedString() ;
VeriExpression *new_exp = node.StaticEvaluateToExpr(0,0,0);
if (new_exp) {
char *str2 = new_exp->GetPrettyPrintedString() ;
node.Info(" Expression: '%s', evaluated to '%s'", str, str2) ;
Strings::free(str) ;
Strings::free(str2) ;
}
}
} ;

int main (int argc, char **argv)
{
const char *file_name = "test.sv" ; // defaulf input filename
if (argc > 1) file_name = argv[1] ; // Set the file name as specified by the user
if (!veri_file::Analyze(file_name, veri_file::SYSTEM_VERILOG)) return 1 ;

if (!veri_file::ElaborateAllStatic()) return 1 ;

MyVisitor mv ;

VeriModule *mod = veri_file::GetModule("test") ;
if (!mod) return 2 ;
mod->Info("In module '%s'", mod->Name()) ;
mod->Accept(mv) ;
return 0 ;
}
</nowiki>

Run:
<nowiki>
$ test-linux
-- Analyzing Verilog file 'test.sv' (VERI-1482)
test.sv(5): INFO: compiling module 'test' (VERI-1018)
test.sv(8): INFO: In module 'test'
test.sv(7): INFO: Expression: 'int ', evaluated to 'int '
test.sv(7): INFO: Expression: '$bits(I.data)', evaluated to '13'
$
</nowiki>

If for some reason static elaboration is not desirable (it does take memory and CPU time), hierarchy-tree elaboration can be run instead. Hierarchy-tree elaboration takes much less memory anc CPU time than static elaborations does.

Reference: https://www.verific.com/docs/index.php?title=Hierarchy_Tree

The C++ example below uses hierarchy-tree elaboration instead of static elaboration:

C++:
<nowiki>
#include "veri_file.h"
#include "VeriModule.h"
#include "VeriId.h"
#include "VeriExpression.h"
#include "VeriBaseValue_Stat.h"
#include "hier_tree.h"
#include "HierTreeNode.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main(int argc, const char **argv)
{
const char *file_name = "test.sv" ;
const char *top_name = "test" ;
const char *my_name = "my_int" ;

if (!veri_file::Analyze(file_name, veri_file::SYSTEM_VERILOG)) return 1 ;

VeriModule *top = veri_file::GetModule(top_name) ;
if (!top) return 2 ;

VeriIdDef *my_id = top->FindDeclared(my_name) ;
if (!my_id) return 3 ;

VeriExpression *init_val = my_id->GetInitialValue() ;
if (!init_val) return 4 ;

Array top_mods(1) ;
top_mods.Insert(top) ;

const Map *top_nodes = hier_tree::CreateHierarchicalTree(&top_mods, 0, 0, 0) ;
if (!top_nodes) return 5 ;

HierTreeNode *top_node = (HierTreeNode *)top_nodes->GetValue(top_name) ;
if (!top_node) {
hier_tree::DeleteHierarchicalTree() ;
return 6 ;
}

InterfaceInfo *info = top_node->GetParamValue(my_id) ;
VeriBaseValue *val = 0 ;
VeriBaseValue *delete_val = 0 ;
if (info) {
// We already have the value evaluated, get from node:
val = info->GetVeriEvaluatedValue() ;
} else {
// Need to evaluate the value, use the context from the node:
Map *context = top_node->PushContext() ;
hier_tree::PushNode(top_node) ;

val = init_val->StaticEvaluate(0, 0, 0, 0) ;
delete_val = val ;

hier_tree::PopNode() ;
top_node->PopContext(context) ;
}

char *val_img = (val) ? val->Image() : 0 ;
init_val->Info("%s(%s) evaluated to %s", my_name, my_id->GetPrettyPrintedString(), ((val_img)?val_img:"<NULL>")) ;
Strings::free(val_img) ;

delete delete_val ;

hier_tree::DeleteHierarchicalTree() ;

return 0 ;
}
</nowiki>

Run:
<nowiki>
$ test-linux
-- Analyzing Verilog file 'test.sv' (VERI-1482)
test.sv(7): INFO: my_int(my_int = $bits(I.data)) evaluated to 13
$
</nowiki>

How to evaluate a Verilog expression

2025-09-03T21:39:56Z

Hoa:

Evaluating a Verilog expression requires 'Static Elaboration' or 'Hierarchy Tree' feature.

In the example below, a, b, and c are declared in the Verilog module. There is no need to run static elaboration on the whole module. But 'Static Elaboration' feature is still required because the API VeriExpression::StaticEvaluate() is available only with 'Static Elaboration' feature.

C++:
<nowiki>
#include "veri_file.h"
#include "VeriExpression.h"
#include "VeriModule.h"
#include "VeriBaseValue_Stat.h"

#include "Strings.h"
#include "Array.h"
#include "Map.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main(int argc, const char **argv)
{
const char *file_name = (argc > 1) ? argv[1] : "test.v" ;
const char *module_name = (argc > 2) ? argv[2] : "test_module" ;

Array files(1) ;
files.Insert(file_name) ;
if (!veri_file::AnalyzeMultipleFiles(&files, veri_file::SYSTEM_VERILOG)) return 1 ;

const VeriModule *mod = veri_file::GetModule(module_name) ;
if (!mod) return 2 ;

// Apply following known values to evaluate "a[b] + c":
// a = {1'b1, 1'b1}
// b = 2'b00
// c = 2'b01

const char *expr_string = "a[b] + c" ;
Map known_values(STRING_HASH) ;
(void) known_values.Insert("a", "{1'b1, 1'b1}") ;
(void) known_values.Insert("b", "2'b00") ;
(void) known_values.Insert("c", "2'b01") ;

ValueTable df ;

MapIter mi ;
const char *id_name ;
const char *val_str ;
FOREACH_MAP_ITEM(&known_values, mi, &id_name, &val_str) {
if (!id_name || !val_str) continue ;

// Find the identifier:
VeriIdDef *id = mod->FindDeclared(id_name) ;
if (!id) return 3 ;

// Create the expression:
VeriExpression *expr = veri_file::AnalyzeExpr(val_str, veri_file::SYSTEM_VERILOG) ;
if (!expr) return 4 ;

// Evaluate the expression:
// If this is a literal expression, we do not need the value value or Resolve() call or else we need both:
VeriBaseValue *val = expr->StaticEvaluate(0 /* self context */, 0 /* value table */) ;
delete expr ;
if (!val) return 5 ;

// Insert into the table to be used later:
if (!df.Insert(id, val)) {
delete val ;
return 6 ;
}
}

// Now create the expression for to be evaluated:
VeriExpression *expr = veri_file::AnalyzeExpr(expr_string, veri_file::SYSTEM_VERILOG) ;
if (!expr) return 7 ;

// Resolve the expression so that the id-refs are resolved:
expr->Resolve(mod->GetScope(), VeriTreeNode::VERI_UNDEF_ENV) ;

VeriBaseValue *val = expr->StaticEvaluate(0 /* self context */, &df /* use this table with the known values */) ;
delete expr ;
if (!val) return 8 ; // Failed to evaluate

char *image = val->Image() ;
int result = val->GetIntegerValue() ;
mod->Info("Evaluated value: %s (%d)", ((image)?image:""), result) ;
Strings::free(image) ;
delete val ;

return 0 ;
}
</nowiki>

Verilog testcase:

<nowiki>
module test_module;
wire a [1:0];
wire [1:0] b;
wire [1:0] c;
endmodule
</nowiki>

Run:

<nowiki>
$ test-linux
-- Analyzing Verilog file 'test.v' (VERI-1482)
test.v(5): INFO: Evaluated value: 2'b10 (2)
$
</nowiki>

If an element in the expression crosses module boundaries, elaboration needs to be run as in the example below:

Verilog testcase:

<nowiki>
interface ifc #(int N=10);
logic [N-1:0] data;
endinterface

module test();
ifc #(.N(13)) I();
int my_int = $bits(I.data);
endmodule
</nowiki>

The C++ example below calls static elaboration:

<nowiki>
#include "veri_file.h"
#include "VeriModule.h"
#include "VeriVisitor.h"
#include "VeriExpression.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

class MyVisitor : public VeriVisitor
{
public:
MyVisitor() : VeriVisitor() { }
virtual ~MyVisitor() { }

virtual void VERI_VISIT(VeriExpression, node)
{
char *str = node.GetPrettyPrintedString() ;
VeriExpression *new_exp = node.StaticEvaluateToExpr(0,0,0);
if (new_exp) {
char *str2 = new_exp->GetPrettyPrintedString() ;
node.Info(" Expression: '%s', evaluated to '%s'", str, str2) ;
Strings::free(str) ;
Strings::free(str2) ;
}
}
} ;

int main (int argc, char **argv)
{
const char *file_name = "test.sv" ; // defaulf input filename
if (argc > 1) file_name = argv[1] ; // Set the file name as specified by the user
if (!veri_file::Analyze(file_name, veri_file::SYSTEM_VERILOG)) return 1 ;

if (!veri_file::ElaborateAllStatic()) return 1 ;

MyVisitor mv ;

VeriModule *mod = veri_file::GetModule("test") ;
if (!mod) return 2 ;
mod->Info("In module '%s'", mod->Name()) ;
mod->Accept(mv) ;
return 0 ;
}
</nowiki>

Run:
<nowiki>
$ test-linux
-- Analyzing Verilog file 'test.sv' (VERI-1482)
test.sv(5): INFO: compiling module 'test' (VERI-1018)
test.sv(8): INFO: In module 'test'
test.sv(7): INFO: Expression: 'int ', evaluated to 'int '
test.sv(7): INFO: Expression: '$bits(I.data)', evaluated to '13'
$
</nowiki>

If for some reason static elaboration is not desirable (it does take memory and CPU time), hierarchy-tree elaboration can be run instead. Hierarchy-tree elaboration takes much less memory anc CPU time than static elaborations does.

Reference: https://www.verific.com/docs/index.php?title=Hierarchy_Tree

The C++ example below uses hierarchy-tree elaboration:

C++:
<nowiki>
#include "veri_file.h"
#include "VeriModule.h"
#include "VeriId.h"
#include "VeriExpression.h"
#include "VeriBaseValue_Stat.h"
#include "hier_tree.h"
#include "HierTreeNode.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main(int argc, const char **argv)
{
const char *file_name = "test.sv" ;
const char *top_name = "test" ;
const char *my_name = "my_int" ;

if (!veri_file::Analyze(file_name, veri_file::SYSTEM_VERILOG)) return 1 ;

VeriModule *top = veri_file::GetModule(top_name) ;
if (!top) return 2 ;

VeriIdDef *my_id = top->FindDeclared(my_name) ;
if (!my_id) return 3 ;

VeriExpression *init_val = my_id->GetInitialValue() ;
if (!init_val) return 4 ;

Array top_mods(1) ;
top_mods.Insert(top) ;

const Map *top_nodes = hier_tree::CreateHierarchicalTree(&top_mods, 0, 0, 0) ;
if (!top_nodes) return 5 ;

HierTreeNode *top_node = (HierTreeNode *)top_nodes->GetValue(top_name) ;
if (!top_node) {
hier_tree::DeleteHierarchicalTree() ;
return 6 ;
}

InterfaceInfo *info = top_node->GetParamValue(my_id) ;
VeriBaseValue *val = 0 ;
VeriBaseValue *delete_val = 0 ;
if (info) {
// We already have the value evaluated, get from node:
val = info->GetVeriEvaluatedValue() ;
} else {
// Need to evaluate the value, use the context from the node:
Map *context = top_node->PushContext() ;
hier_tree::PushNode(top_node) ;

val = init_val->StaticEvaluate(0, 0, 0, 0) ;
delete_val = val ;

hier_tree::PopNode() ;
top_node->PopContext(context) ;
}

char *val_img = (val) ? val->Image() : 0 ;
init_val->Info("%s(%s) evaluated to %s", my_name, my_id->GetPrettyPrintedString(), ((val_img)?val_img:"<NULL>")) ;
Strings::free(val_img) ;

delete delete_val ;

hier_tree::DeleteHierarchicalTree() ;

return 0 ;
}
</nowiki>

Run:
<nowiki>
$ test-linux
-- Analyzing Verilog file 'test.sv' (VERI-1482)
test.sv(7): INFO: my_int(my_int = $bits(I.data)) evaluated to 13
$
</nowiki>

How to evaluate a Verilog expression

2025-09-03T21:38:35Z

Hoa:

Evaluating a Verilog expression requires 'Static Elaboration' or 'Hierarchy Tree' feature.

In the example below, a, b, and c are declared in the Verilog module. There is no need to run static elaboration on the whole module. But 'Static Elaboration' feature is still required because the API VeriExpression::StaticEvaluate() is available only with 'Static Elaboration' feature.

C++:
<nowiki>
#include "veri_file.h"
#include "VeriExpression.h"
#include "VeriModule.h"
#include "VeriBaseValue_Stat.h"

#include "Strings.h"
#include "Array.h"
#include "Map.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main(int argc, const char **argv)
{
const char *file_name = (argc > 1) ? argv[1] : "test.v" ;
const char *module_name = (argc > 2) ? argv[2] : "test_module" ;

Array files(1) ;
files.Insert(file_name) ;
if (!veri_file::AnalyzeMultipleFiles(&files, veri_file::SYSTEM_VERILOG)) return 1 ;

const VeriModule *mod = veri_file::GetModule(module_name) ;
if (!mod) return 2 ;

// Apply following known values to evaluate "a[b] + c":
// a = {1'b1, 1'b1}
// b = 2'b00
// c = 2'b01

const char *expr_string = "a[b] + c" ;
Map known_values(STRING_HASH) ;
(void) known_values.Insert("a", "{1'b1, 1'b1}") ;
(void) known_values.Insert("b", "2'b00") ;
(void) known_values.Insert("c", "2'b01") ;

ValueTable df ;

MapIter mi ;
const char *id_name ;
const char *val_str ;
FOREACH_MAP_ITEM(&known_values, mi, &id_name, &val_str) {
if (!id_name || !val_str) continue ;

// Find the identifier:
VeriIdDef *id = mod->FindDeclared(id_name) ;
if (!id) return 3 ;

// Create the expression:
VeriExpression *expr = veri_file::AnalyzeExpr(val_str, veri_file::SYSTEM_VERILOG) ;
if (!expr) return 4 ;

// Evaluate the expression:
// If this is a literal expression, we do not need the value value or Resolve() call or else we need both:
VeriBaseValue *val = expr->StaticEvaluate(0 /* self context */, 0 /* value table */) ;
delete expr ;
if (!val) return 5 ;

// Insert into the table to be used later:
if (!df.Insert(id, val)) {
delete val ;
return 6 ;
}
}

// Now create the expression for to be evaluated:
VeriExpression *expr = veri_file::AnalyzeExpr(expr_string, veri_file::SYSTEM_VERILOG) ;
if (!expr) return 7 ;

// Resolve the expression so that the id-refs are resolved:
expr->Resolve(mod->GetScope(), VeriTreeNode::VERI_UNDEF_ENV) ;

VeriBaseValue *val = expr->StaticEvaluate(0 /* self context */, &df /* use this table with the known values */) ;
delete expr ;
if (!val) return 8 ; // Failed to evaluate

char *image = val->Image() ;
int result = val->GetIntegerValue() ;
mod->Info("Evaluated value: %s (%d)", ((image)?image:""), result) ;
Strings::free(image) ;
delete val ;

return 0 ;
}
</nowiki>

Verilog testcase:

<nowiki>
module test_module;
wire a [1:0];
wire [1:0] b;
wire [1:0] c;
endmodule
</nowiki>

Run:

<nowiki>
$ test-linux
-- Analyzing Verilog file 'test.v' (VERI-1482)
test.v(5): INFO: Evaluated value: 2'b10 (2)
$
</nowiki>

If an element in the expression crosses module boundaries, elaboration needs to be run as in the example below:

Verilog testcase:

<nowiki>
interface ifc #(int N=10);
logic [N-1:0] data;
endinterface

module test();
ifc #(.N(13)) I();
int my_int = $bits(I.data);
endmodule
</nowiki>

C++:
<nowiki>
#include "veri_file.h"
#include "VeriModule.h"
#include "VeriVisitor.h"
#include "VeriExpression.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

class MyVisitor : public VeriVisitor
{
public:
MyVisitor() : VeriVisitor() { }
virtual ~MyVisitor() { }

virtual void VERI_VISIT(VeriExpression, node)
{
char *str = node.GetPrettyPrintedString() ;
VeriExpression *new_exp = node.StaticEvaluateToExpr(0,0,0);
if (new_exp) {
char *str2 = new_exp->GetPrettyPrintedString() ;
node.Info(" Expression: '%s', evaluated to '%s'", str, str2) ;
Strings::free(str) ;
Strings::free(str2) ;
}
}
} ;

int main (int argc, char **argv)
{
const char *file_name = "test.sv" ; // defaulf input filename
if (argc > 1) file_name = argv[1] ; // Set the file name as specified by the user
if (!veri_file::Analyze(file_name, veri_file::SYSTEM_VERILOG)) return 1 ;

if (!veri_file::ElaborateAllStatic()) return 1 ;

MyVisitor mv ;

VeriModule *mod = veri_file::GetModule("test") ;
if (!mod) return 2 ;
mod->Info("In module '%s'", mod->Name()) ;
mod->Accept(mv) ;
return 0 ;
}
</nowiki>

Run:
<nowiki>
$ test-linux
-- Analyzing Verilog file 'test.sv' (VERI-1482)
test.sv(5): INFO: compiling module 'test' (VERI-1018)
test.sv(8): INFO: In module 'test'
test.sv(7): INFO: Expression: 'int ', evaluated to 'int '
test.sv(7): INFO: Expression: '$bits(I.data)', evaluated to '13'
$
</nowiki>

If for some reason static elaboration is not desirable (it does take memory and CPU time), hierarchy-tree elaboration can be run instead. Hierarchy-tree elaboration takes much less memory anc CPU time than static elaborations does.

Reference: https://www.verific.com/docs/index.php?title=Hierarchy_Tree

The C++ example below uses hierarchy-tree elaboration:

C++:
<nowiki>
#include "veri_file.h"
#include "VeriModule.h"
#include "VeriId.h"
#include "VeriExpression.h"
#include "VeriBaseValue_Stat.h"
#include "hier_tree.h"
#include "HierTreeNode.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main(int argc, const char **argv)
{
const char *file_name = "test.sv" ;
const char *top_name = "test" ;
const char *my_name = "my_int" ;

if (!veri_file::Analyze(file_name, veri_file::SYSTEM_VERILOG)) return 1 ;

VeriModule *top = veri_file::GetModule(top_name) ;
if (!top) return 2 ;

VeriIdDef *my_id = top->FindDeclared(my_name) ;
if (!my_id) return 3 ;

VeriExpression *init_val = my_id->GetInitialValue() ;
if (!init_val) return 4 ;

Array top_mods(1) ;
top_mods.Insert(top) ;

const Map *top_nodes = hier_tree::CreateHierarchicalTree(&top_mods, 0, 0, 0) ;
if (!top_nodes) return 5 ;

HierTreeNode *top_node = (HierTreeNode *)top_nodes->GetValue(top_name) ;
if (!top_node) {
hier_tree::DeleteHierarchicalTree() ;
return 6 ;
}

InterfaceInfo *info = top_node->GetParamValue(my_id) ;
VeriBaseValue *val = 0 ;
VeriBaseValue *delete_val = 0 ;
if (info) {
// We already have the value evaluated, get from node:
val = info->GetVeriEvaluatedValue() ;
} else {
// Need to evaluate the value, use the context from the node:
Map *context = top_node->PushContext() ;
hier_tree::PushNode(top_node) ;

val = init_val->StaticEvaluate(0, 0, 0, 0) ;
delete_val = val ;

hier_tree::PopNode() ;
top_node->PopContext(context) ;
}

char *val_img = (val) ? val->Image() : 0 ;
init_val->Info("%s(%s) evaluated to %s", my_name, my_id->GetPrettyPrintedString(), ((val_img)?val_img:"<NULL>")) ;
Strings::free(val_img) ;

delete delete_val ;

hier_tree::DeleteHierarchicalTree() ;

return 0 ;
}
</nowiki>

Run:
<nowiki>
$ test-linux
-- Analyzing Verilog file 'test.sv' (VERI-1482)
test.sv(7): INFO: my_int(my_int = $bits(I.data)) evaluated to 13
$
</nowiki>

How to evaluate a Verilog expression

2025-09-03T19:18:49Z

Hoa:

How to evaluate a Verilog expression

2025-09-03T19:17:54Z

Hoa:

Evaluating a Verilog expression requires 'Static Elaboration' or 'Hierarchy Tree' feature.

In the example below, a, b, and c are declared in the Verilog module. But 'Static Elaboration' feature is still required because the API VeriExpression::StaticEvaluate() is available only with 'Static Elaboration' feature.

C++:
<nowiki>
#include "veri_file.h"
#include "VeriExpression.h"
#include "VeriModule.h"
#include "VeriBaseValue_Stat.h"

#include "Strings.h"
#include "Array.h"
#include "Map.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main(int argc, const char **argv)
{
const char *file_name = (argc > 1) ? argv[1] : "test.v" ;
const char *module_name = (argc > 2) ? argv[2] : "test_module" ;

Array files(1) ;
files.Insert(file_name) ;
if (!veri_file::AnalyzeMultipleFiles(&files, veri_file::SYSTEM_VERILOG)) return 1 ;

const VeriModule *mod = veri_file::GetModule(module_name) ;
if (!mod) return 2 ;

// Apply following known values to evaluate "a[b] + c":
// a = {1'b1, 1'b1}
// b = 2'b00
// c = 2'b01

const char *expr_string = "a[b] + c" ;
Map known_values(STRING_HASH) ;
(void) known_values.Insert("a", "{1'b1, 1'b1}") ;
(void) known_values.Insert("b", "2'b00") ;
(void) known_values.Insert("c", "2'b01") ;

ValueTable df ;

MapIter mi ;
const char *id_name ;
const char *val_str ;
FOREACH_MAP_ITEM(&known_values, mi, &id_name, &val_str) {
if (!id_name || !val_str) continue ;

// Find the identifier:
VeriIdDef *id = mod->FindDeclared(id_name) ;
if (!id) return 3 ;

// Create the expression:
VeriExpression *expr = veri_file::AnalyzeExpr(val_str, veri_file::SYSTEM_VERILOG) ;
if (!expr) return 4 ;

// Evaluate the expression:
// If this is a literal expression, we do not need the value value or Resolve() call or else we need both:
VeriBaseValue *val = expr->StaticEvaluate(0 /* self context */, 0 /* value table */) ;
delete expr ;
if (!val) return 5 ;

// Insert into the table to be used later:
if (!df.Insert(id, val)) {
delete val ;
return 6 ;
}
}

// Now create the expression for to be evaluated:
VeriExpression *expr = veri_file::AnalyzeExpr(expr_string, veri_file::SYSTEM_VERILOG) ;
if (!expr) return 7 ;

// Resolve the expression so that the id-refs are resolved:
expr->Resolve(mod->GetScope(), VeriTreeNode::VERI_UNDEF_ENV) ;

VeriBaseValue *val = expr->StaticEvaluate(0 /* self context */, &df /* use this table with the known values */) ;
delete expr ;
if (!val) return 8 ; // Failed to evaluate

char *image = val->Image() ;
int result = val->GetIntegerValue() ;
mod->Info("Evaluated value: %s (%d)", ((image)?image:""), result) ;
Strings::free(image) ;
delete val ;

return 0 ;
}
</nowiki>

Verilog testcase:

<nowiki>
module test_module;
wire a [1:0];
wire [1:0] b;
wire [1:0] c;
endmodule
</nowiki>

Run:

<nowiki>
$ test-linux
-- Analyzing Verilog file 'test.v' (VERI-1482)
test.v(5): INFO: Evaluated value: 2'b10 (2)
$
</nowiki>

How to evaluate a Verilog expression

2025-09-03T19:15:31Z

Hoa:

Evaluating a Verilog expression Verific 'Static Elaboration' or 'Hierarchy Tree' feature.

In the example below, a, b, and c are declared in the Verilog module. But 'Static Elaboration' feature is still required because the API VeriExpression::StaticEvaluate() is available only with 'Static Elaboration' feature.

C++:
<nowiki>
#include "veri_file.h"
#include "VeriExpression.h"
#include "VeriModule.h"
#include "VeriBaseValue_Stat.h"

#include "Strings.h"
#include "Array.h"
#include "Map.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main(int argc, const char **argv)
{
const char *file_name = (argc > 1) ? argv[1] : "test.v" ;
const char *module_name = (argc > 2) ? argv[2] : "test_module" ;

Array files(1) ;
files.Insert(file_name) ;
if (!veri_file::AnalyzeMultipleFiles(&files, veri_file::SYSTEM_VERILOG)) return 1 ;

const VeriModule *mod = veri_file::GetModule(module_name) ;
if (!mod) return 2 ;

// Apply following known values to evaluate "a[b] + c":
// a = {1'b1, 1'b1}
// b = 2'b00
// c = 2'b01

const char *expr_string = "a[b] + c" ;
Map known_values(STRING_HASH) ;
(void) known_values.Insert("a", "{1'b1, 1'b1}") ;
(void) known_values.Insert("b", "2'b00") ;
(void) known_values.Insert("c", "2'b01") ;

ValueTable df ;

MapIter mi ;
const char *id_name ;
const char *val_str ;
FOREACH_MAP_ITEM(&known_values, mi, &id_name, &val_str) {
if (!id_name || !val_str) continue ;

// Find the identifier:
VeriIdDef *id = mod->FindDeclared(id_name) ;
if (!id) return 3 ;

// Create the expression:
VeriExpression *expr = veri_file::AnalyzeExpr(val_str, veri_file::SYSTEM_VERILOG) ;
if (!expr) return 4 ;

// Evaluate the expression:
// If this is a literal expression, we do not need the value value or Resolve() call or else we need both:
VeriBaseValue *val = expr->StaticEvaluate(0 /* self context */, 0 /* value table */) ;
delete expr ;
if (!val) return 5 ;

// Insert into the table to be used later:
if (!df.Insert(id, val)) {
delete val ;
return 6 ;
}
}

// Now create the expression for to be evaluated:
VeriExpression *expr = veri_file::AnalyzeExpr(expr_string, veri_file::SYSTEM_VERILOG) ;
if (!expr) return 7 ;

// Resolve the expression so that the id-refs are resolved:
expr->Resolve(mod->GetScope(), VeriTreeNode::VERI_UNDEF_ENV) ;

VeriBaseValue *val = expr->StaticEvaluate(0 /* self context */, &df /* use this table with the known values */) ;
delete expr ;
if (!val) return 8 ; // Failed to evaluate

char *image = val->Image() ;
int result = val->GetIntegerValue() ;
mod->Info("Evaluated value: %s (%d)", ((image)?image:""), result) ;
Strings::free(image) ;
delete val ;

return 0 ;
}
</nowiki>

Verilog testcase:

<nowiki>
module test_module;
wire a [1:0];
wire [1:0] b;
wire [1:0] c;
endmodule
</nowiki>

Run:

<nowiki>
$ test-linux
-- Analyzing Verilog file 'test.v' (VERI-1482)
test.v(5): INFO: Evaluated value: 2'b10 (2)
$
</nowiki>

How to evaluate a Verilog expression

2025-09-03T18:46:12Z

Hoa:

This application example shows how to evaluate a Verilog expression. It requires Verific 'Static Elaboration' feature (the API VeriExpression::StaticEvaluate() available only with Verilog Static Elaboration feature).

Note that a, b, and c are declared in the Verilog module. The application evaluates an expression of these variables.

C++:
<nowiki>
#include "veri_file.h"
#include "VeriExpression.h"
#include "VeriModule.h"
#include "VeriBaseValue_Stat.h"

#include "Strings.h"
#include "Array.h"
#include "Map.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main(int argc, const char **argv)
{
const char *file_name = (argc > 1) ? argv[1] : "test.v" ;
const char *module_name = (argc > 2) ? argv[2] : "test_module" ;

Array files(1) ;
files.Insert(file_name) ;
if (!veri_file::AnalyzeMultipleFiles(&files, veri_file::SYSTEM_VERILOG)) return 1 ;

const VeriModule *mod = veri_file::GetModule(module_name) ;
if (!mod) return 2 ;

// Apply following known values to evaluate "a[b] + c":
// a = {1'b1, 1'b1}
// b = 2'b00
// c = 2'b01

const char *expr_string = "a[b] + c" ;
Map known_values(STRING_HASH) ;
(void) known_values.Insert("a", "{1'b1, 1'b1}") ;
(void) known_values.Insert("b", "2'b00") ;
(void) known_values.Insert("c", "2'b01") ;

ValueTable df ;

MapIter mi ;
const char *id_name ;
const char *val_str ;
FOREACH_MAP_ITEM(&known_values, mi, &id_name, &val_str) {
if (!id_name || !val_str) continue ;

// Find the identifier:
VeriIdDef *id = mod->FindDeclared(id_name) ;
if (!id) return 3 ;

// Create the expression:
VeriExpression *expr = veri_file::AnalyzeExpr(val_str, veri_file::SYSTEM_VERILOG) ;
if (!expr) return 4 ;

// Evaluate the expression:
// If this is a literal expression, we do not need the value value or Resolve() call or else we need both:
VeriBaseValue *val = expr->StaticEvaluate(0 /* self context */, 0 /* value table */) ;
delete expr ;
if (!val) return 5 ;

// Insert into the table to be used later:
if (!df.Insert(id, val)) {
delete val ;
return 6 ;
}
}

// Now create the expression for to be evaluated:
VeriExpression *expr = veri_file::AnalyzeExpr(expr_string, veri_file::SYSTEM_VERILOG) ;
if (!expr) return 7 ;

// Resolve the expression so that the id-refs are resolved:
expr->Resolve(mod->GetScope(), VeriTreeNode::VERI_UNDEF_ENV) ;

VeriBaseValue *val = expr->StaticEvaluate(0 /* self context */, &df /* use this table with the known values */) ;
delete expr ;
if (!val) return 8 ; // Failed to evaluate

char *image = val->Image() ;
int result = val->GetIntegerValue() ;
mod->Info("Evaluated value: %s (%d)", ((image)?image:""), result) ;
Strings::free(image) ;
delete val ;

return 0 ;
}
</nowiki>

Verilog testcase:

<nowiki>
module test_module;
wire a [1:0];
wire [1:0] b;
wire [1:0] c;
endmodule
</nowiki>

Run:

<nowiki>
$ test-linux
-- Analyzing Verilog file 'test.v' (VERI-1482)
test.v(5): INFO: Evaluated value: 2'b10 (2)
$
</nowiki>

How to evaluate a Verilog expression

2025-09-03T18:44:19Z

Hoa:

This application example shows how to evaluate a Verilog expression. It requires Verific 'Static Elaboration' feature.

Note that a, b, and c are declared in the Verilog module. The application evaluates an expression of these variables.

C++:
<nowiki>
#include "veri_file.h"
#include "VeriExpression.h"
#include "VeriModule.h"
#include "VeriBaseValue_Stat.h"

#include "Strings.h"
#include "Array.h"
#include "Map.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main(int argc, const char **argv)
{
const char *file_name = (argc > 1) ? argv[1] : "test.v" ;
const char *module_name = (argc > 2) ? argv[2] : "test_module" ;

Array files(1) ;
files.Insert(file_name) ;
if (!veri_file::AnalyzeMultipleFiles(&files, veri_file::SYSTEM_VERILOG)) return 1 ;

const VeriModule *mod = veri_file::GetModule(module_name) ;
if (!mod) return 2 ;

// Apply following known values to evaluate "a[b] + c":
// a = {1'b1, 1'b1}
// b = 2'b00
// c = 2'b01

const char *expr_string = "a[b] + c" ;
Map known_values(STRING_HASH) ;
(void) known_values.Insert("a", "{1'b1, 1'b1}") ;
(void) known_values.Insert("b", "2'b00") ;
(void) known_values.Insert("c", "2'b01") ;

ValueTable df ;

MapIter mi ;
const char *id_name ;
const char *val_str ;
FOREACH_MAP_ITEM(&known_values, mi, &id_name, &val_str) {
if (!id_name || !val_str) continue ;

// Find the identifier:
VeriIdDef *id = mod->FindDeclared(id_name) ;
if (!id) return 3 ;

// Create the expression:
VeriExpression *expr = veri_file::AnalyzeExpr(val_str, veri_file::SYSTEM_VERILOG) ;
if (!expr) return 4 ;

// Evaluate the expression:
// If this is a literal expression, we do not need the value value or Resolve() call or else we need both:
VeriBaseValue *val = expr->StaticEvaluate(0 /* self context */, 0 /* value table */) ;
delete expr ;
if (!val) return 5 ;

// Insert into the table to be used later:
if (!df.Insert(id, val)) {
delete val ;
return 6 ;
}
}

// Now create the expression for to be evaluated:
VeriExpression *expr = veri_file::AnalyzeExpr(expr_string, veri_file::SYSTEM_VERILOG) ;
if (!expr) return 7 ;

// Resolve the expression so that the id-refs are resolved:
expr->Resolve(mod->GetScope(), VeriTreeNode::VERI_UNDEF_ENV) ;

VeriBaseValue *val = expr->StaticEvaluate(0 /* self context */, &df /* use this table with the known values */) ;
delete expr ;
if (!val) return 8 ; // Failed to evaluate

char *image = val->Image() ;
int result = val->GetIntegerValue() ;
mod->Info("Evaluated value: %s (%d)", ((image)?image:""), result) ;
Strings::free(image) ;
delete val ;

return 0 ;
}
</nowiki>

Verilog testcase:

<nowiki>
module test_module;
wire a [1:0];
wire [1:0] b;
wire [1:0] c;
endmodule
</nowiki>

Run:

<nowiki>
$ test-linux
-- Analyzing Verilog file 'test.v' (VERI-1482)
test.v(5): INFO: Evaluated value: 2'b10 (2)
$
</nowiki>

How to evaluate a VHDL expression

2025-09-02T22:36:07Z

Hoa:

'''>>> This page is under construction <<<'''

Unlike in Verilog, expression evaluation in VHDL is fairly involved and needs all of the following:

* Either static elaborated tree or context from correct HierTreeNode pushed into the parse tree.
* VhdlNode::_present_scope set to the container scope where the expression is defined or to be used.
* Expression evaluation method set to static elaboration with VhdlNode::SetStaticElab().
* Constant pwr/gnd/x/z nets set with VhdlNode::SetConstNets(). Constant nets also need to be deleted to avoid memory leaks, but should only be done after the evaluated value (that is using those nets) is deleted.

The application examples below will illustrate the process.

C++ example 1 (via static elaboration):
<nowiki>
#include "vhdl_file.h"
#include "VhdlUnits.h"
#include "VhdlIdDef.h"
#include "VhdlExpression.h"
#include "VhdlValue_Elab.h"
#include "VhdlDataFlow_Elab.h"

#include "Strings.h"
#include "Map.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

// Restore back to the previous setting:
#define RETURN(N) { \
if (!static_elab) VhdlNode::SetRtlElab() ; \
VhdlNode::_present_scope = save_scope ; \
VhdlNode::ResetConstNets() ; \
return N ; \
}

int main(int argc, const char **argv)
{
const char *file_name = (argc > 1) ? argv[1] : "test.vhd" ;
const char *entity_name = (argc > 2) ? argv[2] : "test_entity" ;
const char *arch_name = (argc > 2) ? argv[2] : "test_arch" ;

const char *expr_string = "a(b) + c" ;
const char *lib_name = "work" ;

if (!vhdl_file::SetDefaultLibraryPath("../vdbs")) return 1 ;
if (!vhdl_file::Analyze(file_name)) return 2 ;

// Step (0): Need to have the parse tree static elaborated already:
if (!vhdl_file::Elaborate(entity_name, lib_name, arch_name, 0 /* generics */, 1 /* static elab */)) return 3 ;

const VhdlLibrary *work = vhdl_file::GetLibrary(lib_name) ;
if (!work) return 4 ;

const VhdlPrimaryUnit *ent = work->GetPrimUnit(entity_name) ;
if (!ent) return 5 ;

const VhdlSecondaryUnit *arch = ent->GetSecondaryUnit(arch_name) ;
if (!arch) return 6 ;

VhdlScope *arch_scope = arch->LocalScope() ;
if (!arch_scope) return 7 ;

// Step (1): Need to set _present_scope:
VhdlScope *save_scope = VhdlNode::_present_scope ;
VhdlNode::_present_scope = arch_scope ;

// Step (2): Need to set constant _pwr, _gnd, _x, _z nets:
VhdlNode::SetConstNets() ;

// Step (3): Need to set evaluation flow to use static elaboration:
unsigned static_elab = VhdlNode::IsStaticElab() ;
if (!static_elab) VhdlNode::SetStaticElab() ;

// Apply following known values to evaluate "a(b) + c":
// a = (2, 3)
// b = 0
// c = 1

Map known_values(STRING_HASH) ;
(void) known_values.Insert("a", "(2, 3)") ;
(void) known_values.Insert("b", "0") ;
(void) known_values.Insert("c", "1") ;

// Create a data-flow and set it to be in the "initial" phase
// and in subprograms, so that static elab uses the values from there:
VhdlDataFlow df(0) ;
df.SetInInitial() ;
df.SetInSubprogramOrProcess() ;

// The known values need to be in the condition-id-value Map to be picked up:
Map *id_value_map = new Map(POINTER_HASH, known_values.Size()) ;
df.SetConditionIdValueMap(id_value_map) ;

MapIter mi ;
const char *id_name ;
const char *val_str ;
FOREACH_MAP_ITEM(&known_values, mi, &id_name, &val_str) {
if (!id_name || !val_str) continue ;

// Find the identifier:
VhdlIdDef *id = arch->FindDeclared(id_name) ;
if (!id) RETURN(8) ;

// Create the expression:
VhdlExpression *expr = vhdl_file::AnalyzeExpr(val_str) ;
if (!expr) RETURN(9) ;

// Resolve the expression so that the id-refs are resolved:
(void) expr->TypeInfer(id->Type() /* expected type */, 0 /* return types */, 0 /* environment */, arch_scope) ;

// Evaluate the expression:
// If this is a literal expression, we do not need the value value or Resolve() call or else we need both:
VhdlConstraint *constraint = id->Constraint() ;
VhdlValue *val = expr->Evaluate(constraint, 0 /* DataFlow */, 0) ;
delete expr ;
if (!val) RETURN(10) ;

// Insert into the table to be used later:
//df.SetAssignValue(id, val) ; // This only works for variables and not for signals
(void) id_value_map->Insert(id, val) ;
}

// Now create the expression for to be evaluated:
VhdlExpression *expr = vhdl_file::AnalyzeExpr(expr_string) ;
if (!expr) RETURN(11) ;

// Resolve the expression (in self-context) so that the id-refs are resolved:
// NOTE: May need to have the context (target) type for resolving context dependent expressions:
VhdlIdDef *target_type = expr->TypeInfer(0 /* expected type */, 0 /* return types */, 0 /* environment */, arch_scope) ;
if (!target_type) RETURN(12) ;

// Evaluate the expression with the proper target type:
VhdlValue *val = expr->Evaluate(target_type->Constraint(), &df /* use this table with the known values */, 0) ;
delete expr ;
if (!val) RETURN(13) ; // Failed to evaluate

// Show the result:
char *image = val->Image() ;
verific_int64 result = val->Integer() ;
arch->Info("Evaluated value: %s (%d)", ((image)?image:""), result) ;
Strings::free(image) ;

// Can create constant expression node so that the value can be deleted and ResetConstNets() can safely be called:
expr = val->CreateConstantVhdlExpression(0, target_type, 0) ;
delete val ;
if (!expr) RETURN(14) ;

// Show the expression node:
image = expr->GetPrettyPrintedString() ;
arch->Info("Converted expression: %s", image) ;
Strings::free(image) ;
delete expr ;

RETURN(0) ;
}
</nowiki>

VHDL testcase:
<nowiki>
library ieee ;
use ieee.std_logic_1164.all ;
entity test_entity is
end ;

architecture test_arch of test_entity is
type int_array is array (1 downto 0) of integer ;
signal a : int_array ;
signal b : integer ;
signal c : integer ;
begin
end ;
</nowiki>

Run:
<nowiki>
$ test-linux
INFO: default VHDL library search path is now "/mnt/awing5_customers/Verific/extra_tests/vdbs" (VHDL-1504)
-- Analyzing VHDL file 'test.vhd' (VHDL-1481)
-- Restoring VHDL unit 'ieee.std_logic_1164' from file '/mnt/awing5_customers/Verific/extra_tests/vdbs/ieee/std_logic_1164.vdb' (VHDL-1493)
-- Restoring VHDL unit 'std.standard' from file '/mnt/awing5_customers/Verific/extra_tests/vdbs/std/standard.vdb' (VHDL-1493)
test.vhd(3): INFO: analyzing entity 'test_entity' (VHDL-1012)
test.vhd(6): INFO: analyzing architecture 'test_arch' (VHDL-1010)
test.vhd(3): INFO: processing 'test_entity(test_arch)' (VHDL-1067)
test.vhd(12): INFO: Evaluated value: 4 (4)
test.vhd(12): INFO: Converted expression: 4
$
</nowiki>

C++ example 2 (via hierarchy tree creation):

<nowiki>
#include "vhdl_file.h"
#include "vhdl_tokens.h"
#include "VhdlExpression.h"
#include "VhdlValue_Elab.h"

#include "hier_tree.h"
#include "HierTreeNode.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main(void)
{
vhdl_file::SetDefaultLibraryPath("../vdbs") ;

const char *file_name = "design.vhdl" ;
if (!vhdl_file::Analyze(file_name)) return 1 ;

VhdlLibrary *work = vhdl_file::GetLibrary("work") ;
if (!work) return 2 ;

Array vhdl_libs ;
vhdl_libs.Insert(work) ;
const Map *top_nodes = hier_tree::CreateHierarchicalTreeAll(0, &vhdl_libs, 0) ;
if (!top_nodes) return 3 ;

HierTreeNode *test = (HierTreeNode *)top_nodes->GetValue("test") ;
if (!test) return 4 ;

HierTreeNode *u1 = test->GetChild("u1") ;
if (!u1) return 5 ;

Map *context = u1->PushContext() ;

//VhdlScope *node_scope = u1->GetNodeScope() ; // Entity scope
VhdlScope *node_scope = u1->GetVhdlArchitectureScope() ; // Architecture scope
if (!node_scope) { u1->PopContext(context) ; return 6 ; }

VhdlScope *save = VhdlNode::_present_scope ;
unsigned stat_elab = VhdlNode::IsStaticElab() ;

VhdlNode::_present_scope = node_scope ;
VhdlNode::SetConstNets() ;
VhdlNode::SetStaticElab() ;

// If you have the expression, use that; or parse one:
VhdlExpression *expr = vhdl_file::AnalyzeExpr("A + B") ;
if (!expr) { u1->PopContext(context) ; return 7 ; }

(void) expr->TypeInfer(0, 0, VHDL_READ, node_scope) ;
VhdlValue *val = expr->Evaluate(0, 0, 0) ;
if (!val) { delete expr ; u1->PopContext(context) ; return 8 ; }

char *img = val->Image() ;
char *pp_str = expr->GetPrettyPrintedString() ;
expr->Info("Expression '%s' evaluated to '%s'", pp_str, img) ;
Strings::free(pp_str) ;
Strings::free(img) ;
delete val ;
delete expr ;

VhdlNode::ResetConstNets() ;
if (!stat_elab) VhdlNode::SetRtlElab() ;
VhdlNode::_present_scope = save ;

u1->PopContext(context) ;

return 0 ;
}
</nowiki>

VHDL testcase:

<nowiki>
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity mult is
generic (
A: integer :=0;
B: integer :=7 );

port (ain : in integer range (A) to (B);
z : out integer range (A) to (B));
end mult;

architecture xxx of mult is
begin
process(ain) begin
z <= ain ;
end process;
end xxx;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity test is
port (ain1 : in integer range (0) to (2);
cout1: out integer range (0) to (2));
end test;

architecture rtl of test is
component mult
generic (
A: integer :=0;
B: integer :=2 );
port (ain : in integer range (A+B) to (B);
z : out integer range (A) to (B) );
end component;

begin
u1: mult
generic map(
A=> 0,
B=> 1
)
port map(ain=>ain1,z=>cout1);
end rtl;
</nowiki>

Run:

<nowiki>
$ test-linux
INFO: default VHDL library search path is now "/mnt/awing5_customers/Verific/extra_tests/vdbs" (VHDL-1504)
-- Analyzing VHDL file 'design.vhdl' (VHDL-1481)
-- Restoring VHDL unit 'ieee.std_logic_1164' from file '/mnt/awing5_customers/Verific/extra_tests/vdbs/ieee/std_logic_1164.vdb' (VHDL-1493)
-- Restoring VHDL unit 'std.standard' from file '/mnt/awing5_customers/Verific/extra_tests/vdbs/std/standard.vdb' (VHDL-1493)
-- Restoring VHDL unit 'ieee.std_logic_arith' from file '/mnt/awing5_customers/Verific/extra_tests/vdbs/ieee/std_logic_arith.vdb' (VHDL-1493)
design.vhdl(5): INFO: analyzing entity 'mult' (VHDL-1012)
design.vhdl(14): INFO: analyzing architecture 'xxx' (VHDL-1010)
design.vhdl(25): INFO: analyzing entity 'test' (VHDL-1012)
design.vhdl(30): INFO: analyzing architecture 'rtl' (VHDL-1010)
INFO: Expression '(a + b)' evaluated to '1'
$
</nowiki>

How to evaluate a VHDL expression

2025-09-02T22:33:39Z

Hoa:

'''>>> This page is under construction <<<'''

Unlike in Verilog, expression evaluation in VHDL is fairly involved and needs all of the following:

* Either static elaborated tree or context from correct HierTreeNode pushed into the parse tree.
* VhdlNode::_present_scope set to the container scope where the expression is defined or to be used.
* Expression evaluation method set to static elaboration with VhdlNode::SetStaticElab().
* Constant pwr/gnd/x/z nets set with VhdlNode::SetConstNets(). Constant nets also need to be deleted to avoid memory leaks, but should only be done after the evaluated value (that is using those nets) is deleted.

The application examples below will illustrate the process.

C++ example 1:
<nowiki>
#include "vhdl_file.h"
#include "VhdlUnits.h"
#include "VhdlIdDef.h"
#include "VhdlExpression.h"
#include "VhdlValue_Elab.h"
#include "VhdlDataFlow_Elab.h"

#include "Strings.h"
#include "Map.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

// Restore back to the previous setting:
#define RETURN(N) { \
if (!static_elab) VhdlNode::SetRtlElab() ; \
VhdlNode::_present_scope = save_scope ; \
VhdlNode::ResetConstNets() ; \
return N ; \
}

int main(int argc, const char **argv)
{
const char *file_name = (argc > 1) ? argv[1] : "test.vhd" ;
const char *entity_name = (argc > 2) ? argv[2] : "test_entity" ;
const char *arch_name = (argc > 2) ? argv[2] : "test_arch" ;

const char *expr_string = "a(b) + c" ;
const char *lib_name = "work" ;

if (!vhdl_file::SetDefaultLibraryPath("../vdbs")) return 1 ;
if (!vhdl_file::Analyze(file_name)) return 2 ;

// Step (0): Need to have the parse tree static elaborated already:
if (!vhdl_file::Elaborate(entity_name, lib_name, arch_name, 0 /* generics */, 1 /* static elab */)) return 3 ;

const VhdlLibrary *work = vhdl_file::GetLibrary(lib_name) ;
if (!work) return 4 ;

const VhdlPrimaryUnit *ent = work->GetPrimUnit(entity_name) ;
if (!ent) return 5 ;

const VhdlSecondaryUnit *arch = ent->GetSecondaryUnit(arch_name) ;
if (!arch) return 6 ;

VhdlScope *arch_scope = arch->LocalScope() ;
if (!arch_scope) return 7 ;

// Step (1): Need to set _present_scope:
VhdlScope *save_scope = VhdlNode::_present_scope ;
VhdlNode::_present_scope = arch_scope ;

// Step (2): Need to set constant _pwr, _gnd, _x, _z nets:
VhdlNode::SetConstNets() ;

// Step (3): Need to set evaluation flow to use static elaboration:
unsigned static_elab = VhdlNode::IsStaticElab() ;
if (!static_elab) VhdlNode::SetStaticElab() ;

// Apply following known values to evaluate "a(b) + c":
// a = (2, 3)
// b = 0
// c = 1

Map known_values(STRING_HASH) ;
(void) known_values.Insert("a", "(2, 3)") ;
(void) known_values.Insert("b", "0") ;
(void) known_values.Insert("c", "1") ;

// Create a data-flow and set it to be in the "initial" phase
// and in subprograms, so that static elab uses the values from there:
VhdlDataFlow df(0) ;
df.SetInInitial() ;
df.SetInSubprogramOrProcess() ;

// The known values need to be in the condition-id-value Map to be picked up:
Map *id_value_map = new Map(POINTER_HASH, known_values.Size()) ;
df.SetConditionIdValueMap(id_value_map) ;

MapIter mi ;
const char *id_name ;
const char *val_str ;
FOREACH_MAP_ITEM(&known_values, mi, &id_name, &val_str) {
if (!id_name || !val_str) continue ;

// Find the identifier:
VhdlIdDef *id = arch->FindDeclared(id_name) ;
if (!id) RETURN(8) ;

// Create the expression:
VhdlExpression *expr = vhdl_file::AnalyzeExpr(val_str) ;
if (!expr) RETURN(9) ;

// Resolve the expression so that the id-refs are resolved:
(void) expr->TypeInfer(id->Type() /* expected type */, 0 /* return types */, 0 /* environment */, arch_scope) ;

// Evaluate the expression:
// If this is a literal expression, we do not need the value value or Resolve() call or else we need both:
VhdlConstraint *constraint = id->Constraint() ;
VhdlValue *val = expr->Evaluate(constraint, 0 /* DataFlow */, 0) ;
delete expr ;
if (!val) RETURN(10) ;

// Insert into the table to be used later:
//df.SetAssignValue(id, val) ; // This only works for variables and not for signals
(void) id_value_map->Insert(id, val) ;
}

// Now create the expression for to be evaluated:
VhdlExpression *expr = vhdl_file::AnalyzeExpr(expr_string) ;
if (!expr) RETURN(11) ;

// Resolve the expression (in self-context) so that the id-refs are resolved:
// NOTE: May need to have the context (target) type for resolving context dependent expressions:
VhdlIdDef *target_type = expr->TypeInfer(0 /* expected type */, 0 /* return types */, 0 /* environment */, arch_scope) ;
if (!target_type) RETURN(12) ;

// Evaluate the expression with the proper target type:
VhdlValue *val = expr->Evaluate(target_type->Constraint(), &df /* use this table with the known values */, 0) ;
delete expr ;
if (!val) RETURN(13) ; // Failed to evaluate

// Show the result:
char *image = val->Image() ;
verific_int64 result = val->Integer() ;
arch->Info("Evaluated value: %s (%d)", ((image)?image:""), result) ;
Strings::free(image) ;

// Can create constant expression node so that the value can be deleted and ResetConstNets() can safely be called:
expr = val->CreateConstantVhdlExpression(0, target_type, 0) ;
delete val ;
if (!expr) RETURN(14) ;

// Show the expression node:
image = expr->GetPrettyPrintedString() ;
arch->Info("Converted expression: %s", image) ;
Strings::free(image) ;
delete expr ;

RETURN(0) ;
}
</nowiki>

VHDL testcase:
<nowiki>
library ieee ;
use ieee.std_logic_1164.all ;
entity test_entity is
end ;

architecture test_arch of test_entity is
type int_array is array (1 downto 0) of integer ;
signal a : int_array ;
signal b : integer ;
signal c : integer ;
begin
end ;
</nowiki>

Run:
<nowiki>
$ test-linux
INFO: default VHDL library search path is now "/mnt/awing5_customers/Verific/extra_tests/vdbs" (VHDL-1504)
-- Analyzing VHDL file 'test.vhd' (VHDL-1481)
-- Restoring VHDL unit 'ieee.std_logic_1164' from file '/mnt/awing5_customers/Verific/extra_tests/vdbs/ieee/std_logic_1164.vdb' (VHDL-1493)
-- Restoring VHDL unit 'std.standard' from file '/mnt/awing5_customers/Verific/extra_tests/vdbs/std/standard.vdb' (VHDL-1493)
test.vhd(3): INFO: analyzing entity 'test_entity' (VHDL-1012)
test.vhd(6): INFO: analyzing architecture 'test_arch' (VHDL-1010)
test.vhd(3): INFO: processing 'test_entity(test_arch)' (VHDL-1067)
test.vhd(12): INFO: Evaluated value: 4 (4)
test.vhd(12): INFO: Converted expression: 4
$
</nowiki>

C++ example 2:

<nowiki>
#include "vhdl_file.h"
#include "vhdl_tokens.h"
#include "VhdlExpression.h"
#include "VhdlValue_Elab.h"

#include "hier_tree.h"
#include "HierTreeNode.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main(void)
{
vhdl_file::SetDefaultLibraryPath("../vdbs") ;

const char *file_name = "design.vhdl" ;
if (!vhdl_file::Analyze(file_name)) return 1 ;

VhdlLibrary *work = vhdl_file::GetLibrary("work") ;
if (!work) return 2 ;

Array vhdl_libs ;
vhdl_libs.Insert(work) ;
const Map *top_nodes = hier_tree::CreateHierarchicalTreeAll(0, &vhdl_libs, 0) ;
if (!top_nodes) return 3 ;

HierTreeNode *test = (HierTreeNode *)top_nodes->GetValue("test") ;
if (!test) return 4 ;

HierTreeNode *u1 = test->GetChild("u1") ;
if (!u1) return 5 ;

Map *context = u1->PushContext() ;

//VhdlScope *node_scope = u1->GetNodeScope() ; // Entity scope
VhdlScope *node_scope = u1->GetVhdlArchitectureScope() ; // Architecture scope
if (!node_scope) { u1->PopContext(context) ; return 6 ; }

VhdlScope *save = VhdlNode::_present_scope ;
unsigned stat_elab = VhdlNode::IsStaticElab() ;

VhdlNode::_present_scope = node_scope ;
VhdlNode::SetConstNets() ;
VhdlNode::SetStaticElab() ;

// If you have the expression, use that; or parse one:
VhdlExpression *expr = vhdl_file::AnalyzeExpr("A + B") ;
if (!expr) { u1->PopContext(context) ; return 7 ; }

(void) expr->TypeInfer(0, 0, VHDL_READ, node_scope) ;
VhdlValue *val = expr->Evaluate(0, 0, 0) ;
if (!val) { delete expr ; u1->PopContext(context) ; return 8 ; }

char *img = val->Image() ;
char *pp_str = expr->GetPrettyPrintedString() ;
expr->Info("Expression '%s' evaluated to '%s'", pp_str, img) ;
Strings::free(pp_str) ;
Strings::free(img) ;
delete val ;
delete expr ;

VhdlNode::ResetConstNets() ;
if (!stat_elab) VhdlNode::SetRtlElab() ;
VhdlNode::_present_scope = save ;

u1->PopContext(context) ;

return 0 ;
}
</nowiki>

VHDL testcase:

<nowiki>
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity mult is
generic (
A: integer :=0;
B: integer :=7 );

port (ain : in integer range (A) to (B);
z : out integer range (A) to (B));
end mult;

architecture xxx of mult is
begin
process(ain) begin
z <= ain ;
end process;
end xxx;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity test is
port (ain1 : in integer range (0) to (2);
cout1: out integer range (0) to (2));
end test;

architecture rtl of test is
component mult
generic (
A: integer :=0;
B: integer :=2 );
port (ain : in integer range (A+B) to (B);
z : out integer range (A) to (B) );
end component;

begin
u1: mult
generic map(
A=> 0,
B=> 1
)
port map(ain=>ain1,z=>cout1);
end rtl;
</nowiki>

Run:

<nowiki>
$ test-linux
INFO: default VHDL library search path is now "/mnt/awing5_customers/Verific/extra_tests/vdbs" (VHDL-1504)
-- Analyzing VHDL file 'design.vhdl' (VHDL-1481)
-- Restoring VHDL unit 'ieee.std_logic_1164' from file '/mnt/awing5_customers/Verific/extra_tests/vdbs/ieee/std_logic_1164.vdb' (VHDL-1493)
-- Restoring VHDL unit 'std.standard' from file '/mnt/awing5_customers/Verific/extra_tests/vdbs/std/standard.vdb' (VHDL-1493)
-- Restoring VHDL unit 'ieee.std_logic_arith' from file '/mnt/awing5_customers/Verific/extra_tests/vdbs/ieee/std_logic_arith.vdb' (VHDL-1493)
design.vhdl(5): INFO: analyzing entity 'mult' (VHDL-1012)
design.vhdl(14): INFO: analyzing architecture 'xxx' (VHDL-1010)
design.vhdl(25): INFO: analyzing entity 'test' (VHDL-1012)
design.vhdl(30): INFO: analyzing architecture 'rtl' (VHDL-1010)
INFO: Expression '(a + b)' evaluated to '1'
$
</nowiki>

How to evaluate a VHDL expression

2025-09-02T22:32:45Z

Hoa:

'''>>> This page is under construction <<<'''

Unlike in Verilog, expression evaluation in VHDL is fairly involved and needs all of the following:

* Either static elaborated tree or context from correct HierTreeNode pushed into the parse tree.
* VhdlNode::_present_scope set to the container scope where the expression is defined or to be used.
* Expression evaluation method set to static elaboration with VhdlNode::SetStaticElab().
* Constant pwr/gnd/x/z nets set with VhdlNode::SetConstNets(). Constant nets also need to be deleted to avoid memory leaks, but should only be done after the evaluated value (that is using those nets) is deleted.

The application examples below will illustrate the process.

C++ example 1:
<nowiki>
#include "vhdl_file.h"
#include "VhdlUnits.h"
#include "VhdlIdDef.h"
#include "VhdlExpression.h"
#include "VhdlValue_Elab.h"
#include "VhdlDataFlow_Elab.h"

#include "Strings.h"
#include "Map.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

// Restore back to the previous setting:
#define RETURN(N) { \
if (!static_elab) VhdlNode::SetRtlElab() ; \
VhdlNode::_present_scope = save_scope ; \
VhdlNode::ResetConstNets() ; \
return N ; \
}

int main(int argc, const char **argv)
{
const char *file_name = (argc > 1) ? argv[1] : "test.vhd" ;
const char *entity_name = (argc > 2) ? argv[2] : "test_entity" ;
const char *arch_name = (argc > 2) ? argv[2] : "test_arch" ;

const char *expr_string = "a(b) + c" ;
const char *lib_name = "work" ;

if (!vhdl_file::SetDefaultLibraryPath("../vdbs")) return 1 ;
if (!vhdl_file::Analyze(file_name)) return 2 ;

// Step (0): Need to have the parse tree static elaborated already:
if (!vhdl_file::Elaborate(entity_name, lib_name, arch_name, 0 /* generics */, 1 /* static elab */)) return 3 ;

const VhdlLibrary *work = vhdl_file::GetLibrary(lib_name) ;
if (!work) return 4 ;

const VhdlPrimaryUnit *ent = work->GetPrimUnit(entity_name) ;
if (!ent) return 5 ;

const VhdlSecondaryUnit *arch = ent->GetSecondaryUnit(arch_name) ;
if (!arch) return 6 ;

VhdlScope *arch_scope = arch->LocalScope() ;
if (!arch_scope) return 7 ;

// Step (1): Need to set _present_scope:
VhdlScope *save_scope = VhdlNode::_present_scope ;
VhdlNode::_present_scope = arch_scope ;

// Step (2): Need to set constant _pwr, _gnd, _x, _z nets:
VhdlNode::SetConstNets() ;

// Step (3): Need to set evaluation flow to use static elaboration:
unsigned static_elab = VhdlNode::IsStaticElab() ;
if (!static_elab) VhdlNode::SetStaticElab() ;

// Apply following known values to evaluate "a(b) + c":
// a = (2, 3)
// b = 0
// c = 1

Map known_values(STRING_HASH) ;
(void) known_values.Insert("a", "(2, 3)") ;
(void) known_values.Insert("b", "0") ;
(void) known_values.Insert("c", "1") ;

// Create a data-flow and set it to be in the "initial" phase
// and in subprograms, so that static elab uses the values from there:
VhdlDataFlow df(0) ;
df.SetInInitial() ;
df.SetInSubprogramOrProcess() ;

// The known values need to be in the condition-id-value Map to be picked up:
Map *id_value_map = new Map(POINTER_HASH, known_values.Size()) ;
df.SetConditionIdValueMap(id_value_map) ;

MapIter mi ;
const char *id_name ;
const char *val_str ;
FOREACH_MAP_ITEM(&known_values, mi, &id_name, &val_str) {
if (!id_name || !val_str) continue ;

// Find the identifier:
VhdlIdDef *id = arch->FindDeclared(id_name) ;
if (!id) RETURN(8) ;

// Create the expression:
VhdlExpression *expr = vhdl_file::AnalyzeExpr(val_str) ;
if (!expr) RETURN(9) ;

// Resolve the expression so that the id-refs are resolved:
(void) expr->TypeInfer(id->Type() /* expected type */, 0 /* return types */, 0 /* environment */, arch_scope) ;

// Evaluate the expression:
// If this is a literal expression, we do not need the value value or Resolve() call or else we need both:
VhdlConstraint *constraint = id->Constraint() ;
VhdlValue *val = expr->Evaluate(constraint, 0 /* DataFlow */, 0) ;
delete expr ;
if (!val) RETURN(10) ;

// Insert into the table to be used later:
//df.SetAssignValue(id, val) ; // This only works for variables and not for signals
(void) id_value_map->Insert(id, val) ;
}

// Now create the expression for to be evaluated:
VhdlExpression *expr = vhdl_file::AnalyzeExpr(expr_string) ;
if (!expr) RETURN(11) ;

// Resolve the expression (in self-context) so that the id-refs are resolved:
// NOTE: May need to have the context (target) type for resolving context dependent expressions:
VhdlIdDef *target_type = expr->TypeInfer(0 /* expected type */, 0 /* return types */, 0 /* environment */, arch_scope) ;
if (!target_type) RETURN(12) ;

// Evaluate the expression with the proper target type:
VhdlValue *val = expr->Evaluate(target_type->Constraint(), &df /* use this table with the known values */, 0) ;
delete expr ;
if (!val) RETURN(13) ; // Failed to evaluate

// Show the result:
char *image = val->Image() ;
verific_int64 result = val->Integer() ;
arch->Info("Evaluated value: %s (%d)", ((image)?image:""), result) ;
Strings::free(image) ;

// Can create constant expression node so that the value can be deleted and ResetConstNets() can safely be called:
expr = val->CreateConstantVhdlExpression(0, target_type, 0) ;
delete val ;
if (!expr) RETURN(14) ;

// Show the expression node:
image = expr->GetPrettyPrintedString() ;
arch->Info("Converted expression: %s", image) ;
Strings::free(image) ;
delete expr ;

RETURN(0) ;
}
</nowiki>

VHDL testcase:
<nowiki>
library ieee ;
use ieee.std_logic_1164.all ;
entity test_entity is
end ;

architecture test_arch of test_entity is
type int_array is array (1 downto 0) of integer ;
signal a : int_array ;
signal b : integer ;
signal c : integer ;
begin
end ;
</nowiki>

Run:
<nowiki>
$ test-linux
INFO: default VHDL library search path is now "/mnt/awing5_customers/Verific/extra_tests/vdbs" (VHDL-1504)
-- Analyzing VHDL file 'test.vhd' (VHDL-1481)
-- Restoring VHDL unit 'ieee.std_logic_1164' from file '/mnt/awing5_customers/Verific/extra_tests/vdbs/ieee/std_logic_1164.vdb' (VHDL-1493)
-- Restoring VHDL unit 'std.standard' from file '/mnt/awing5_customers/Verific/extra_tests/vdbs/std/standard.vdb' (VHDL-1493)
test.vhd(3): INFO: analyzing entity 'test_entity' (VHDL-1012)
test.vhd(6): INFO: analyzing architecture 'test_arch' (VHDL-1010)
test.vhd(3): INFO: processing 'test_entity(test_arch)' (VHDL-1067)
test.vhd(12): INFO: Evaluated value: 4 (4)
test.vhd(12): INFO: Converted expression: 4
$
</nowiki>

C++ example 2:

<nowiki>
#include "vhdl_file.h"
#include "vhdl_tokens.h"
#include "VhdlExpression.h"
#include "VhdlValue_Elab.h"

#include "hier_tree.h"
#include "HierTreeNode.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main(void)
{
vhdl_file::SetDefaultLibraryPath("../vdbs") ;

const char *file_name = "design.vhdl" ;
if (!vhdl_file::Analyze(file_name)) return 1 ;

VhdlLibrary *work = vhdl_file::GetLibrary("work") ;
if (!work) return 2 ;

Array vhdl_libs ;
vhdl_libs.Insert(work) ;
const Map *top_nodes = hier_tree::CreateHierarchicalTreeAll(0, &vhdl_libs, 0) ;
if (!top_nodes) return 3 ;

HierTreeNode *test = (HierTreeNode *)top_nodes->GetValue("test") ;
if (!test) return 4 ;

HierTreeNode *u1 = test->GetChild("u1") ;
if (!u1) return 5 ;

Map *context = u1->PushContext() ;

//VhdlScope *node_scope = u1->GetNodeScope() ; // Entity scope
VhdlScope *node_scope = u1->GetVhdlArchitectureScope() ; // Architecture scope
if (!node_scope) { u1->PopContext(context) ; return 6 ; }

VhdlScope *save = VhdlNode::_present_scope ;
unsigned stat_elab = VhdlNode::IsStaticElab() ;

VhdlNode::_present_scope = node_scope ;
VhdlNode::SetConstNets() ;
VhdlNode::SetStaticElab() ;

// If you have the expression, use that; or parse one:
VhdlExpression *expr = vhdl_file::AnalyzeExpr("A + B") ;
if (!expr) { u1->PopContext(context) ; return 7 ; }

(void) expr->TypeInfer(0, 0, VHDL_READ, node_scope) ;
VhdlValue *val = expr->Evaluate(0, 0, 0) ;
if (!val) { delete expr ; u1->PopContext(context) ; return 8 ; }

char *img = val->Image() ;
char *pp_str = expr->GetPrettyPrintedString() ;
expr->Info("Expression '%s' evaluated to '%s'", pp_str, img) ;
Strings::free(pp_str) ;
Strings::free(img) ;
delete val ;
delete expr ;

VhdlNode::ResetConstNets() ;
if (!stat_elab) VhdlNode::SetRtlElab() ;
VhdlNode::_present_scope = save ;

u1->PopContext(context) ;

return 0 ;
}

</nowiki>

VHDL testcase:

<nowiki>
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity mult is
generic (
A: integer :=0;
B: integer :=7 );

port (ain : in integer range (A) to (B);
z : out integer range (A) to (B));
end mult;

architecture xxx of mult is
begin
process(ain) begin
z <= ain ;
end process;
end xxx;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity test is
port (ain1 : in integer range (0) to (2);
cout1: out integer range (0) to (2));
end test;

architecture rtl of test is
component mult
generic (
A: integer :=0;
B: integer :=2 );
port (ain : in integer range (A+B) to (B);
z : out integer range (A) to (B) );
end component;

begin
u1: mult
generic map(
A=> 0,
B=> 1
)
port map(ain=>ain1,z=>cout1);
end rtl;
</nowiki>

Run:

<nowiki>
$ test-linux
INFO: default VHDL library search path is now "/mnt/awing5_customers/Verific/extra_tests/vdbs" (VHDL-1504)
-- Analyzing VHDL file 'design.vhdl' (VHDL-1481)
-- Restoring VHDL unit 'ieee.std_logic_1164' from file '/mnt/awing5_customers/Verific/extra_tests/vdbs/ieee/std_logic_1164.vdb' (VHDL-1493)
-- Restoring VHDL unit 'std.standard' from file '/mnt/awing5_customers/Verific/extra_tests/vdbs/std/standard.vdb' (VHDL-1493)
-- Restoring VHDL unit 'ieee.std_logic_arith' from file '/mnt/awing5_customers/Verific/extra_tests/vdbs/ieee/std_logic_arith.vdb' (VHDL-1493)
design.vhdl(5): INFO: analyzing entity 'mult' (VHDL-1012)
design.vhdl(14): INFO: analyzing architecture 'xxx' (VHDL-1010)
design.vhdl(25): INFO: analyzing entity 'test' (VHDL-1012)
design.vhdl(30): INFO: analyzing architecture 'rtl' (VHDL-1010)
INFO: Expression '(a + b)' evaluated to '1'
$
</nowiki>

How to evaluate a VHDL expression

2025-09-02T22:13:12Z

Hoa: Created page with "'''>>> This page is under construction <<<''' Unlike in Verilog, expression evaluation in VHDL is fairly involved and needs all of the following: * Either static elaborated..."

Main Page

2025-09-02T22:00:10Z

Hoa:

'''General'''
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
* [[Source code customization & Stable release services | Source code customization & Stable release services]]
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]
* [[Release version | How do I tell the version of a Verific software release? ]]
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
* [[LineFile data from input files | LineFile data from input files]]
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]
* [[Preserving user nets - preventing nets from being optimized away | Preserving user nets - preventing nets from being optimized away]]
* [[Python pretty-printer for gdb | Python pretty-printer for gdb]]
* [[Yosys-Verific Integration | Yosys-Verific integration]]
* [[How to enable long paths on Windows? | How to enable long paths on Windows?]]

'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Port Expressions]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[Modules with '_1' '_2' suffix in their names | Verilog: After static elaboration, there are modules with "_1", "_2", ..., suffix in their names. Why?]]
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
* [[Notes on analysis | SystemVerilog: Notes on analysis]]
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units/interfaces with "_default" or "or "_1, _2" suffix in their names. What are they?]]
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
'''Netlist Database'''
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]
* [[System attributes | Netlist Database: System attributes]]

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''Scripting languages: TCL, Perl, Python'''
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]

'''Code examples'''
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]
* [[How to use MessageCallBackHandler Class | Util/C++: How to use MessageCallBackHandler Class]]
* [[How to use RegisterPragmaRefCallBack() | Util/C++: How to use RegisterPragmaRefCallBack()]]
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
* [[Extract clock enable | Database/C++: Extract clock enable]]
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
* [[Post processing port resolution of black boxes | Database/C++: Post processing port resolution of black boxes]]
* [[Finding hierarchical paths of a Netlist | Database/C++: Finding hierarchical paths of a Netlist]]
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]
* [[Type Range example | Database/Verilog/C++: Type Range example (simple)]]
* [[Type Range example with multi-dimensional arrays| Database/Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
* [[Using TypeRange table to retrieve the originating type-range for an id | Database/Verilog/C++: Using TypeRange table to retrieve the originating type-range for an id]]
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
* [[How to ignore certain modules while analyzing input RTL files | Verilog/C++: How to ignore certain modules while analyzing input RTL files]]
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
* [[In Verilog parsetree adding names to unnamed instances | Verilog/C++: In Verilog parsetree adding names to unnamed instances]]
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
* [[Getting design hierarchy from input RTL files | Verilog/C++/Python: Getting design hierarchy from input RTL files]]
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]
* [[Parse select modules only and ignore the rest | Verilog/C++: Parse select modules only and ignore the rest]]
* [[Create DOT diagram of parse tree | Verilog/C++: Create DOT diagram of a parse tree]]
* [[How to evaluate a Verilog expression | Verilog/C++: How to evaluate a Verilog expression]]
* [[How to get parameters creation-time initial expression/value after Static Elaboration | Verilog/C++: How to get parameters creation-time initial expression/value after Static Elaboration]]
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
* [[Evaluate 'for-generate' loop | Verilog/C++: Evaluate 'for-generate' loop]]
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
* [[How to replace a statement that has a label | SystemVerilog/C++: How to replace a statement that has a label]]
* [[How to insert/add a statement, or a module item, into a sequential block and a generate block | SystemVerilog/C++: How to insert/add a statement, or a module item, into a sequential block and a generate block]]
* [[Simple examples of VHDL visitor pattern | VHDL/C++: Simple examples of VHDL visitor pattern]]
* [[Traverse instances in parsetree | VHDL/C++: Traverse instances in parsetree]]
* [[How to evaluate a VHDL expression | VHDL/C++: How to evaluate a VHDL expression]]
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]

'''INVIO Code examples'''
* [[Simple port modification | SystemVerilog/Python: Simple port modification]]

Getting design hierarchy from input RTL files

2025-08-12T16:53:41Z

Hoa:

C++ application:
<nowiki>
#include <sstream>
#include <iostream>
#include <fstream>
#include <string>
#include "Array.h" // Make class Array available
#include "Set.h" // Make class Set available
#include "Message.h" // Make message handlers available
#include "Strings.h" // Definition of class to manipulate copy, concatenate, create etc...
#include "LineFile.h"
#include "veri_file.h" // Make verilog reader available
#include "VeriModule.h" // Definition of a VeriModule and VeriPrimitive
#include "VeriExpression.h" // Definition of VeriName
#include "VeriId.h" // Definitions of all verilog identifier nodes
#include "VeriScope.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

std::string PrintLocation(const linefile_type lf)
{
std::ostringstream result("") ;
if (lf) {
#ifdef VERIFIC_LINEFILE_INCLUDES_COLUMNS
result << lf->GetFileName() ;
result << "[" ;
result << lf->GetLeftLine() ;
result << ":" ;
result << lf->GetLeftCol() ;
result << "]-[" ;
result << lf->GetRightLine() ;
result << ":" ;
result << lf->GetRightCol() ;
result << "]" ;
#else
result << LineFile::GetFileName(lf) ;
result << "[" ;
result << LineFile::GetLineNo(lf) ;
result << "]" ;
#endif
}
return result.str() ;
}

void PrintHierarchy(VeriModule *module, unsigned depth)
{
if (!module) return ; // Ignore NULL netlists

char *prefix = 0 ;
if (depth) {
prefix = Strings::allocate(depth*4 +3) ;
unsigned i ;
for (i = 0; i < (depth *4); i++) prefix[i] = ' ' ;
prefix[i] = 0 ;
}

// Get the scope of the module:
VeriScope *scope = module->GetScope() ;
// Find all the declared ids in this scope:
Map *ids = scope ? scope->DeclArea() : 0 ;
MapIter mi ;
VeriIdDef *id ;
FOREACH_MAP_ITEM(ids, mi, 0, &id) { // Traverse declared ids
if (!id || !id->IsInst()) continue ; // Consider only the instance ids
VeriModuleInstantiation *mod_inst = id->GetModuleInstance() ; // Take the module instance
VeriModule *mod = mod_inst ? mod_inst->GetInstantiatedModule() : 0 ; // The module instance is a module
if (mod) { // This is module instantiation
linefile_type lf = mod->Linefile() ;
const char *location = PrintLocation(lf).c_str() ;
char *inst_mod = Strings::save(prefix ? prefix : "", id->Name(), " (", mod->Name());
Message::PrintLine(inst_mod, " {", location, "})") ;
PrintHierarchy(mod, depth+1) ;
}
}
}

int main()
{
const char *file_name = "top.v" ;
const char *top_name = "top" ;
const char *work_lib = "work" ;

veri_file::AddVFile("mbot.v") ;
veri_file::AddYDir(".") ;
veri_file::AddIncludeDir(".") ;
veri_file::AddLibExt(".v") ;
if (!veri_file::Analyze(file_name, veri_file::VERILOG_2K /*Verilog 2000*/, work_lib)) return 1 ;

if (veri_file::GetModule(top_name)) {
if (!veri_file::ElaborateStatic(top_name)) return 2 ; // Component-module binding happens in static elaboration
VeriModule *top_module = veri_file::GetModule(top_name) ; // Get the pointer to the top-level module
if (!top_module) {
return 3 ; // Exit from application if there is no top module by the given name in the given Verilog designs
}
linefile_type lf = top_module->Linefile() ;
const char *location = PrintLocation(lf).c_str() ;
Message::PrintLine("Top module: ", top_module->Name(), " {", location, "}") ;
PrintHierarchy(top_module, 1) ;
}
return 0 ; // all good
}

</nowiki>

Python script:
<nowiki>
#! /usr/bin/python
import sys
sys.path.append('../../pythonmain/install')
import Verific

def PrintLocation(lf):
result = '';
if lf:
# if 'VERIFIC_LINEFILE_INCLUDES_COLUMNS' is enabled
result = result + lf.GetFileName() + '[' + Verific.Strings.itoa(lf.GetLeftLine()) + ':' \
+ Verific.Strings.itoa(lf.GetLeftCol()) + ']-[' \
+ Verific.Strings.itoa(lf.GetRightLine()) + ':' \
+ Verific.Strings.itoa(lf.GetRightCol()) + ']'
# if 'VERIFIC_LINEFILE_INCLUDES_COLUMNS' is disabled
# result = result + Verific.LineFile.GetFileName(lf) + '[' + Verific.Strings.itoa(Verific.LineFile.GetLineNo(lf)) + ']'
return result

def PrintHierarchy(module, depth):
if not module:
return
prefix = ''
for i in range (depth):
prefix = prefix + ' '
scope = module.GetScope()
ids = scope.DeclArea() # Map of VeriIdDefs
id_iter = Verific.VeriIdDefMapIter(ids)
id = id_iter.First()
while (id):
if (not id.IsInst()):
id = id_iter.Next()
continue
mod_inst = id.GetModuleInstance() # Take the module instance - VeriModuleInstantiation
mod = mod_inst.GetInstantiatedModule() # The module instance is a module - VeriModule
if (not mod):
id = id_iter.Next()
continue
location = PrintLocation(mod.Linefile());
print ('%sInstance %s (%s {%s})' % (prefix, id.Name(), mod.Name(), location))
id = id_iter.Next()
PrintHierarchy(mod, depth+1);

# main
reader = Verific.veri_file()
file_name = 'top.v'
top_name = 'top'
work_lib = 'work'

reader.AddVFile("mbot.v") ;
reader.AddYDir(".") ;
reader.AddIncludeDir(".") ;
reader.AddLibExt(".v") ;

if (not reader.Analyze(file_name, reader.VERILOG_2K, work_lib)):
print ('Error in Analyze')
sys.exit(1)

top_module = reader.GetModule(top_name) ;
if (not top_module):
print ('Error in GetModule')
sys.exit(2)

# Component-module binding happens in static elaboration
if (not reader.ElaborateStatic(top_name)):
print ('Error in ElaborateStatic')
sys.exit(3)

location = PrintLocation(top_module.Linefile());
print ('\nTop module: %s {%s}' % (top_module.Name(), location))
PrintHierarchy(top_module, 1)

print ('\nDone')

sys.exit(0)

</nowiki>

Input RTL:
<nowiki>
$ cat top.v
// top module
module top(a, b, c, d, e, f, out, m, n, o) ;
input a, b, c, d, e, f, m, n ;
output out, o ;

wire tmp1, tmp2 ;

mid1 i1(a, b, c, d, tmp1) ;
mid1 i2(a, d, e, f, tmp2) ;
mid1 i3(tmp1, tmp2, e, f, out) ;
bot bi(o, m, n);

endmodule
$ cat mid1.v
module mid1 (mid1_inp1, mid1_inp2, mid1_inp3, mid1_inp4, mid1_out,
mid1b_inp1, mid1b_inp2, mid1b_out) ;
input mid1_inp1, mid1_inp2, mid1_inp3, mid1_inp4 ;
output mid1_out ;
input mid1b_inp1, mid1b_inp2 ;
output mid1b_out ;

wire tmp1, tmp2 ;

mid2 m1(mid1_inp1, mid1_inp2, tmp1) ;
mid2 m2(mid1_inp3, mid1_inp4, tmp2) ;
mid2 m3(tmp1, tmp2, mid1_out) ;
bot b(mid1b_inp1, mid1b_inp2, mid1b_out) ;

endmodule
$ cat mid2.v
module mid2 (mid2_inp1, mid2_inp2, mid2_out) ;
input mid2_inp1, mid2_inp2 ;
output mid2_out ;

bot b(mid2_inp1, mid2_inp2, mid2_out) ;

endmodule
$ cat mbot.v

module bot (bot_inp1, bot_inp2, bot_out) ;
input bot_inp1, bot_inp2 ;
output bot_out ;

assign bot_out = bot_inp1 & bot_inp2 ;

endmodule
$
</nowiki>

Run:
<nowiki>
$ test-linux
-- Analyzing Verilog file 'top.v' (VERI-1482)
-- Parsing library file mbot.v (VERI-1482)
-- Analyzing Verilog file 'mbot.v' (VERI-1482)
-- Resolving module 'bot' (VERI-1489)
-- Analyzing Verilog file './mid1.v' (VERI-1482)
-- Resolving module 'mid1' (VERI-1489)
-- Analyzing Verilog file './mid2.v' (VERI-1482)
-- Resolving module 'mid2' (VERI-1489)
top.v(2): INFO: compiling module 'top' (VERI-1018)
top.v(8): WARNING: port 'mid1b_inp1' is not connected on this instance (VERI-2435)
top.v(8): WARNING: port 'mid1b_out' remains unconnected for this instance (VERI-1927)
top.v(9): WARNING: port 'mid1b_inp1' is not connected on this instance (VERI-2435)
top.v(9): WARNING: port 'mid1b_out' remains unconnected for this instance (VERI-1927)
top.v(10): WARNING: port 'mid1b_inp1' is not connected on this instance (VERI-2435)
top.v(10): WARNING: port 'mid1b_out' remains unconnected for this instance (VERI-1927)
top.v(11): WARNING: assignment to input 'n' (VERI-1214)
-- Top module: top {top.v[2:1]-[13:10]}
-- i1 (mid1 {./mid1.v[1:1]-[15:10]})
-- m1 (mid2 {./mid2.v[1:1]-[7:10]})
-- b (bot {mbot.v[2:1]-[8:10]})
-- m2 (mid2 {./mid2.v[1:1]-[7:10]})
-- b (bot {mbot.v[2:1]-[8:10]})
-- m3 (mid2 {./mid2.v[1:1]-[7:10]})
-- b (bot {mbot.v[2:1]-[8:10]})
-- b (bot {mbot.v[2:1]-[8:10]})
-- i2 (mid1 {./mid1.v[1:1]-[15:10]})
-- m1 (mid2 {./mid2.v[1:1]-[7:10]})
-- b (bot {mbot.v[2:1]-[8:10]})
-- m2 (mid2 {./mid2.v[1:1]-[7:10]})
-- b (bot {mbot.v[2:1]-[8:10]})
-- m3 (mid2 {./mid2.v[1:1]-[7:10]})
-- b (bot {mbot.v[2:1]-[8:10]})
-- b (bot {mbot.v[2:1]-[8:10]})
-- i3 (mid1 {./mid1.v[1:1]-[15:10]})
-- m1 (mid2 {./mid2.v[1:1]-[7:10]})
-- b (bot {mbot.v[2:1]-[8:10]})
-- m2 (mid2 {./mid2.v[1:1]-[7:10]})
-- b (bot {mbot.v[2:1]-[8:10]})
-- m3 (mid2 {./mid2.v[1:1]-[7:10]})
-- b (bot {mbot.v[2:1]-[8:10]})
-- b (bot {mbot.v[2:1]-[8:10]})
-- bi (bot {mbot.v[2:1]-[8:10]})
$
</nowiki>

Source code customization & Stable release services

2025-07-22T22:11:20Z

Hoa:

On Verific's system, each of our licensees has a separate code branch. There are mechanisms in place to prevent cross-contamination among code branches, helping to ensure their privacy and security. With this implementation Verific is able to offer two complimentary services to our licensees : ''Source Code Customization'' and ''Stable Release Maintenance''.

'''1. Source Code Customization
'''

A licensee can send in custom code modifications to be merged into their branch maintained by Verific. The customizations will be included in future source code releases so that the licensee will not need to merge them manually each time. Please note the following :

* The modified code should be complete and compilable on Verific's system.

* Zip the modified code with the same password used for the monthly code releases.

* Mention the Verific release version that the modifications are based upon.

The licensee can include testcases that exercise the customized code. These testcases will be added to the regression testsuite of the licensee's code branch.

The best way to initiate this process is for the licensee to file a VIPER issue with Type "Merge Request" and attach the zip file of the code modifications to the VIPER issue. This VIPER issue will be closed (not just "fixed") when the code merge has been completed. The licensee will receive an email notice when the VIPER issue is closed.

'''Important notes:''' Verific will maintain the code changes, but the ownership still lies with the licensee and issues arising from it, if any, need to be corrected by the licensee.

'''2. Stable Release Maintenance
'''

A stable release is a physically separate branch of a licensee's code on Verific's system. It is treated as a distinct "customer" branch. There are no connections between a Stable branch and the licensee's normal branch. A stable branch is usually requested by a licensee when a specific monthly normal branch has been extensively tested and integrated into the licensee's tool and there is a need to maintain this branch of code for a longer period of time than the regular monthly Verific releases. Some notes to keep in mind about the stable branch :

* After creation, stable branch code can only be changed to fix stable branch VIPER issues. VIPER issues filed for a stable branch are treated as "customer-specific". In other words, VIPER fixes in a stable branch don't go into the normal branch and, likewise, VIPER fixes in the normal branch don't go into a stable branch.

* To avoid having new issues introduced into a stable branch, only defect (not enhancement) VIPERs are allowed for a stable branch.

* If an issue needs to be fixed in both a stable branch and in the normal branch, two separate VIPER issues will need to be filed: one for the stable branch and one for the normal branch.

* Stable branch code can not be merged into normal branch code.

* When a stable branch has served its purpose and is ready to be retired, the licensee should inform Verific about this decision as soon as possible. We will then archive the branch and stop its maintenance, helping to free up our time and resources.

Source code customization & Stable release services

2025-07-22T22:09:24Z

Hoa:

On Verific's system, each of our licensees has a separate code branch. There are mechanisms in place to prevent cross-contamination among code branches, helping to ensure their privacy and security. With this implementation Verific is able to offer two complimentary services to our licensees : ''Source Code Customization'' and ''Stable Release Maintenance''.

'''1. Source Code Customization
'''

A licensee can send in custom code modifications to be merged into their branch maintained by Verific. The customizations will be included in future source code releases so that the licensee will not need to merge them manually each time. Please note the following :

* The modified code should be complete and compilable on Verific's system.

* Zip the modified code with the same password used for the monthly code releases.

* Mention the Verific release version that the modifications are based upon.

The licensee can include testcases that exercise the customized code. These testcases will be added to the regression testsuite of the licensee's code branch.

The best way to initiate this process is for the licensee to file a VIPER issue with Type "Merge Request" and attach the zip file of the code modifications to the VIPER issue. This VIPER issue will be closed (not just "fixed") when the code merge has been completed. The licensee will receive an email notice when the VIPER issue is closed.

'''Important notes:''' Verific will maintain the code changes, but the ownership still lies with the licensee and issues arising from it, if any, need to be corrected by the licensee.

'''2. Stable Release Maintenance
'''

A Stable release is a physically separate branch of a licensee's code on Verific's system. It is treated as a distinct "customer" branch. There are no connections between a Stable branch and the licensee's normal branch. A Stable branch is usually requested by a licensee when a specific monthly normal branch has been extensively tested and integrated into the licensee's tool and there is a need to maintain this branch of code for a longer period of time than the regular monthly Verific releases. Some notes to keep in mind about the Stable branch :

* After creation, Stable branch code can only be changed to fix Stable branch VIPER issues. VIPER issues filed for a Stable branch are treated as "customer-specific". In other words, VIPER fixes in a Stable branch don't go into the normal branch and, likewise, VIPER fixes in the normal branch don't go into a Stable branch.

* To avoid having new issues introduced into a Stable branch, only defect (not enhancement) VIPERs are allowed for a Stable branch.

* If an issue needs to be fixed in both a Stable branch and in the normal branch, two separate VIPER issues will need to be filed : one for the Stable branch and one for the normal branch.

* Stable branch code can not be merged into normal branch code.

* When a Stable branch has served its purpose and is ready to be retired, the licensee should inform Verific about this decision as soon as possible. We will then archive the branch and stop its maintenance, helping to free up our time and resources.

Getting design hierarchy from input RTL files

2025-07-14T19:12:36Z

Hoa: Created page with "C++ application: <nowiki> #include <sstream> #include <iostream> #include <fstream> #include <string> #include "Array.h" // Make class Array available #include "Set...."

C++ application:
<nowiki>
#include <sstream>
#include <iostream>
#include <fstream>
#include <string>
#include "Array.h" // Make class Array available
#include "Set.h" // Make class Set available
#include "Message.h" // Make message handlers available
#include "Strings.h" // Definition of class to manipulate copy, concatenate, create etc...
#include "LineFile.h"
#include "veri_file.h" // Make verilog reader available
#include "VeriModule.h" // Definition of a VeriModule and VeriPrimitive
#include "VeriExpression.h" // Definition of VeriName
#include "VeriId.h" // Definitions of all verilog identifier nodes
#include "VeriScope.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

std::string PrintLocation(const linefile_type lf)
{
std::ostringstream result("") ;
if (lf) {
#ifdef VERIFIC_LINEFILE_INCLUDES_COLUMNS
result << lf->GetFileName() ;
result << "[" ;
result << lf->GetLeftLine() ;
result << ":" ;
result << lf->GetLeftCol() ;
result << "]-[" ;
result << lf->GetRightLine() ;
result << ":" ;
result << lf->GetRightCol() ;
result << "]" ;
#else
result << LineFile::GetFileName(lf) ;
result << "[" ;
result << LineFile::GetLineNo(lf) ;
result << "]" ;
#endif
}
return result.str() ;
}

void PrintHierarchy(VeriModule *module, unsigned depth)
{
if (!module) return ; // Ignore NULL netlists

char *prefix = 0 ;
if (depth) {
prefix = Strings::allocate(depth*4 +3) ;
unsigned i ;
for (i = 0; i < (depth *4); i++) prefix[i] = ' ' ;
prefix[i] = 0 ;
}

// Get the scope of the module:
VeriScope *scope = module->GetScope() ;
// Find all the declared ids in this scope:
Map *ids = scope ? scope->DeclArea() : 0 ;
MapIter mi ;
VeriIdDef *id ;
FOREACH_MAP_ITEM(ids, mi, 0, &id) { // Traverse declared ids
if (!id || !id->IsInst()) continue ; // Consider only the instance ids
VeriModuleInstantiation *mod_inst = id->GetModuleInstance() ; // Take the module instance
VeriModule *mod = mod_inst ? mod_inst->GetInstantiatedModule() : 0 ; // The module instance is a module
if (mod) { // This is module instantiation
linefile_type lf = mod->Linefile() ;
const char *location = PrintLocation(lf).c_str() ;
char *inst_mod = Strings::save(prefix ? prefix : "", id->Name(), " (", mod->Name());
Message::PrintLine(inst_mod, " {", location, "})") ;
PrintHierarchy(mod, depth+1) ;
}
}
}

int main()
{
const char *file_name = "top.v" ;
const char *top_name = "top" ;
const char *work_lib = "work" ;

veri_file::AddVFile("mbot.v") ;
veri_file::AddYDir(".") ;
veri_file::AddIncludeDir(".") ;
veri_file::AddLibExt(".v") ;
if (!veri_file::Analyze(file_name, veri_file::VERILOG_2K /*Verilog 2000*/, work_lib)) return 1 ;

if (veri_file::GetModule(top_name)) {
// Optional - statically elaborate all the top Verilog module. Return if any error shows up.
if (!veri_file::ElaborateStatic(top_name)) return 2 ; // statically elaborates all verilog modules in the "work" libarary

VeriModule *top_module = veri_file::GetModule(top_name) ; // Get the pointer to the top-level module
if (!top_module) {
return 3 ; // Exit from application if there is no top module by the given name in the given Verilog designs
}
linefile_type lf = top_module->Linefile() ;
const char *location = PrintLocation(lf).c_str() ;
Message::PrintLine("Top module: ", top_module->Name(), " {", location, "}") ;
PrintHierarchy(top_module, 1) ;
}
return 0 ; // all good
}

</nowiki>

Python script:
<nowiki>
#! /usr/bin/python
import sys
sys.path.append('../../pythonmain/install')
import Verific

def PrintLocation(lf):
result = '';
if lf:
# if 'VERIFIC_LINEFILE_INCLUDES_COLUMNS' is enabled
result = result + lf.GetFileName() + '[' + Verific.Strings.itoa(lf.GetLeftLine()) + ':' \
+ Verific.Strings.itoa(lf.GetLeftCol()) + ']-[' \
+ Verific.Strings.itoa(lf.GetRightLine()) + ':' \
+ Verific.Strings.itoa(lf.GetRightCol()) + ']'
# if 'VERIFIC_LINEFILE_INCLUDES_COLUMNS' is disabled
# result = result + Verific.LineFile.GetFileName(lf) + '[' + Verific.Strings.itoa(Verific.LineFile.GetLineNo(lf)) + ']'
return result

def PrintHierarchy(module, depth):
if not module:
return
prefix = ''
for i in range (depth):
prefix = prefix + ' '
scope = module.GetScope()
ids = scope.DeclArea() # Map of VeriIdDefs
id_iter = Verific.VeriIdDefMapIter(ids)
id = id_iter.First()
while (id):
if (not id.IsInst()):
id = id_iter.Next()
continue
mod_inst = id.GetModuleInstance() # Take the module instance - VeriModuleInstantiation
mod = mod_inst.GetInstantiatedModule() # The module instance is a module - VeriModule
if (not mod):
id = id_iter.Next()
continue
location = PrintLocation(mod.Linefile());
print ('%sInstance %s (%s {%s})' % (prefix, id.Name(), mod.Name(), location))
id = id_iter.Next()
PrintHierarchy(mod, depth+1);

# main
reader = Verific.veri_file()
file_name = 'top.v'
top_name = 'top'
work_lib = 'work'

reader.AddVFile("mbot.v") ;
reader.AddYDir(".") ;
reader.AddIncludeDir(".") ;
reader.AddLibExt(".v") ;

if (not reader.Analyze(file_name, reader.VERILOG_2K, work_lib)):
print ('Error in Analyze')
sys.exit(1)

top_module = reader.GetModule(top_name) ;
if (not top_module):
print ('Error in GetModule')
sys.exit(2)

# Static elaboration is optional
if (not reader.ElaborateStatic(top_name)):
print ('Error in ElaborateStatic')
sys.exit(3)

location = PrintLocation(top_module.Linefile());
print ('\nTop module: %s {%s}' % (top_module.Name(), location))
PrintHierarchy(top_module, 1)

print ('\nDone')

sys.exit(0)

</nowiki>

Input RTL:
<nowiki>
$ cat top.v
// top module
module top(a, b, c, d, e, f, out, m, n, o) ;
input a, b, c, d, e, f, m, n ;
output out, o ;

wire tmp1, tmp2 ;

mid1 i1(a, b, c, d, tmp1) ;
mid1 i2(a, d, e, f, tmp2) ;
mid1 i3(tmp1, tmp2, e, f, out) ;
bot bi(o, m, n);

endmodule
$ cat mid1.v
module mid1 (mid1_inp1, mid1_inp2, mid1_inp3, mid1_inp4, mid1_out,
mid1b_inp1, mid1b_inp2, mid1b_out) ;
input mid1_inp1, mid1_inp2, mid1_inp3, mid1_inp4 ;
output mid1_out ;
input mid1b_inp1, mid1b_inp2 ;
output mid1b_out ;

wire tmp1, tmp2 ;

mid2 m1(mid1_inp1, mid1_inp2, tmp1) ;
mid2 m2(mid1_inp3, mid1_inp4, tmp2) ;
mid2 m3(tmp1, tmp2, mid1_out) ;
bot b(mid1b_inp1, mid1b_inp2, mid1b_out) ;

endmodule
$ cat mid2.v
module mid2 (mid2_inp1, mid2_inp2, mid2_out) ;
input mid2_inp1, mid2_inp2 ;
output mid2_out ;

bot b(mid2_inp1, mid2_inp2, mid2_out) ;

endmodule
$ cat mbot.v

module bot (bot_inp1, bot_inp2, bot_out) ;
input bot_inp1, bot_inp2 ;
output bot_out ;

assign bot_out = bot_inp1 & bot_inp2 ;

endmodule
$
</nowiki>

Run:
<nowiki>
$ test-linux
-- Analyzing Verilog file 'top.v' (VERI-1482)
-- Parsing library file mbot.v (VERI-1482)
-- Analyzing Verilog file 'mbot.v' (VERI-1482)
-- Resolving module 'bot' (VERI-1489)
-- Analyzing Verilog file './mid1.v' (VERI-1482)
-- Resolving module 'mid1' (VERI-1489)
-- Analyzing Verilog file './mid2.v' (VERI-1482)
-- Resolving module 'mid2' (VERI-1489)
top.v(2): INFO: compiling module 'top' (VERI-1018)
top.v(8): WARNING: port 'mid1b_inp1' is not connected on this instance (VERI-2435)
top.v(8): WARNING: port 'mid1b_out' remains unconnected for this instance (VERI-1927)
top.v(9): WARNING: port 'mid1b_inp1' is not connected on this instance (VERI-2435)
top.v(9): WARNING: port 'mid1b_out' remains unconnected for this instance (VERI-1927)
top.v(10): WARNING: port 'mid1b_inp1' is not connected on this instance (VERI-2435)
top.v(10): WARNING: port 'mid1b_out' remains unconnected for this instance (VERI-1927)
top.v(11): WARNING: assignment to input 'n' (VERI-1214)
-- Top module: top {top.v[2:1]-[13:10]}
-- i1 (mid1 {./mid1.v[1:1]-[15:10]})
-- m1 (mid2 {./mid2.v[1:1]-[7:10]})
-- b (bot {mbot.v[2:1]-[8:10]})
-- m2 (mid2 {./mid2.v[1:1]-[7:10]})
-- b (bot {mbot.v[2:1]-[8:10]})
-- m3 (mid2 {./mid2.v[1:1]-[7:10]})
-- b (bot {mbot.v[2:1]-[8:10]})
-- b (bot {mbot.v[2:1]-[8:10]})
-- i2 (mid1 {./mid1.v[1:1]-[15:10]})
-- m1 (mid2 {./mid2.v[1:1]-[7:10]})
-- b (bot {mbot.v[2:1]-[8:10]})
-- m2 (mid2 {./mid2.v[1:1]-[7:10]})
-- b (bot {mbot.v[2:1]-[8:10]})
-- m3 (mid2 {./mid2.v[1:1]-[7:10]})
-- b (bot {mbot.v[2:1]-[8:10]})
-- b (bot {mbot.v[2:1]-[8:10]})
-- i3 (mid1 {./mid1.v[1:1]-[15:10]})
-- m1 (mid2 {./mid2.v[1:1]-[7:10]})
-- b (bot {mbot.v[2:1]-[8:10]})
-- m2 (mid2 {./mid2.v[1:1]-[7:10]})
-- b (bot {mbot.v[2:1]-[8:10]})
-- m3 (mid2 {./mid2.v[1:1]-[7:10]})
-- b (bot {mbot.v[2:1]-[8:10]})
-- b (bot {mbot.v[2:1]-[8:10]})
-- bi (bot {mbot.v[2:1]-[8:10]})
$
</nowiki>

Main Page

2025-07-14T18:52:55Z

Hoa:

'''General'''
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
* [[Source code customization & Stable release services | Source code customization & Stable release services]]
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]
* [[Release version | How do I tell the version of a Verific software release? ]]
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
* [[LineFile data from input files | LineFile data from input files]]
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]
* [[Preserving user nets - preventing nets from being optimized away | Preserving user nets - preventing nets from being optimized away]]
* [[Python pretty-printer for gdb | Python pretty-printer for gdb]]
* [[Yosys-Verific Integration | Yosys-Verific integration]]
* [[How to enable long paths on Windows? | How to enable long paths on Windows?]]

'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Port Expressions]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[Modules with '_1' '_2' suffix in their names | Verilog: After static elaboration, there are modules with "_1", "_2", ..., suffix in their names. Why?]]
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
* [[Notes on analysis | SystemVerilog: Notes on analysis]]
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units/interfaces with "_default" or "or "_1, _2" suffix in their names. What are they?]]
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
'''Netlist Database'''
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]
* [[System attributes | Netlist Database: System attributes]]

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''Scripting languages: TCL, Perl, Python'''
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]

'''Code examples'''
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]
* [[How to use MessageCallBackHandler Class | Util/C++: How to use MessageCallBackHandler Class]]
* [[How to use RegisterPragmaRefCallBack() | Util/C++: How to use RegisterPragmaRefCallBack()]]
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
* [[Extract clock enable | Database/C++: Extract clock enable]]
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
* [[Post processing port resolution of black boxes | Database/C++: Post processing port resolution of black boxes]]
* [[Finding hierarchical paths of a Netlist | Database/C++: Finding hierarchical paths of a Netlist]]
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]
* [[Type Range example | Database/Verilog/C++: Type Range example (simple)]]
* [[Type Range example with multi-dimensional arrays| Database/Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
* [[Using TypeRange table to retrieve the originating type-range for an id | Database/Verilog/C++: Using TypeRange table to retrieve the originating type-range for an id]]
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
* [[How to ignore certain modules while analyzing input RTL files | Verilog/C++: How to ignore certain modules while analyzing input RTL files]]
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
* [[In Verilog parsetree adding names to unnamed instances | Verilog/C++: In Verilog parsetree adding names to unnamed instances]]
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
* [[Getting design hierarchy from input RTL files | Verilog/C++/Python: Getting design hierarchy from input RTL files]]
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]
* [[Parse select modules only and ignore the rest | Verilog/C++: Parse select modules only and ignore the rest]]
* [[Create DOT diagram of parse tree | Verilog/C++: Create DOT diagram of a parse tree]]
* [[How to evaluate a Verilog expression | Verilog/C++: How to evaluate a Verilog expression]]
* [[How to get parameters creation-time initial expression/value after Static Elaboration | Verilog/C++: How to get parameters creation-time initial expression/value after Static Elaboration]]
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
* [[Evaluate 'for-generate' loop | Verilog/C++: Evaluate 'for-generate' loop]]
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
* [[How to replace a statement that has a label | SystemVerilog/C++: How to replace a statement that has a label]]
* [[How to insert/add a statement, or a module item, into a sequential block and a generate block | SystemVerilog/C++: How to insert/add a statement, or a module item, into a sequential block and a generate block]]
* [[Simple examples of VHDL visitor pattern | VHDL/C++: Simple examples of VHDL visitor pattern]]
* [[Traverse instances in parsetree | VHDL/C++: Traverse instances in parsetree]]
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]

'''INVIO Code examples'''
* [[Simple port modification | SystemVerilog/Python: Simple port modification]]

Pretty-print a module and the packages imported by the module

2025-07-01T00:21:43Z

Hoa:

C++:
<nowiki>
#include <iostream>
#include <fstream>

#include "veri_file.h"
#include "VeriModule.h"
#include "VeriId.h"
#include "VeriScope.h"

#include "Map.h"

using namespace std ;

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

void print_packages_used (VeriModule *module, std::ofstream &out_stream)
{
if (!module) return ;
VeriScope *scope = module->GetScope() ;
Set *using_scopes = (scope) ? scope->GetUsing() : 0 ;
SetIter si ;
VeriScope *using_scope ;
FOREACH_SET_ITEM(using_scopes, si, &using_scope) {
VeriIdDef *mod_id2 = using_scope->GetContainingModule() ;
VeriModule *mod2 = (mod_id2) ? mod_id2->GetModule() : 0 ;
print_packages_used (mod2, out_stream) ;
if (mod2->IsPackage()) {
std::cout << ">>> Module '" << module->Name() << "' uses package '" << mod2->Name() << "' <<<\n";
}
out_stream << "// Printing package " << mod2->Name() << endl ;
mod2->PrettyPrint(out_stream, 0) ;
}
}

int main()
{
Array files(1) ;
// files.InsertLast("my_pack.sv") ;
files.InsertLast("test.sv") ;
if (!veri_file::AnalyzeMultipleFiles(&files, veri_file::SYSTEM_VERILOG, "work", veri_file::MFCU)) return 1 ;

MapIter mi ;
VeriModule *module ;
FOREACH_VERILOG_MODULE(mi, module){
if (!module) continue ;

if (module->IsPackage()) continue ; // no need to dive into package
// if (module->IsRootModule()) continue ;

char *outputfilename = Strings::save(module->Name(), "_pp_out.v");
std::ofstream f(outputfilename, std::ios::out) ;
print_packages_used (module, f) ;

// Now print the module:
f << "// Printing module " << module->Name() << endl ;
module->PrettyPrint(f, 0) ;
f.close() ;
}

return 0 ;
}

</nowiki>

Input Verilog:
<nowiki>
package PKG1 ;
typedef int my_int ;
endpackage

typedef byte my_byte ;

module test ;
import PKG1::* ;
my_int int1 ;
my_byte byte1 ;
endmodule
</nowiki>
Console output:
<nowiki>
-- Analyzing Verilog file 'top.v' (VERI-1482)
>>> Module 'top' uses package 'PKG1' <<<
>>> Module 'top' uses package '$unit_top_v' <<<
</nowiki>

Pretty-printed output:
<nowiki>
// Printing package PKG1

package PKG1 ;
typedef int my_int ;
endpackage

// Printing package $unit_test_sv

typedef byte my_byte ;

// Printing module test

module test ;
import PKG1:: * ;
my_int int1 ;
my_byte byte1 ;
endmodule
</nowiki>

Notes on analysis

2025-04-23T17:53:46Z

Hoa:

First, please read this article: [[Defined macros become undefined - MFCU vs SFCU]].

'''Q: Can I use 'veri_file::Analyze()' to read SystemVerilog input files one by one, all of them belonging to one compilation unit?'''

Yes. But if you have multiple files, it’s better to use 'veri_file::AnalyzeMultipleFiles()'.

'veri_file::AnalyzeMultipleFiles()', besides analyzing each file, also:

* opens and ends the compilation unit
* processes –v and –y options
* removes include directories
* processes root module
* undefines user-defined macros, including command-line macros
* resets compile directives (e.g. `default_nettype, `timescale)

If you use 'veri_file::Analyze()' to analyze each file one by one, after all the calls to 'veri_file::Analyze(), depending on the application, you may want to run veri_file::RemoveAllIncludeDirs() and veri_file::EndCompilationUnit().

The TCL command 'analyze' uses the API 'veri_file::AnalyzeMultipleFiles()'. In other words, it assumes a complete compilation unit for each execution.

LineFile data from input files

2025-03-06T17:11:36Z

Hoa:

Verific uses the 'LineFile' manager to preserve line/file origination information from HDL source files. This info is annotated on all objects in parse trees and netlist databases, as well as used in the message handler, so that from any object that Verific creates from an RTL design, information is available as to where it came from in the user's original RTL design.

We have the following compile flags (see util/LineFile.h and util/VerificSystem.h) :

# VERIFIC_LINEFILE_INCLUDES_COLUMNS
#: We define a class ColLineFile to have both the starting and ending locations including column info.
#: Valid values of NUM_LINE_BITS, NUM_COL_BITS and NUM_FILE_BITS are 1 to 31 bits.
#: Use as per your requirements. Making (NUM_LINE_BITS + NUM_COL_BITS) <= 32 will consume less memory.
#: You can use 31 as NUM_FILE_BITS without any extra memory overhead.
#: This flag needs to be enabled for applications using Text-Based Design Modification.
# VERIFIC_LARGE_LINEFILE
#: We still define the class ColLineFile, but it has only a single starting or ending location and does not include column info.
#: Valid values of NUM_LINE_BITS and NUM_FILE_BITS are 1 to 31 bits.
#: Use as per your requirements. Making (NUM_LINE_BITS + NUM_FILE_BITS) <= 32 will consume less memory.
# VERIFIC_LARGE_LINEFILE_FOR_64 (only for 64-bit Windows since long is 4 bytes there)
#: Same as (2) above but without the class and only for 64-bit Windows systems.
# VERILOG_STORE_ENDING_LINEFILE_INFO
#: If this compile flag is ON and VERIFIC_LINEFILE_INCLUDES_COLUMNS is OFF, VeriModuleItem::StartingLinefile() API and VeriModuleItem::EndingLinefile() API will return the correct linefile as per their names. These two functions work for all derived classes of VeriModuleItem (VeriModule, VeriStatement, ....).
#: Note that the compile flag VERILOG_USE_STARTING_LINEFILE_INFO works independently from VERILOG_STORE_ENDING_LINEFILE_INFO. It returns linefile of starting or ending location of a construct via Linefile() API.

The compile flags (1), (2), and (3) above are mutually exclusive. You should have only one of them defined according to your requirements.

If you do not define any of the above compile flags, Verific uses the following by default:

* On a 64-bit (non-Windows) system, line number and file-id are encoded into a 64-bit unsigned long. You need to set (NUM_LINE_BITS + NUM_FILE_BITS) <= 64

* On a 32-bit (and 64-bit Windows) system, line number and file-id are encoded into a 32-bit unsigned long. You need to set (NUM_LINE_BITS + NUM_FILE_BITS) <= 32

If you do not need column numbers or both starting and ending locations, you can turn off column info.

If the number of files overflows NUM_FILE_BITS, we issue "WARNING: number of file names exceeded maximum of %d" when there are too many files. However, producing the same warning for lines/columns would result in too many messages.

How to evaluate a Verilog expression

2025-02-21T17:06:23Z

Hoa:

This applicatione example shows how to evaluate a Verilog expression. It requires Verific 'Static Elaboration' feature.

Note that a, b, and c are declared in the Verilog module. The application evaluates an expression of these variables.

C++:
<nowiki>
#include "veri_file.h"
#include "VeriExpression.h"
#include "VeriModule.h"
#include "VeriBaseValue_Stat.h"

#include "Strings.h"
#include "Array.h"
#include "Map.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main(int argc, const char **argv)
{
const char *file_name = (argc > 1) ? argv[1] : "test.v" ;
const char *module_name = (argc > 2) ? argv[2] : "test_module" ;

Array files(1) ;
files.Insert(file_name) ;
if (!veri_file::AnalyzeMultipleFiles(&files, veri_file::SYSTEM_VERILOG)) return 1 ;

const VeriModule *mod = veri_file::GetModule(module_name) ;
if (!mod) return 2 ;

// Apply following known values to evaluate "a[b] + c":
// a = {1'b1, 1'b1}
// b = 2'b00
// c = 2'b01

const char *expr_string = "a[b] + c" ;
Map known_values(STRING_HASH) ;
(void) known_values.Insert("a", "{1'b1, 1'b1}") ;
(void) known_values.Insert("b", "2'b00") ;
(void) known_values.Insert("c", "2'b01") ;

ValueTable df ;

MapIter mi ;
const char *id_name ;
const char *val_str ;
FOREACH_MAP_ITEM(&known_values, mi, &id_name, &val_str) {
if (!id_name || !val_str) continue ;

// Find the identifier:
VeriIdDef *id = mod->FindDeclared(id_name) ;
if (!id) return 3 ;

// Create the expression:
VeriExpression *expr = veri_file::AnalyzeExpr(val_str, veri_file::SYSTEM_VERILOG) ;
if (!expr) return 4 ;

// Evaluate the expression:
// If this is a literal expression, we do not need the value value or Resolve() call or else we need both:
VeriBaseValue *val = expr->StaticEvaluate(0 /* self context */, 0 /* value table */) ;
delete expr ;
if (!val) return 5 ;

// Insert into the table to be used later:
if (!df.Insert(id, val)) {
delete val ;
return 6 ;
}
}

// Now create the expression for to be evaluated:
VeriExpression *expr = veri_file::AnalyzeExpr(expr_string, veri_file::SYSTEM_VERILOG) ;
if (!expr) return 7 ;

// Resolve the expression so that the id-refs are resolved:
expr->Resolve(mod->GetScope(), VeriTreeNode::VERI_UNDEF_ENV) ;

VeriBaseValue *val = expr->StaticEvaluate(0 /* self context */, &df /* use this table with the known values */) ;
delete expr ;
if (!val) return 8 ; // Failed to evaluate

char *image = val->Image() ;
int result = val->GetIntegerValue() ;
mod->Info("Evaluated value: %s (%d)", ((image)?image:""), result) ;
Strings::free(image) ;
delete val ;

return 0 ;
}
</nowiki>

Verilog testcase:

<nowiki>
module test_module;
wire a [1:0];
wire [1:0] b;
wire [1:0] c;
endmodule
</nowiki>

Run:

<nowiki>
$ test-linux
-- Analyzing Verilog file 'test.v' (VERI-1482)
test.v(5): INFO: Evaluated value: 2'b10 (2)
$
</nowiki>

How to evaluate a Verilog expression

2025-02-20T17:20:55Z

Hoa: Created page with "This applicatione example shows how to evaluate a Verilog expression. Note that it requires 'Static Elaboration' feature. C++: <nowiki> #include "veri_file.h" #include "Veri..."

This applicatione example shows how to evaluate a Verilog expression. Note that it requires 'Static Elaboration' feature.

C++:
<nowiki>
#include "veri_file.h"
#include "VeriExpression.h"
#include "VeriModule.h"
#include "VeriBaseValue_Stat.h"

#include "Strings.h"
#include "Array.h"
#include "Map.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main(int argc, const char **argv)
{
const char *file_name = (argc > 1) ? argv[1] : "test.v" ;
const char *module_name = (argc > 2) ? argv[2] : "test_module" ;

Array files(1) ;
files.Insert(file_name) ;
if (!veri_file::AnalyzeMultipleFiles(&files, veri_file::SYSTEM_VERILOG)) return 1 ;

const VeriModule *mod = veri_file::GetModule(module_name) ;
if (!mod) return 2 ;

// Apply following known values to evaluate "a[b] + c":
// a = {1'b1, 1'b1}
// b = 2'b00
// c = 2'b01

const char *expr_string = "a[b] + c" ;
Map known_values(STRING_HASH) ;
(void) known_values.Insert("a", "{1'b1, 1'b1}") ;
(void) known_values.Insert("b", "2'b00") ;
(void) known_values.Insert("c", "2'b01") ;

ValueTable df ;

MapIter mi ;
const char *id_name ;
const char *val_str ;
FOREACH_MAP_ITEM(&known_values, mi, &id_name, &val_str) {
if (!id_name || !val_str) continue ;

// Find the identifier:
VeriIdDef *id = mod->FindDeclared(id_name) ;
if (!id) return 3 ;

// Create the expression:
VeriExpression *expr = veri_file::AnalyzeExpr(val_str, veri_file::SYSTEM_VERILOG) ;
if (!expr) return 4 ;

// Evaluate the expression:
// If this is a literal expression, we do not need the value value or Resolve() call or else we need both:
VeriBaseValue *val = expr->StaticEvaluate(0 /* self context */, 0 /* value table */) ;
delete expr ;
if (!val) return 5 ;

// Insert into the table to be used later:
if (!df.Insert(id, val)) {
delete val ;
return 6 ;
}
}

// Now create the expression for to be evaluated:
VeriExpression *expr = veri_file::AnalyzeExpr(expr_string, veri_file::SYSTEM_VERILOG) ;
if (!expr) return 7 ;

// Resolve the expression so that the id-refs are resolved:
expr->Resolve(mod->GetScope(), VeriTreeNode::VERI_UNDEF_ENV) ;

VeriBaseValue *val = expr->StaticEvaluate(0 /* self context */, &df /* use this table with the known values */) ;
delete expr ;
if (!val) return 8 ; // Failed to evaluate

char *image = val->Image() ;
int result = val->GetIntegerValue() ;
mod->Info("Evaluated value: %s (%d)", ((image)?image:""), result) ;
Strings::free(image) ;
delete val ;

return 0 ;
}
</nowiki>

Run:

<nowiki>
$ test-linux
-- Analyzing Verilog file 'test.v' (VERI-1482)
test.v(5): INFO: Evaluated value: 2'b10 (2)
$
</nowiki>

Main Page

2025-02-20T17:15:46Z

Hoa:

'''General'''
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
* [[Source code customization & Stable release services | Source code customization & Stable release services]]
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]
* [[Release version | How do I tell the version of a Verific software release? ]]
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
* [[LineFile data from input files | LineFile data from input files]]
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]
* [[Preserving user nets - preventing nets from being optimized away | Preserving user nets - preventing nets from being optimized away]]
* [[Python pretty-printer for gdb | Python pretty-printer for gdb]]
* [[Yosys-Verific Integration | Yosys-Verific integration]]
* [[How to enable long paths on Windows? | How to enable long paths on Windows?]]

'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Port Expressions]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[Modules with '_1' '_2' suffix in their names | Verilog: After static elaboration, there are modules with "_1", "_2", ..., suffix in their names. Why?]]
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
* [[Notes on analysis | SystemVerilog: Notes on analysis]]
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units/interfaces with "_default" or "or "_1, _2" suffix in their names. What are they?]]
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
'''Netlist Database'''
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]
* [[System attributes | Netlist Database: System attributes]]

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''Scripting languages: TCL, Perl, Python'''
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]

'''Code examples'''
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]
* [[How to use MessageCallBackHandler Class | Util/C++: How to use MessageCallBackHandler Class]]
* [[How to use RegisterPragmaRefCallBack() | Util/C++: How to use RegisterPragmaRefCallBack()]]
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
* [[Extract clock enable | Database/C++: Extract clock enable]]
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
* [[Post processing port resolution of black boxes | Database/C++: Post processing port resolution of black boxes]]
* [[Finding hierarchical paths of a Netlist | Database/C++: Finding hierarchical paths of a Netlist]]
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]
* [[Type Range example | Database/Verilog/C++: Type Range example (simple)]]
* [[Type Range example with multi-dimensional arrays| Database/Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
* [[Using TypeRange table to retrieve the originating type-range for an id | Database/Verilog/C++: Using TypeRange table to retrieve the originating type-range for an id]]
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
* [[How to ignore certain modules while analyzing input RTL files | Verilog/C++: How to ignore certain modules while analyzing input RTL files]]
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
* [[In Verilog parsetree adding names to unnamed instances | Verilog/C++: In Verilog parsetree adding names to unnamed instances]]
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]
* [[Parse select modules only and ignore the rest | Verilog/C++: Parse select modules only and ignore the rest]]
* [[Create DOT diagram of parse tree | Verilog/C++: Create DOT diagram of a parse tree]]
* [[How to evaluate a Verilog expression | Verilog/C++: How to evaluate a Verilog expression]]
* [[How to get parameters creation-time initial expression/value after Static Elaboration | Verilog/C++: How to get parameters creation-time initial expression/value after Static Elaboration]]
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
* [[Evaluate 'for-generate' loop | Verilog/C++: Evaluate 'for-generate' loop]]
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
* [[How to replace a statement that has a label | SystemVerilog/C++: How to replace a statement that has a label]]
* [[How to insert/add a statement, or a module item, into a sequential block and a generate block | SystemVerilog/C++: How to insert/add a statement, or a module item, into a sequential block and a generate block]]
* [[Simple examples of VHDL visitor pattern | VHDL/C++: Simple examples of VHDL visitor pattern]]
* [[Traverse instances in parsetree | VHDL/C++: Traverse instances in parsetree]]
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]

'''INVIO Code examples'''
* [[Simple port modification | SystemVerilog/Python: Simple port modification]]

Modules with ' 1' ' 2' suffix in their names

2024-10-19T01:41:15Z

Hoa:

'''>>> This article will be merged with [http://www.verific.com/faq/index.php?title=Modules/design_units_with_%22_default%22_suffix_in_their_names this article] <<<'''

Static elaboration process adds the suffix "_<number>" to the module name when:
#Module contains hierarchical identifier(s), and
#Hierarchical identifier(s) in that module point(s) to different objects depending on the hierarchical position of that module instance.

An example :

<nowiki>
module test ;
parameter p = 12 ;
mod I() ;
foo I2() ;
endmodule

module foo ;
test1 test() ;
endmodule

module test1 ;
parameter p = 2 ;
mod I3() ;
endmodule

module mod ;
initial $display(test.p) ; // This is hierarchical identifier
endmodule
</nowiki>

The hierarchy is:

<nowiki>
test (top module)
I (mod)
I2 (foo)
test (test1)
I3 (mod)
</nowiki>

So here module 'mod' is instantiated twice in the hierarchy. The hierarchical identifier 'test.p' inside module 'mod', can refer to parameter 'p' inside top level module 'test' for the instance 'I' of module 'mod'; but it can also refer to parameter 'p' inside module 'test1' for the instance 'I3' of module 'mod'. In other words, the prefix 'test' can refer to module 'test' (top module) or instance 'top' inside module 'foo'.

In the example above, one hierarchical name can refer to different objects in the hierarchy. In this situation static elaboration creates 2 different copies of module 'mod' and their names are differentiated by adding "_<number>" ('mod_2' and 'mod_3'). Hierarchical identifiers in these two modules are resolved with proper identifiers.

The parsetree after static elaboration:

<nowiki>
module test ;
parameter p = 12 ;
mod_2 I () ;
foo I2 () ;
endmodule

module foo ;
test1 test () ;
endmodule

module test1 ;
parameter p = 2 ;
mod_3 I3 () ;
endmodule

module mod ;
initial
$display (test.p) ;
endmodule

module mod_2 ;
initial
$display (test.p) ;
endmodule

module mod_3 ;
initial
$display (test.p) ;
endmodule
</nowiki>

The design hierarchy is:
<nowiki>
test (top module)
I (mod_2)
I2 (foo)
test (test1)
I3 (mod_3)
</nowiki>

The original module 'mod' is not instantiated.

Remove Verific data structures

2024-10-19T01:15:21Z

Hoa:

'''Q: How do I remove all Verific data structures in memory?'''

To remove hdl file sorting data:

hdl_file_sort::Reset();

To reset file system cache:

FileSystem::ResetDirectoryCache();

To remove Verilog parsetree:

veri_file::Reset();

To remove VHDL parsetree:

vhdl_file::Reset();

To remove synlib parsetree:

synlib_file::Reset();

To remove hierarchy tree:

hier_tree::DeleteHierarchicalTree() ;

To remove UPF data structures:

upf_file::DeleteAll();

To remove the netlist database:

Libset::Reset();

To remove linefile data (make sure that you've removed all parsetrees and the netlist database):

LineFile::DeleteAllLineFiles();
LineFile::ResetFileIdMaps();

To remove message type settings:

Message::Reset();

To reset run-time flags:

RuntimeFlags::DeleteAllFlags();

Modules/design units with " default" suffix in their names

2024-10-19T01:11:23Z

Hoa:

<pre style="color: red"> This article is currently under construction </pre>

'''Q: After static elaboration, there are modules/design units with "_default" or "_1, _2" suffix in their names. Why? And what are they? '''

==== Modules with "_default" suffix ====

Static elaboration process is a multiple-iteration process and modules/design units may be modified differently in each iteration.

We need to keep original version of modules/design units as they are immediately after analysis so that they can be copied for different parameter/generic settings in each iteration and body of copied modules/design units can be elaborated (generate unroll, array instance processing, etc.) differently for each parameter/generic setting.

Another reason to copy instantiated modules/design units with "_default" name is in mixed language elaboration. Here a Verilog module may instantiate a VHDL entity which has been elaborated earlier with different generic values. In that case during Verilog elaboration we will not get original contents of instantiated entity.

Moreover, to support incremental elaboration we need to keep original modules/design units, as lower level units can be elaborated earlier.

In Verilog, we have a runtime-flag "veri_remove_suffix_default_from_copied_module_names" to rename modules from "<orig_name>_default" to "<orig_name>". This will work only when runtime-flag "veri_cleanup_base_modules" is set.

==== Interfaces with "_default" suffix ====

SystemVerilog interfaces can be used in any of the following ways :

* As interface instantiations.
* As interface ports.
* As virtual interfaces.
* As hierarchical names.

Interface is always copied with '_default' suffix since we do not know for sure if there is a virtual interface in the hierarchy below which is yet to be processed.

The copied interface (with '_default' suffix) will be the one that is elaborated and specified in the virtual interface declaration, interface instance, or top-level module port. Every instantiated module containing interface type ports will also be copied during static elaboration since its interface port names may have been modified as well.

Virtual interfaces can appear in many different parts of a design, and may or may not be associated with interface instances. Virtual interfaces are not stored in Verific's pseudo-tree, so after static elaboration we do not know whether an interface is used as a virtual interface or not, or where it is being used. Without this knowledge, we cannot arbitrarily change all the references of an interface from '<interface_name>_default' to '<interface_name> because the references may become invalid. Because of this, we do not have flags to remove the '_default' from the interface names as we do for modules.

The '_default_<n>' suffix may also be added due to the presence of hierarchical references in an interface or bind statements containing interface instantiations.

Verific VIPER #19809 has more details.

==== Modules with "_<N>" suffix ====

Modules can be copied with _<N> suffix for hier-ref present/going via them.

Example:
<nowiki>
module top ;
test t () ;
test #(0) t0 () ;
test #(1) t1 () ;
test #(2) t2 () ;
endmodule

module test ;
parameter P = 0 ;
wire [P:0] sig ;
bot b1 () ;
endmodule

module bot ;
initial $display(test.sig) ;
endmodule
</nowiki>

Here "bot" has to be copied 3 times with _<N> suffix so that they can point to 3 different "sig" of 3 different sizes.
The same can happen for bind statements as well. Different bind instances can be added to different instances of the same module.

==== Modules with "_copy<N>" suffix ====

Modules can be copied with _copy<N> suffix when a module with _<N> is already present in the same library.

Example:
<nowiki>
module top ;
test t () ;
test #(0) t0 () ;
test #(1) t1 () ;
test #(2) t2 () ;
endmodule

module test ;
parameter P = 0 ;
wire [P:0] sig ;
bot b1 () ;
endmodule

module bot ;
initial $display(test.sig) ;
endmodule

module bot_2 ;
endmodule
</nowiki>

Here "bot_2" already exists and hence the copied "bot" which we wanted to name "bot_2" is renamed to "bot_copy<N>".

==== Modules with "_<N>_<M>" suffix ====

Modules can even be copied with _<N>_<M> suffix in some corner cases with name conflict as well as hier-refs.

Example:
<nowiki>
module top ;
test t () ;
test #(0) t0 () ;
test #(1) t1 () ;
test #(2) t2 () ;
bot_2 b1 () ;
endmodule

module test ;
parameter P = 0 ;
wire [P:0] sig ;
bot b1 () ;
endmodule

module bot ;
initial $display(test.sig) ;
endmodule

module bot_2 ;
generate
test #(2) t1 () ;
endgenerate
endmodule
</nowiki>

Here instead of "bot_copy<N>", one of the elaborated versions of "bot" which is to be renamed to "bot_2" is actually named as "bot_2_1".

==== How to get the original name or the original module ====

APIs to retrieve the original name of the module or to get the original module itself (only when the original module is available):

<nowiki>
VeriModule::GetOriginalModuleName()
VeriModule::GetOriginalModule()
</nowiki>

Modules with ' 1' ' 2' suffix in their names

2024-10-19T01:10:20Z

Hoa:

<pre style="color: red"> This article will be merged with another article </pre>

Static elaboration process adds the suffix "_<number>" to the module name when:
#Module contains hierarchical identifier(s), and
#Hierarchical identifier(s) in that module point(s) to different objects depending on the hierarchical position of that module instance.

An example :

<nowiki>
module test ;
parameter p = 12 ;
mod I() ;
foo I2() ;
endmodule

module foo ;
test1 test() ;
endmodule

module test1 ;
parameter p = 2 ;
mod I3() ;
endmodule

module mod ;
initial $display(test.p) ; // This is hierarchical identifier
endmodule
</nowiki>

The hierarchy is:

<nowiki>
test (top module)
I (mod)
I2 (foo)
test (test1)
I3 (mod)
</nowiki>

So here module 'mod' is instantiated twice in the hierarchy. The hierarchical identifier 'test.p' inside module 'mod', can refer to parameter 'p' inside top level module 'test' for the instance 'I' of module 'mod'; but it can also refer to parameter 'p' inside module 'test1' for the instance 'I3' of module 'mod'. In other words, the prefix 'test' can refer to module 'test' (top module) or instance 'top' inside module 'foo'.

In the example above, one hierarchical name can refer to different objects in the hierarchy. In this situation static elaboration creates 2 different copies of module 'mod' and their names are differentiated by adding "_<number>" ('mod_2' and 'mod_3'). Hierarchical identifiers in these two modules are resolved with proper identifiers.

The parsetree after static elaboration:

<nowiki>
module test ;
parameter p = 12 ;
mod_2 I () ;
foo I2 () ;
endmodule

module foo ;
test1 test () ;
endmodule

module test1 ;
parameter p = 2 ;
mod_3 I3 () ;
endmodule

module mod ;
initial
$display (test.p) ;
endmodule

module mod_2 ;
initial
$display (test.p) ;
endmodule

module mod_3 ;
initial
$display (test.p) ;
endmodule
</nowiki>

The design hierarchy is:
<nowiki>
test (top module)
I (mod_2)
I2 (foo)
test (test1)
I3 (mod_3)
</nowiki>

The original module 'mod' is not instantiated.

Main Page

2024-10-19T01:08:38Z

Hoa:

'''General'''
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
* [[Source code customization & Stable release services | Source code customization & Stable release services]]
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]
* [[Release version | How do I tell the version of a Verific software release? ]]
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
* [[LineFile data from input files | LineFile data from input files]]
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]
* [[Preserving user nets - preventing nets from being optimized away | Preserving user nets - preventing nets from being optimized away]]
* [[Python pretty-printer for gdb | Python pretty-printer for gdb]]
* [[Yosys-Verific Integration | Yosys-Verific integration]]

'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Port Expressions]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[Modules with '_1' '_2' suffix in their names | Verilog: After static elaboration, there are modules with "_1", "_2", ..., suffix in their names. Why?]]
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
* [[Notes on analysis | SystemVerilog: Notes on analysis]]
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units/interfaces with "_default" or "or "_1, _2" suffix in their names. What are they?]]
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
'''Netlist Database'''
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]
* [[System attributes | Netlist Database: System attributes]]

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''Scripting languages: TCL, Perl, Python'''
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]

'''Code examples'''
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]
* [[How to use MessageCallBackHandler Class | Util/C++: How to use MessageCallBackHandler Class]]
* [[How to use RegisterPragmaRefCallBack() | Util/C++: How to use RegisterPragmaRefCallBack()]]
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
* [[Extract clock enable | Database/C++: Extract clock enable]]
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
* [[Post processing port resolution of black boxes | Database/C++: Post processing port resolution of black boxes]]
* [[Finding hierarchical paths of a Netlist | Database/C++: Finding hierarchical paths of a Netlist]]
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]
* [[Type Range example | Database/Verilog/C++: Type Range example (simple)]]
* [[Type Range example with multi-dimensional arrays| Database/Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
* [[Using TypeRange table to retrieve the originating type-range for an id | Database/Verilog/C++: Using TypeRange table to retrieve the originating type-range for an id]]
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
* [[How to ignore certain modules while analyzing input RTL files | Verilog/C++: How to ignore certain modules while analyzing input RTL files]]
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
* [[In Verilog parsetree adding names to unnamed instances | Verilog/C++: In Verilog parsetree adding names to unnamed instances]]
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]
* [[Parse select modules only and ignore the rest | Verilog/C++: Parse select modules only and ignore the rest]]
* [[Create DOT diagram of parse tree | Verilog/C++: Create DOT diagram of a parse tree]]
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
* [[Evaluate 'for-generate' loop | Verilog/C++: Evaluate 'for-generate' loop]]
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
* [[How to replace a statement that has a label | SystemVerilog/C++: How to replace a statement that has a label]]
* [[How to insert/add a statement, or a module item, into a sequential block and a generate block | SystemVerilog/C++: How to insert/add a statement, or a module item, into a sequential block and a generate block]]
* [[Simple examples of VHDL visitor pattern | VHDL/C++: Simple examples of VHDL visitor pattern]]
* [[Traverse instances in parsetree | VHDL/C++: Traverse instances in parsetree]]
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]

'''INVIO Code examples'''
* [[Simple port modification | SystemVerilog/Python: Simple port modification]]

Modules/design units with " default" suffix in their names

2024-10-19T01:06:43Z

Hoa:

<pre style="color: red"> This article is currently under construction </pre>

'''Q: After static elaboration, there are modules/design units with "_default" or "_1, _2" suffix in their names. Why? And what are they? '''

==== Modules with "_default" suffix ====

Static elaboration process is a multiple-iteration process and modules/design units may be modified differently in each iteration.

We need to keep original version of modules/design units as they are immediately after analysis so that they can be copied for different parameter/generic settings in each iteration and body of copied modules/design units can be elaborated (generate unroll, array instance processing, etc.) differently for each parameter/generic setting.

Another reason to copy instantiated modules/design units with "_default" name is in mixed language elaboration. Here a Verilog module may instantiate a VHDL entity which has been elaborated earlier with different generic values. In that case during Verilog elaboration we will not get original contents of instantiated entity.

Moreover, to support incremental elaboration we need to keep original modules/design units, as lower level units can be elaborated earlier.

In Verilog, we have a runtime-flag "veri_remove_suffix_default_from_copied_module_names" to rename modules from "<orig_name>_default" to "<orig_name>". This will work only when runtime-flag "veri_cleanup_base_modules" is set.

==== Interfaces with "_default" suffix ====

SystemVerilog interfaces can be used in any of the following ways :

* As interface instantiations.
* As interface ports.
* As virtual interfaces.
* As hierarchical names.

Interface is always copied with '_default' suffix since we do not know for sure if there is a virtual interface in the hierarchy below which is yet to be processed.

The copied interface (with '_default' suffix) will be the one that is elaborated and specified in the virtual interface declaration, interface instance, or top-level module port. Every instantiated module containing interface type ports will also be copied during static elaboration since its interface port names may have been modified as well.

Virtual interfaces can appear in many different parts of a design, and may or may not be associated with interface instances. Virtual interfaces are not stored in Verific's pseudo-tree, so after static elaboration we do not know whether an interface is used as a virtual interface or not, or where it is being used. Without this knowledge, we cannot arbitrarily change all the references of an interface from '<interface_name>_default' to '<interface_name> because the references may become invalid. Because of this, we do not have flags to remove the '_default' from the interface names as we do for modules.

The '_default_<n>' suffix may also be added due to the presence of hierarchical references in an interface or bind statements containing interface instantiations.

==== Modules with "_<N>" suffix ====

Modules can be copied with _<N> suffix for hier-ref present/going via them.

Example:
<nowiki>
module top ;
test t () ;
test #(0) t0 () ;
test #(1) t1 () ;
test #(2) t2 () ;
endmodule

module test ;
parameter P = 0 ;
wire [P:0] sig ;
bot b1 () ;
endmodule

module bot ;
initial $display(test.sig) ;
endmodule
</nowiki>

Here "bot" has to be copied 3 times with _<N> suffix so that they can point to 3 different "sig" of 3 different sizes.
The same can happen for bind statements as well. Different bind instances can be added to different instances of the same module.

==== Modules with "_copy<N>" suffix ====

Modules can be copied with _copy<N> suffix when a module with _<N> is already present in the same library.

Example:
<nowiki>
module top ;
test t () ;
test #(0) t0 () ;
test #(1) t1 () ;
test #(2) t2 () ;
endmodule

module test ;
parameter P = 0 ;
wire [P:0] sig ;
bot b1 () ;
endmodule

module bot ;
initial $display(test.sig) ;
endmodule

module bot_2 ;
endmodule
</nowiki>

Here "bot_2" already exists and hence the copied "bot" which we wanted to name "bot_2" is renamed to "bot_copy<N>".

==== Modules with "_<N>_<M>" suffix ====

Modules can even be copied with _<N>_<M> suffix in some corner cases with name conflict as well as hier-refs.

Example:
<nowiki>
module top ;
test t () ;
test #(0) t0 () ;
test #(1) t1 () ;
test #(2) t2 () ;
bot_2 b1 () ;
endmodule

module test ;
parameter P = 0 ;
wire [P:0] sig ;
bot b1 () ;
endmodule

module bot ;
initial $display(test.sig) ;
endmodule

module bot_2 ;
generate
test #(2) t1 () ;
endgenerate
endmodule
</nowiki>

Here instead of "bot_copy<N>", one of the elaborated versions of "bot" which is to be renamed to "bot_2" is actually named as "bot_2_1".

==== How to get the original name or the original module ====

APIs to retrieve the original name of the module or to get the original module itself (only when the original module is available):

<nowiki>
VeriModule::GetOriginalModuleName()
VeriModule::GetOriginalModule()
</nowiki>

Simple example of visitor pattern

2024-09-06T23:04:57Z

Hoa:

Example 1:
<nowiki>
$ cat test.cpp
#include <iostream>
#include "veri_file.h"
#include "VeriModule.h"
#include "VeriVisitor.h"
#include "VeriConstVal.h"
#include "Map.h"
#include "Strings.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

class MyVisitor : public VeriVisitor
{
public:
MyVisitor() : VeriVisitor() { }
virtual ~MyVisitor() { }

virtual void VERI_VISIT(VeriConst, node)
{
char *str = node.GetPrettyPrintedString() ;
node.Info("Got expression: %s", str) ;
Strings::free(str) ;
}
} ;

int main (int argc, char **argv)
{
const char *file_name = "test.sv" ; // defaulf input filename
if (argc > 1) file_name = argv[1] ; // Set the file name as specified by the user
// veri_file::Analyze(const char *file_name, unsigned verilog_mode=VERILOG_2K, const char *lib_name="work", unsigned cu_mode=NO_MODE) ;
if (!veri_file::Analyze(file_name, veri_file::SYSTEM_VERILOG)) return 1 ;

// if (!veri_file::ElaborateAllStatic()) return 1 ;

MyVisitor mv ;

MapIter mi ;
VeriModule *mod ;
FOREACH_VERILOG_MODULE(mi, mod) if (mod) mod->Accept(mv) ;

return 0 ;
}

$ cat test.sv
module test ;
(* a = 1, b = 2.6 *) wire w ;
assign w = 2'b00 ;
endmodule

$ test-linux
-- Analyzing Verilog file 'test.sv' (VERI-1482)
test.sv(2): INFO: Got expression: 1
test.sv(2): INFO: Got expression: 2.6
test.sv(3): INFO: Got expression: 2'b0
$
</nowiki>
Example 2:
<nowiki>
$ cat test.cpp
#include <iostream>
#include "veri_file.h"
#include "VeriModule.h"
#include "VeriVisitor.h"
#include "VeriExpression.h"
#include "VeriId.h"
#include "Strings.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

class MyVisitor : public VeriVisitor
{
public:
MyVisitor() : VeriVisitor() { }
virtual ~MyVisitor() { }

virtual void VERI_VISIT(VeriBindDirective, node)
{
char *str = node.GetPrettyPrintedString() ;
std::cout << " bind directive: " << str;
Strings::free(str) ;
VeriModuleItem *verimoduleitem = node.GetInstantiation();
if (verimoduleitem->IsInstantiation()) {
VeriModuleInstantiation *instantiation = static_cast <VeriModuleInstantiation *>(verimoduleitem);
str = instantiation->GetPrettyPrintedString() ;
std::cout << " instantiation: " << str ;
VeriModule *mod = instantiation->GetInstantiatedModule();
if (mod) {
std::cout << " instantiated module: " << mod->Name() << "\n";;
}
Array *ids = instantiation->GetIds();
unsigned i;
VeriInstId *instid;
FOREACH_ARRAY_ITEM (ids, i, instid) {
std::cout << " instance name: " << instid->Name() << "\n";;
}
Strings::free(str) ;
}
Array *target_inst_list = node.GetTargetInstanceList();
unsigned i;
VeriExpression *target_instance ;
FOREACH_ARRAY_ITEM(target_inst_list, i, target_instance) {
if (!target_instance) continue ;
char *str = target_instance->GetPrettyPrintedString() ;
std::cout << " target_instance: " << str;
Strings::free(str) ;
std::cout << "\n";
}
}
} ;

int main(int argc, char **argv)
{
if (!veri_file::Analyze("test.v", veri_file::SYSTEM_VERILOG)) return 1 ;

MyVisitor mv ;

MapIter mi ;
VeriModule *mod ;
FOREACH_VERILOG_MODULE(mi, mod) if (mod) mod->Accept(mv) ;

return 0 ;
}

$ cat test.v
module test;
sub inst();
endmodule

module foo;
endmodule

bind test.inst foo i_foo(.*);

$ test-linux
-- Analyzing Verilog file 'test.v' (VERI-1482)
bind directive: bind test.inst foo i_foo (.* ) ;
instantiation: foo i_foo (.* ) ;
instantiated module: foo
instance name: i_foo
target_instance: test.inst

$
</nowiki>

Support IEEE 1735 encryption standard

2024-07-25T05:27:36Z

Hoa:

'''Q: Does Verific provide support for IEEE 1735 encryption standard?'''

''Note: This article mentions only "encryption/decryption '''algorithms'''," but the same arguments also apply to "decryption/encryption '''keys'''."''

Verific provides APIs with which the licensees can plug in their proprietary encryption/decryption algorithms.

For technical details, please see:

[http://www.verific.com/docs/index.php?title=Parsing_Protected_and_IEEE_1735_Encrypted_RTL_Files Parsing Protected and IEEE 1735 Encrypted RTL Files]
(contact Verific Tech Support if you don't have credentials for Verific Documentation).

There are application examples in Verific distribution:

examples/verilog/parse_encrypted_RTL
examples/verilog/parse_encrypted_RTL_1735style

Verific does not implement nor provide encryption/decryption algorithms for several reasons:

* If Verific were to provide encryption algorithms, Verific would have to provide the decryption algorithms. Verific has always been shipping source code and is not set up to ship binaries. If Verific shipped the implementations of the encryption/decryption algorithms in the form of C++ source code, that would defeat the purpose of encryption in the first place.

* If Verific provided encryption/decryption algorithms, it would ship the same implementations to all of its licensees. Many licensees of Verific are direct competitors. A company would not want its competitors to have access to its encryption/decryption algorithms.

* As the provider of encryption/decryption algorithms, Verific would be responsible for providing measures to prevent security breaching. Since the encryption/decryption implementations were shipped to multiple licensees, there would be no guarantee that the algorithms would enjoy the same protection as the licensees' IPs would. It is not fair nor practical to expect Verific to bear the responsibility.

So the task of encryption/decryption implementations is appropriately reserved to the licensee.

How to parse a string

2024-06-18T17:10:19Z

Hoa:

Let's say you want to add a node to the parse tree.

One simple way to do so is to start with a text string, then "parse" that string to get a VHDL or Verilog construct. The construct can then be added to the parse tree.

Below are the APIs to parse a string:

'''Verilog:'''
* VeriExpression *veri_file::AnalyzeExpr(const char *expr, unsigned verilog_mode=VERILOG_2K, const linefile_type line_file = 0)
* VeriModuleItem *veri_file::AnalyzeModuleItem(const char *module_item, unsigned verilog_mode=VERILOG_2K, const linefile_type line_file = 0, VeriScope *container_scope = 0)
* VeriStatement *veri_file::AnalyzeStatement(const char *statement, unsigned verilog_mode=VERILOG_2K, const linefile_type line_file = 0, VeriScope *container_scope = 0)
Notes for Verilog :
:- appropriate scope information where the given string is valid should be passed to the APIs for them to work properly
:- need to call Resolve() on the returned parse tree nodes with proper scope where these items will be used
:- VeriTreeNode::VERI_UNDEF_ENV can be passed as the Resolve() environment
:- if required the nodes can be added to the existing parse tree using the appropriate APIs

'''VHDL:'''
* VhdlExpression *vhdl_file::AnalyzeExpr(const char *expr, unsigned vhdl_mode=VHDL_93, const linefile_type line_file=0)
* VhdlStatement *vhdl_file::AnalyzeSequentialStatement(const char *statement, unsigned vhdl_mode = VHDL_93, const char *lib_name = "work", const linefile_type line_file = 0, * VhdlScope *container_scope = 0)
* VhdlStatement *vhdl_file::AnalyzeConcurrentStatement(const char *statement, unsigned vhdl_mode = VHDL_93, const char *lib_name = "work", const linefile_type line_file = 0, VhdlScope *container_scope = 0)
* VhdlDesignUnit *vhdl_file::AnalyzeUnit(const char *unit, unsigned vhdl_mode = VHDL_93, const char *lib_name = "work", const linefile_type line_file = 0)
Notes for VHDL :
:- appropriate scope information where the given string is valid should be passed to the APIs for them to work properly
:- need vhdl_file::AnalyzeSequentialStatement() as well as vhdl_file::AnalyzeConcurrentStatement() to differentiate between the starting points of the two
:- Verilog AnalyzeModuleItem() = both VHDL AnalyzeConcurrentStatement() and VHDL AnalyzeUnit()
:- Verilog AnalyzeStatement() = VHDL AnalyzeSequentialStatement()

An example excerpt of C++ code using AnalyzeExpr() is as follows :
VeriExpression *expr = veri_file::AnalyzeExpr(expr_string, veri_file::SYSTEM_VERILOG);
VeriScope *current_scope = module->GetScope() ;
if (expr) {
expr->Resolve(current_scope, VeriTreeNode::VERI_UNDEF_ENV);
// plus anything else user may want to add
}

Full designs can be analyzed from strings as well. Please use streams for that.
See [https://www.verific.com/docs/index.php?title=Analyzing_Stream_Inputs Analyzing Stream Inputs]

Below is a C++ code example of using string parsing (veri_file::AnalyzeModuleItem()) to add a module to the parsetree.

<nowiki>
#include <iostream>

#include "veri_file.h"
#include "VeriModule.h"
#include "VeriId.h"
#include "VeriScope.h"
#include "VeriLibrary.h"
#include "DataBase.h"
#include "VeriWrite.h"

#include "Array.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main(void)
{
// Analyze the file:
Array files(1) ;
files.InsertLast("test.v") ;
if (!veri_file::AnalyzeMultipleFiles(&files, veri_file::SYSTEM_VERILOG, "work")) return 1 ;

// Get the 'top' module:
VeriModule *top = veri_file::GetModule("test") ;
if (!top) return 2 ;

// Get the library of the 'top' module:
VeriLibrary *work_lib = top->GetLibrary() ;
if (!work_lib) return 4 ;

// Get the compilation unit of the 'top' module and then the compilation unit scope where the class is declared:
VeriModule *root = top->GetCompilationUnit() ;
VeriScope *scope = (root) ? root->GetScope() : 0 ;

// Analyze a new module under the scope of the compilation unit:
linefile_type dummy_lf = LineFile::EncodeLineFile("read-from-string", 1) ;
VeriModuleItem *mi = veri_file::AnalyzeRootItem("module new_module ( RESET, SET, CLK, IN, O );parameter INIT = 1'b0;input RESET;input SET;input CLK;input IN;output reg O = INIT;endmodule", veri_file::SYSTEM_VERILOG, dummy_lf, scope) ;
if (!mi) return 5 ;

// Get the identifier of the module item:
VeriIdDef *id = mi->GetId() ;
if (!id) return 6 ;

// Get the VeriModule * from the identifier of the module:
// This will return NULL if it is not actually a module.
VeriModule *mod = id->GetModule() ;
if (!mod) return 7 ;

// Add to user defined library:
VeriLibrary *user_define_lib = veri_file::GetLibrary("new_lib", 1 /* create if needed */) ;
VERIFIC_ASSERT(user_define_lib) ; // Must be there, should be created if it was not there
if (!user_define_lib->AddModule(mod)) return 8 ;

mod->Resolve(scope, VeriTreeNode::VERI_UNDEF_ENV) ;

veri_file::PrettyPrint("pp.v.golden.new", 0) ;

// Finally, elaborate the top module:
veri_file::AddLOption("user_define_lib") ;
if (!veri_file::Elaborate("test")) return 9 ;

Netlist *top_nl = Netlist::PresentDesign() ;
if (!top_nl) return 10 ;

VeriWrite vw ;
vw.WriteFile ("netlist_out.v.golden.new", top_nl) ;

return 0 ;
}
</nowiki>

Source code customization & Stable release services

2024-05-08T17:23:51Z

Hoa:

On Verific's system, each of our licensees has a separate code branch. There are mechanisms in place to prevent cross-contamination among code branches, helping to ensure their privacy and security. With this implementation Verific is able to offer two complimentary services to our licensees : ''Source Code Customization'' and ''Stable Release Maintenance''.

'''1. Source Code Customization
'''

A licensee can send in custom code modifications to be merged into their branch maintained by Verific. The customizations will be included in future source code releases so that the licensee will not need to merge them manually each time. Please note the following :

* The modified code should be complete and compilable on Verific's system.

* Zip the modified code with the same password used for the monthly code releases.

* Mention the Verific release version that the modifications are based upon.

The licensee can include testcases that exercise the customized code. These testcases will be added to the regression testsuite of the licensee's code branch.

The best way to initiate this process is for the licensee to file a VIPER issue with Type "Merge Request" and attach the zip file of the code modifications to the VIPER issue. This VIPER issue will be closed (not just "fixed") when the code merge has been completed. The licensee will receive an email notice when the VIPER issue is closed.

'''Important notes:''' Verific will maintain the code changes, but the ownership still lies with the customer and issues arising from it, if any, need to be corrected by the customer.

'''2. Stable Release Maintenance
'''

A Stable release is a physically separate branch of a licensee's code on Verific's system. It is treated as a distinct "customer" branch. There are no connections between a Stable branch and the licensee's normal branch. A Stable branch is usually requested by a licensee when a specific monthly normal branch has been extensively tested and integrated into the licensee's tool and there is a need to maintain this branch of code for a longer period of time than the regular monthly Verific releases. Some notes to keep in mind about the Stable branch :

* After creation, Stable branch code can only be changed to fix Stable branch VIPER issues. VIPER issues filed for a Stable branch are treated as "customer-specific". In other words, VIPER fixes in a Stable branch don't go into the normal branch and, likewise, VIPER fixes in the normal branch don't go into a Stable branch.

* To avoid having new issues introduced into a Stable branch, only defect (not enhancement) VIPERs are allowed for a Stable branch.

* If an issue needs to be fixed in both a Stable branch and in the normal branch, two separate VIPER issues will need to be filed : one for the Stable branch and one for the normal branch.

* Stable branch code can not be merged into normal branch code.

* When a Stable branch has served its purpose and is ready to be retired, the licensee should inform Verific about this decision as soon as possible. We will then archive the branch and stop its maintenance, helping to free up our time and resources.

Using TypeRange table to retrieve the originating type-range for an id

2024-04-23T18:35:47Z

Hoa: Created page with "C++: <nowiki> #include "veri_file.h" #include "DataBase.h" #include "Map.h" #include "Set.h" #ifdef VERIFIC_NAMESPACE using namespace Verific ; #endif int main() { Runt..."

C++:
<nowiki>
#include "veri_file.h"
#include "DataBase.h"
#include "Map.h"
#include "Set.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main()
{
RuntimeFlags::SetVar("db_preserve_user_nets", 1) ;

// Need to set this flag
RuntimeFlags::SetVar("db_add_id_vs_netbus_map", 1) ;

if (!veri_file::Analyze("test.sv", veri_file::SYSTEM_VERILOG)) return 1 ;
if (!veri_file::ElaborateAll()) return 2 ;

Netlist *netlist = Netlist::PresentDesign() ;
if (!netlist) return 3 ;

const char *id_name = 0 ;
const TypeRange *type_range = 0 ;
char *tr_str = 0 ;

#if 1 // To get the originating type-range for an id (e.g. 'a[0].AW')
id_name = "a[0].AW" ;
type_range = netlist->GetTypeRange(id_name, 1) ;
tr_str = (type_range) ? type_range->Dump() : 0 ;
netlist->Info("'%s' is created from type '%s'", id_name, tr_str) ;
Strings::free(tr_str) ;

#else // To get the originating type-ranges for all nets/buses
const Map *type_ranges = netlist->GetTypeRangeTable() ;
if (!type_ranges) return 4 ;

const Map *id_vs_nets = netlist->GetIdNetsTable() ;
if (!id_vs_nets) return 5 ;

// Create a mapping of all nets/buses to Verilog id from where they are created:
Map net_or_bus_2_id(POINTER_HASH) ;
MapIter mi ;
const Set *net_or_buses ;
DesignObj *net_or_bus ;
FOREACH_MAP_ITEM(id_vs_nets, mi, &id_name, &net_or_buses) {
SetIter si ;
FOREACH_SET_ITEM(net_or_buses, si, &net_or_bus) {
(void) net_or_bus_2_id.Insert(net_or_bus, id_name) ;
}
}

// Now get the id-name of all nets/buses from the above mapping and find them from the type-range table.
Set done_buses(POINTER_HASH) ;
const Net *net ;
const NetBus *bus ;
FOREACH_NET_OF_NETLIST(netlist, mi, net) {
if (!net || !net->IsUserDeclared()) continue ;
bus = net->Bus() ;
if (bus && !done_buses.Insert(bus)) continue ;
net_or_bus = (bus) ? (DesignObj*)bus : (DesignObj*)net ;
id_name = (const char *)net_or_bus_2_id.GetValue(net_or_bus) ;
if (!id_name) {
net_or_bus->Error("'%s' does not have an associated id", net_or_bus->Name()) ;
continue ;
}
type_range = (const TypeRange *)type_ranges->GetValue(id_name) ;
if (!type_range) {
net_or_bus->Error("'%s' created from '%s' does not have an associated type-range info", net_or_bus->Name(), id_name) ;
continue ;
}
tr_str = type_range->Dump() ;
net_or_bus->Info("'%s' is created from '%s' of type '%s'", net_or_bus->Name(), id_name, tr_str) ;
Strings::free(tr_str) ;
}
#endif

return 0 ;
}
</nowiki>

pkg.sv:
<nowiki>
package pkg;
typedef struct packed {
reg [1:0] AA;
reg [1:0] BB;
} t1;
typedef struct packed {
reg [5:0] CC;
reg DD;
} t2;
typedef struct packed {
t1 AW;
t2 BW;
} mst;
endpackage // pkg
</nowiki>

test.sv:
<nowiki>
`include "pkg.sv"
module top (
input clk, rst,
input [5:0] a_in,
input [5:0] b_in
);
wire pkg::mst a[3:0];
assign a[0].AW.AA = a_in[1:0];
assign a[0].AW.BB = a_in[4:2];
assign a[0].BW.CC = a_in | b_in;
assign a[0].BW.DD = 1;
endmodule
</nowiki>

Run:
<nowiki>
$ test-linux
-- Analyzing Verilog file 'test.sv' (VERI-1482)
test.sv(1): INFO: analyzing included file 'pkg.sv' (VERI-1328)
test.sv(1): INFO: back to file 'test.sv' (VERI-2320)
test.sv(2): INFO: compiling module 'top' (VERI-1018)
test.sv(9): WARNING: expression size 3 truncated to fit in target size 2 (VERI-1209)
test.sv(2): INFO: 'a[0].AW' is created from type ' {struct packed <t1> {AA : [1:0] reg, BB : [1:0] reg}}'
$
</nowiki>

Main Page

2024-04-23T18:30:13Z

Hoa:

'''General'''
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
* [[Source code customization & Stable release services | Source code customization & Stable release services]]
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]
* [[Release version | How do I tell the version of a Verific software release? ]]
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
* [[LineFile data from input files | LineFile data from input files]]
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]
* [[Preserving user nets - preventing nets from being optimized away | Preserving user nets - preventing nets from being optimized away]]
* [[Python pretty-printer for gdb | Python pretty-printer for gdb]]

'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Port Expressions]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[Modules with '_1' '_2' suffix in their names | Verilog: After static elaboration, there are modules with "_1", "_2", ..., suffix in their names. Why?]]
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
* [[Notes on analysis | SystemVerilog: Notes on analysis]]
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units/interfaces with "_default" suffix in their names. Why? And what are they?]]
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
'''Netlist Database'''
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]
* [[System attributes | Netlist Database: System attributes]]

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''Scripting languages: TCL, Perl, Python'''
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]

'''Code examples'''
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]
* [[How to use MessageCallBackHandler Class | Util/C++: How to use MessageCallBackHandler Class]]
* [[How to use RegisterPragmaRefCallBack() | Util/C++: How to use RegisterPragmaRefCallBack()]]
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
* [[Extract clock enable | Database/C++: Extract clock enable]]
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
* [[Post processing port resolution of black boxes | Database/C++: Post processing port resolution of black boxes]]
* [[Finding hierarchical paths of a Netlist | Database/C++: Finding hierarchical paths of a Netlist]]
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]
* [[Type Range example | Database/Verilog/C++: Type Range example (simple)]]
* [[Type Range example with multi-dimensional arrays| Database/Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
* [[Using TypeRange table to retrieve the originating type-range for an id | Database/Verilog/C++: Using TypeRange table to retrieve the originating type-range for an id]]
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
* [[How to ignore certain modules while analyzing input RTL files | Verilog/C++: How to ignore certain modules while analyzing input RTL files]]
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
* [[In Verilog parsetree adding names to unnamed instances | Verilog/C++: In Verilog parsetree adding names to unnamed instances]]
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]
* [[Parse select modules only and ignore the rest | Verilog/C++: Parse select modules only and ignore the rest]]
* [[Create DOT diagram of parse tree | Verilog/C++: Create DOT diagram of a parse tree]]
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
* [[Evaluate 'for-generate' loop | Verilog/C++: Evaluate 'for-generate' loop]]
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
* [[Simple examples of VHDL visitor pattern | VHDL/C++: Simple examples of VHDL visitor pattern]]
* [[Traverse instances in parsetree | VHDL/C++: Traverse instances in parsetree]]
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]

In Verilog parsetree adding names to unnamed instances

2024-04-04T02:52:10Z

Hoa:

In Verilog, each module instantiation should have a name. But name is optional for UDP instantiation and Verilog primitive instantiation.

Verific issues a warning for unnamed module instantiation:

test.v(16): WARNING: instantiating unknown module 'foo' (VERI-1063)

The warning is issued during elaboration because in analysis, it is not known whether the instantiated construct is a module, a UDP, or a primitive.

This application adds a name to each unnamed module instantiation. Note that this application has facilities to keep track of the scope of the instantiation statement.

<nowiki>
#include <iostream>
#include "veri_file.h"
#include "VeriModule.h"
#include "VeriId.h"
#include "VeriExpression.h"
#include "VeriScope.h"
#include "Map.h"

using namespace std ;
#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

class MyVisitor : public VeriVisitor
{
public:
MyVisitor() : VeriVisitor(), _scope_stack(0) { }
virtual ~MyVisitor() { }

virtual void VERI_VISIT(VeriModuleInstantiation, node)
{
VeriScope *current_scope = GetCurrentScope() ;
Array *inst_ids ;
inst_ids = node.GetIds() ;
unsigned i ;
VeriInstId *inst_id ;
FOREACH_ARRAY_ITEM(inst_ids, i, inst_id) {
if (!inst_id) continue ;
const char *inst_name = inst_id->InstName() ;
char *allocated_inst_name = 0 ;
if (!inst_name && current_scope) {
VeriIdDef *scope_id = current_scope->GetOwner();
unsigned uniq_no = 0 ;
char *suffix = Strings::itoa((int)(uniq_no)) ;
char *prefix = (scope_id && scope_id->Name()) ? Strings::save("unnamed_inst_", scope_id->Name(), "_") : Strings::save("unnamed_inst_") ;
allocated_inst_name = Strings::save(prefix, suffix) ;
while (current_scope->FindLocal(allocated_inst_name) && (uniq_no < 1000)) {
Strings::free(allocated_inst_name) ;
Strings::free(suffix) ;
suffix = Strings::itoa((int)(uniq_no)) ;
allocated_inst_name = Strings::save(prefix, suffix) ;
uniq_no++ ;
}
current_scope->Undeclare(inst_id) ;
inst_id->SetName(allocated_inst_name) ;
current_scope->Declare(inst_id, 0, 0) ;
Strings::free(allocated_inst_name) ;
Strings::free(suffix) ;
Strings::free(prefix) ;
}
}
}

virtual void PreAction(VeriTreeNode &node)
{
// Push the scope of the current node into the stack:
const VeriModuleItem *item = dynamic_cast<VeriModuleItem *>(&node) ;
VeriScope *scope = (item) ? item->GetScope() : 0 ;
if (scope) _scope_stack.InsertLast(scope) ;
}

virtual void PostAction(VeriTreeNode &node)
{
// Pop the scope of the current node from the stack:
const VeriModuleItem *item = dynamic_cast<VeriModuleItem *>(&node) ;
VeriScope *scope = (item) ? item->GetScope() : 0 ;
if (scope) (void) _scope_stack.RemoveLast() ;
}

// Get the current/active scope for the parse tree we are visiting:
VeriScope *GetCurrentScope() const { return (_scope_stack.Size()) ? (VeriScope *)_scope_stack.GetLast() : 0 ; }

private:
Array _scope_stack ;
} ;

int main() {
if (!veri_file::Analyze("test.v", veri_file::SYSTEM_VERILOG)) return 1 ;
veri_file::PrettyPrint ("pp_out_before.v.golden.new", 0) ;
MyVisitor mv ;
MapIter mi ;
VeriModule *mod ;
FOREACH_VERILOG_MODULE(mi, mod) {
if (!mod) continue ;
mod->Accept(mv) ;
}
veri_file::PrettyPrint ("pp_out_after.v.golden.new", 0) ;
return 0 ;
}
</nowiki>

SystemVerilog "std" package

2024-02-29T00:05:06Z

Hoa:

'''Q: Support for SystemVerilog semaphore/process/mailbox.'''

When I analyzed my SystemVerilog file, Verific issued error message:

test.sv(4): ERROR: process is not declared (VERI-1128)

(similarly for "mailbox" and "semaphore").

Does Verific support those SystemVerilog constructs?

According to SystemVerilog LRM, "process", "mailbox", and "semaphore" are classes defined in package "std" in library "std". Before analyzing the file using these classes, you need to load the "std" package. You can use either of the following ways:

* Analyze the package before loading the design:
veri_file::Analyze("verilog_packages/std.sv", veri_file::SYSTEM_VERILOG, "std") ;
* or load the library on demand using binary/restore method:
veri_file::AddLibraryPath("std", "verilog_packages/sdbs/std") ;
The binary dump file "std.sdb" should be in "verilog_packages/sdbs/std" directory.

* tcl commands:

setveriloglibrarypath -default ../sdbs

or

setveriloglibrarypath -associate std=../sdbs/std

Instance - Module binding order

2024-01-26T00:41:36Z

Hoa:

'''Q: Verilog has many ways to find modules not in the file being directly read: -L, -v, -y, .... There may be more than one module of the same name. What is the order of binding?'''

The order of searching for modules is:

# While parsing:
## `uselib
## -L
## (present working library)
## -y/-v (their order in an f-file is considered)
# While elaborating:
## configurations
## already resolved module from analysis, ie, order of parsing (above)

Constant expression replacement

2023-11-17T16:51:38Z

Hoa:

'''Q: Does Verific replace constant expressions with their respective values?'''

I have in my Verilog code:
parameter size = 8;
reg [size-1:0] foo;
I expect the range of "foo" to be [7:0]. How do I get the range [7:0]?

If run-time flag "veri_replace_const_exprs" is set, during static elaboration, Verific will replace the following constant expressions with their respective values:
# Bounds of packed and unpacked ranges in all data declarations.
# Default values of all declared objects if those are constant.
# Delay values.
# Reject and error limits of VeriPathPulse values.
# Indexed expressions only if the indexed expression is a bit-select on the LHS of a continuous assignment or output/inout port of module or gate instantiation.

Above specific replacements are not done on un-elaborated modules because the parameter values they depend on might be changed later by other applications.

In C++:
RuntimeFlags::SetVar("veri_replace_const_exprs", 1) ;

In Tcl:
set_runtime_flag "veri_replace_const_exprs" 1

Notes on analysis

2023-11-01T04:53:25Z

Hoa:

First, please read this article: [[Defined macros become undefined - MFCU vs SFCU]].

'''Q: Can I use 'veri_file::Analyze()' to read SystemVerilog input files one by one, all of them belonging to one compilation unit?'''

Yes. But if you have multiple files, it’s better to use 'veri_file::AnalyzeMultipleFiles()'.

'veri_file::AnalyzeMultipleFiles()', besides analyzing each file, also:

* opens and ends the compilation unit
* processes –v and –y options
* removes include directories
* processes root module
* undefines user-defined macros, including command-line macros
* resets compile directives (e.g. `default_nettype, `timescale)

If you use 'veri_file::Analyze()' to analyze each file one by one, after all the calls to 'veri_file::Analyze(), depending on the application, you may want to run veri_file::RemoveAllIncludeDirs() and veri_file::EndCompilationUnit().

If the application calls any elaboration API (e.g. veri_file::Elaborate()), there is no need to call veri_file::RemoveAllIncludeDirs() and veri_file::EndCompilationUnit() because the elaboration API will call those APIs before actual elaboration.

The TCL command 'analyze' uses the API 'veri_file::AnalyzeMultipleFiles()'. In other words, it assumes a complete compilation unit for each execution.

Notes on analysis

2023-11-01T04:52:10Z

Hoa:

First, please read this article: [[Defined macros become undefined - MFCU vs SFCU]].

'''Q: Can I use 'veri_file::Analyze()' to read SystemVerilog input files one by one, all of them belonging to one compilation unit?'''

Yes. But if you have multiple files, it’s better to use 'veri_file::AnalyzeMultipleFiles()'.

'veri_file::AnalyzeMultipleFiles()', besides analyzing each file, also:

* opens and ends the compilation unit
* processes –v and –y options
* removes include directories
* processes root module
* undefines user-defined macros, including command-line macros
* resets compile directives (e.g. `default_nettype, `timescale)

If you use 'veri_file::Analyze()' to analyze each file one by one, after all the calls to 'veri_file::Analyze(), depending on the application, you may also want to run veri_file::RemoveAllIncludeDirs() and veri_file::EndCompilationUnit().

If the application calls any elaboration API (e.g. veri_file::Elaborate()), there is no need to call veri_file::RemoveAllIncludeDirs() and veri_file::EndCompilationUnit() because the elaboration API will call those APIs before actual elaboration.

The TCL command 'analyze' uses the API 'veri_file::AnalyzeMultipleFiles()'. In other words, it assumes a complete compilation unit for each execution.

Notes on analysis

2023-10-20T19:13:07Z

Hoa:

First, please read this article: [[Defined macros become undefined - MFCU vs SFCU]].

'''Q: Can I use 'veri_file::Analyze()' to read SystemVerilog input files one by one, all of them belonging to one compilation unit?'''

Yes. But if you have multiple files, it’s better to use 'veri_file::AnalyzeMultipleFiles()'.

'veri_file::AnalyzeMultipleFiles()', besides analyzing each file, also:

* opens and ends the compilation unit
* processes –v and –y options
* removes include directories
* processes root module
* undefines user-defined macros, including command-line macros
* resets compile directives (e.g. `default_nettype, `timescale)

If you use 'veri_file::Analyze()' to analyze each file one by one, after all the calls to 'veri_file::Analyze()', you’ll need to call 'veri_file::AnalyzeFull()' to complete the analysis before starting any other operation. Depending on the application, you may also want to run veri_file::RemoveAllIncludeDirs() and veri_file::EndCompilationUnit().

The TCL command 'analyze' uses the API 'veri_file::AnalyzeMultipleFiles()'. In other words, it assumes a complete compilation unit for each execution.

Notes on analysis

2023-10-20T16:32:52Z

Hoa:

First, please read this article: [[Defined macros become undefined - MFCU vs SFCU]].

'''Q: Can I use 'veri_file::Analyze()' to read SystemVerilog input files one by one, all of them belonging to one compilation unit?'''

Yes. But if you have multiple files, it’s better to use 'veri_file::AnalyzeMultipleFiles()'.

'veri_file::AnalyzeMultipleFiles()', besides analyzing each file, also:

* opens and ends the compilation unit
* processes –v and –y options
* removes include directories
* processes root module
* undefines user-defined macros, including command-line macros
* resets compile directives (e.g. `default_nettype, `timescale)

If you use 'veri_file::Analyze()' to analyze each file one by one, after all the calls to 'veri_file::Analyze()'. you’ll need to call 'veri_file::AnalyzeFull()' to complete the analysis before starting any other operation. Depending on the application, you may also want to run veri_file::RemoveAllIncludeDirs() and veri_file::EndCompilationUnit().

The TCL command 'analyze' uses the API 'veri_file::AnalyzeMultipleFiles()'. In other words, it assumes a complete compilation unit for each execution.

How to get best support from Verific

2023-10-12T00:25:36Z

Hoa:

We here at Verific strive to provide you with the best customer service.

But we need help from you. Please:

* Identify your company and your group/business unit. Many of our customers have multiple Verific licenses, each with a different product configuration. On our file system, each of the licensees has a dedicated code branch, and code cross-contamination is an absolute no-no. Identifying your company and your business unit will help us to use the appropriate code branch. - The API "Message::CustomerName()" returns your company name. - Another way is to tell us the name/email address of the person in your company that frequently deal with Verific. - Please use an email address associated with your company; do not use an email address from a generic email service provider (e.g. JohnSmith@gmail.com).

* Tell us what Verific release you are using: - The API "Message::ReleaseString()" returns something like "Jul17_SW_Release." - Or you can just search for "ReleaseString" in util/Message.cpp. - If you are evaluating Verific software, tell us the exact name of the zip file containing the library package. - Or you can run tclmain application with "-v" option:
$ tclmain-linux-O -v
-- (c) Copyright 1999 - 2020 Verific Design Automation Inc. All rights reserved
-- Verific release: Mar20_SW_Release, to: Company, release date: Tue Apr 28 09:13:38 2020
Hello, init.tcl has been executed
%

* Be clear and precise about the issue. Send us the log file if available; if not, a description of the symptom and the exact error/warning messages will help tremendously. If it is at all possible, send us a testcase that we can use to re-create the symptom. If there is a problem, that testcase can be used to verify that the problem has been fixed. By the way, the testcase you provide will be added to the regression testsuite for your code branch. It will not be shared with anyone/organization outside of Verific. The testcase should include Verilog/VHDL files, a TCL/Perl/Python script, or a C++ application exhibiting the symptom (current output), and the expected output. ''In sending the testcase, '''do not send screenshots'''. Rather, please send text files, or put them in the body of the email message so that we can save the files or cut and paste the text to create the testcase on our file system. If you send screenshots, we will have to type the files in, which takes time and is error-prone.''

* The C++ application or the TCL/Perl/Python modules used to recreate the symptoms should be built with '''''the C++ source code as shipped from Verific'''''. Otherwise please let us know any modifications, including compile-time flags and run-time flags, that have been done on the source code.

* If you send a log file, please do not suppress any messages from Verific; they are essential in debugging. To clear message suppressions, please use Message::ClearAllMessageTypes().

* If any of the older releases of Verific has a different behavior, and you are reporting a regression, tell us what release(s) of Verific you are comparing to. This will save us some time checking the old releases.

* If there are other EDA tools that run "correctly," provide the names and the versions of the tools and their "correct" output. Do not just say, "Other tools accept the design" (then we will need to ask you the names of the tools).
* Send email to support@verific.com. If you want to send email to an individual Verific engineer, add support@verific.com to the cc list. We have an internal procedure to prevent tech support requests from falling through the cracks. This procedure works only for email messages sent to, or cc'ed, support@verific.com. ''If your questions are related to Verific's Invio product, please send email to invio@verific.com.''
* Initiate a new email thread (new subject line) for a new issue. Do not 'reply' to an old email thread to report a new issue. Our internal procedure depends on the subject line of the email message. Reusing an old subject line may result in a delay in response time.

* If the problem is resolved at your end, inform us so we can close the issue.

Thank you very much.