Verific Design Automation FAQ - User contributions [en]

Main Page

2017-01-12T01:53:56Z

Michiel: Undo revision 270 by Michiel (talk)

'''General'''
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior?]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? ]]

'''VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[Prettyprint to a string | Verilog: How to prettyprint a parsetree node to a string.]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[SystemVerilog "std" package | Verilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''TCL, Perl, Python, Java'''
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]

Main Page

2017-01-12T01:51:36Z

Michiel: Undo revision 273 by Michiel (talk)

'''General'''
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior?]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? ]]

'''VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[Prettyprint to a string | Verilog: How to prettyprint a parsetree node to a string.]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[SystemVerilog "std" package | Verilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''TCL, Perl, Python, Java'''
* [[What languages can I use with the Verific software? | What programming languages can I use with the Verific software?]]

Main Page

2017-01-12T01:50:45Z

Michiel: Undo revision 272 by Michiel (talk)

'''General'''
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior?]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? ]]

'''VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[Prettyprint to a string | Verilog: How to prettyprint a parsetree node to a string.]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[SystemVerilog "std" package | Verilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''TCL, Perl, Python, Java'''
* [[What languages can I use with the Verific software? | What programming languages can I use with Verific software?]]

Main Page

2017-01-12T01:50:02Z

Michiel: Undo revision 271 by Michiel (talk)

'''General'''
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior?]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? ]]

'''VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[Prettyprint to a string | Verilog: How to prettyprint a parsetree node to a string.]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[SystemVerilog "std" package | Verilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''TCL, Perl, Python, Java'''
* [[What languages can I use with the Verific software? | What programming languages can I use with the Verific software?]]

Main Page

2017-01-12T01:49:03Z

Michiel:

'''General'''
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior?]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? ]]

'''VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[Prettyprint to a string | Verilog: How to prettyprint a parsetree node to a string.]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[SystemVerilog "std" package | Verilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''TCL, Perl, Python, Java'''
* [[What languages can I use with the Verific software? | What programming languages can I use with Verific software?]]

Main Page

2017-01-12T01:48:32Z

Michiel:

'''General'''
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior?]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? ]]

'''VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[Prettyprint to a string | Verilog: How to prettyprint a parsetree node to a string.]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[SystemVerilog "std" package | Verilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''TCL, Perl, Python, Java'''
* [[What languages can I use with the Verific software? | What programming languages can I use with the Verific software?]]

Main Page

2017-01-12T01:47:29Z

Michiel: