This example converts module with struct ports into flat ports.

<nowiki>
from invio import *

set_preference("invio_insert_ports_with_newline", 1)
add_sv_file("test.sv")
analyze()
elaborate("top")

# Convert instance of the module with struct ports into flat ports
mod = get_modules("child").first
for i in get_instances(mod):
for p in i.portmaps:
pin = p.pin
if pin and pin.data_type.is_named_user_type:
print(f'... Replacing portmap: {p.full_name}')
portmap = ''
for m in pin.data_type.members:
portmap = portmap + f'.{pin.base_name}_{m.base_name} ({p.connected.first.base_name}.{m.base_name})' + ', \n'
rt = create_raw_text_object(ref=p)
replace_orig_text_of_object(rt, portmap[:len(portmap)-3]) # trim off the last ', '
# You will need to write out the modification and relaod to see the effect of text replacement in the parse tree.

# Replace the assignment with raw text
a = get_assigns(mod).first
new_assign = """assign out_bus_clk = in_bus_clk;
assign out_bus_rst = in_bus_rst;
assign out_bus_addr = in_bus_addr;
assign out_bus_data = in_bus_data;
"""
print(f'... Replacing assignment: {a.full_name}')
replace_orig_text_of_object(a, new_assign)

# flatten the ports
new_ports = []
for p in get_ports(mod):
p_type = p.data_type
if (p_type.is_named_user_type):
print(f'... Replacing port: {p.full_name}')
# Create new ports for each memeber and add them to the module
for m in p_type.members:
portname = f"{p.base_name}_{m.base_name}"
dims = []
for d in m.dimensions:
dims.append( (d.left_index, d.right_index) )
# Create a port with the same attributes as struct memebers
new_port = create_port(portname, p.direction, datatype_name=m.data_type_name, dimensions=dims);
new_ports.append(new_port)

# Delete the old struct port
delete_object(p)

# Insert them into top module after removing the old ports
for p in new_ports:
insert_into(p, mod)

# Write out the modifications
write_modified_file("test.sv", "test_mod.sv")
</nowiki>

"test.sv"
<nowiki>
typedef struct {
logic clk;
logic rst;
logic [1:0] addr;
int data;
} bus_t;

module child (
input bus_t in_bus,
output bus_t out_bus
);

assign out_bus = in_bus;
endmodule // child

module top #(WIDTH = 4)(
input bus_t top_in_bus,
input [0:WIDTH-1] a,
output [0:WIDTH-1] d,
output bus_t top_out_bus
) ;

child u_child (
.in_bus (top_in_bus),
.out_bus (top_out_bus)
);

endmodule
</nowiki>

Testcase after modification, "test_mod.sv":
<nowiki>
typedef struct {
logic clk;
logic rst;
logic [1:0] addr;
int data;
} bus_t;

module child (
input logic in_bus_clk,
input logic in_bus_rst,
input logic [1:0] in_bus_addr,
input int in_bus_data,
output logic out_bus_clk,
output logic out_bus_rst,
output logic [1:0] out_bus_addr,
output int out_bus_data
);

assign out_bus_clk = in_bus_clk;
assign out_bus_rst = in_bus_rst;
assign out_bus_addr = in_bus_addr;
assign out_bus_data = in_bus_data;

endmodule // child

module top #(WIDTH = 4)(
input bus_t top_in_bus,
input [0:WIDTH-1] a,
output [0:WIDTH-1] d,
output bus_t top_out_bus
) ;

child u_child (
.in_bus_clk (top_in_bus.clk),
.in_bus_rst (top_in_bus.rst),
.in_bus_addr (top_in_bus.addr),
.in_bus_data (top_in_bus.data),
.out_bus_clk (top_out_bus.clk),
.out_bus_rst (top_out_bus.rst),
.out_bus_addr (top_out_bus.addr),
.out_bus_data (top_out_bus.data)
);

endmodule
</nowiki>

2023-11-04T00:37:10Z

Mohammad:

'''Q: How do I get type and initial value of parameters?'''

Example C++ code:
<nowiki>
#include "veri_file.h"
#include "VeriId.h"
#include "VeriExpression.h"
#include "Netlist.h"
#include "VeriModule.h"
#include <iostream>

using namespace Verific ;

int main()
{
const char *file_name = "test.v";
if (!veri_file::Analyze(file_name, veri_file::SYSTEM_VERILOG)) {
std::cout << "unable to analyze file " << file_name << " and mode SYSTEM_VERILOG\n";
return 1 ;
}
const char *top_module_name = "top";

VeriModule *top = veri_file::GetModule(top_module_name);
if (!top) {
std::cout <<"module " << top_module_name << " not found\n";
return 1;
}

Array *param_array = top->GetParameters() ;
if (!param_array) {
std::cout << "*** no parameters found ***\n";
return 1;
}

unsigned i ;
VeriIdDef *param_id ;
FOREACH_ARRAY_ITEM(param_array, i, param_id) {
if (!param_id) continue;

std::cout << "*** param name: " << param_id->Name() << " ***\n";
VeriDataType *type = param_id->GetDataType();
if (type) {
std::cout << "*** type: " << type->GetPrettyPrintedString() << "***\n";
} else {
std::cout << "*** type not declared ***\n";
}

VeriExpression *init_value = param_id->GetInitialValue();

if (init_value) {
std::cout << "*** initial value: " << init_value->GetPrettyPrintedString() << " ***\n";
}
}
return 0 ;
}
</nowiki>

Example Perl code:
<nowiki>
#!/usr/bin/perl

push(@INC,"../../../perlmain/install");
require "Verific.pm";

my $filename = "test.v";
my $mode = 4; # SystemVerilog - Verilog 2K: my $mode = 1;
if (!Verific::veri_file::Analyze($filename, $mode)) { die "unable to analyze file $filename and mode $mode\n"; }

$top_module_name = "top";

# $top is VeriModule *
my $top = Verific::veri_file::GetModule($top_module_name);
if (!defined($top)) { die "module $top_mod not found\n"; }

my $param_array = $top->GetParameters();
if (!defined($param_array)) { print "*** no parameters found ***\n"; exit; }

# now let's get an Array iterator instead of using the FOREACH_ARRAY_ITEM macro
my $param_array_iter = $param_array->Iterator("VeriIdDef");

for (my $param_id = $param_array_iter->First();
$param_array_iter < $param_array_iter->Size();
$param_id = $param_array_iter->Next()) {

# null check param_id..
if (!defined($param_id)) { next; }

# print param name
printf "* param name: %s ***\n", $param_id->Name();

# print param type
# $type, if specified, is VeriDataType *
my $type = $param_id->GetDataType();
if (defined($type)) {
my $to_string = "";
$type->PrettyPrint(\$to_string, 0);
print "*** type: $to_string ***\n";
} else {
print "*** type not declared ***\n";
}

# $init_value is VeriExpression *
my $init_value = $param_id->GetInitialValue();

if (defined($init_value)) {
my $to_string = "";
$init_value->PrettyPrint(\$to_string, 0);
print "*** initial value: $to_string ***\n";
}
}

exit;
</nowiki>

For example, this RTL code:
<nowiki>
module top (a0, a1, b0, b1, c0, c1);
parameter int DUMMY0 = 8;
parameter logic DUMMY1 = 16;
parameter WIDTH = 4;
input [WIDTH-1 : 0] a0, b0, a1, b1;
output [WIDTH-1 : 0] c0, c1;

endmodule
</nowiki>

Will have the following output:
<nowiki>
-- Analyzing Verilog file 'test.v' (VERI-1482)
*** param name: DUMMY0 ***
*** type: int ***
*** initial value: 8 ***
*** param name: DUMMY1 ***
*** type: logic ***
*** initial value: 16 ***
*** param name: WIDTH ***
*** type not declared ***
*** initial value: 4 ***
</nowiki>