Verific Design Automation FAQ - User contributions [en]

How to save computer resources

2025-10-10T17:40:54Z

Vince:

There are compile flags & runtime flags that may help to reduce memory consumption and/or runtime.
Below are some common ones.

- Compile flag "VERIFIC_MEMORY_MANAGER" in util/VerificSystem.h
Highly recommended.

Enables the new, zero-overhead, Verific memory manager. Typically reduces memory usage of the Verific software by an additional 20% over the default system memory manager.
- Compile flag "DB_USE_PORT_ORDERED_PORTREF" in database/DBCompileFlags.h
Highly recommended.

Organizes the PortRef structures in an ordered array rather than a hash table. This saves a significant amount of memory since PortRefs are no longer individually allocated,
and the overhead of a hash table is also saved.

- Compile flag "VERILOG_QUICK_PARSE_V_FILES" in verilog/VeriCompileFlags.h
Normally a -v file may contain multiple module definitions. The Verilog parser is supposed to pick only the required modules from that file.

However, the file may not contain any of the required modules; instead it is a large file containing many other modules of no interest. In such a case, analyzing and creating a parse tree for the full file will consume much time and memory.

To prevent this, we provide this compile flag to quickly parse the file and see if it is actually required or not, without creating the parse tree. If it is not required we will ignore the file, otherwise we will fully parse it and pick the required modules.

- Compile flag "VERIFIC_LINEFILE_INCLUDES_COLUMNS" in util/VerificSystem.h
If you don't need the starting and ending locations including column info, turn this flag off.

For more details, see [[LineFile data from input files|LineFile data from input files]]
- Runtime flag "veri_improve_include_dir_processing_runtime_for_network_file_system"
Adds directory caching for include directories with simple files (files without a directory specification).

We read the contents of the directory on first encountering it while checking for an include file. Subsequent searches will find the file in the cache instead of the actual disk.

The cache is automatically cleared at the end of the veri_file::Analyze() or veri_file::AnalyzeMultipleFiles() calls. Note that we cannot keep it alive after the two analyze calls since there could possibly be a chdir() call which would make the cache invalid.
- Runtime flag "veri_share_nodes_in_static_elab"

Reduces memory and runtime for large designs. This flag will ensure that only one node will be created in static elaboration for each unique signature of a module, regardless of whether it is a top module or instantiated. The number of nodes that can be reduced depends on the nature of the design. For more details on this flag check [https://www.verific.com/faq/index.php?title=Parse_tree_node_sharing_in_Static_Elaboration here]

- Runtime flag "veri_ignore_always_constructs"

This enables a "light-weighed" RTL elaboration. "always" constructs in the input RTL Verilog file will be skipped over.

The output netlist is not complete, but is useful if you are interested only in module interfaces and instantiations.

Note that this flag is active only during RTL elaboration, not analysis. The input files still need to be Verilog-legal.

- Runtime flag "edif_delete_view_contents_after_processing"

For EDIF input.

Highly recommended.

Deletes the "contents" of a "view" after processing it, i.e., after creating the netlist. We still keep the "interface", i.e., ports alive so that the view can be instantiated.

- Runtime flag "edif_link_case_insensitive"

For EDIF input.

EDIF LRM does not define how existing external cells (maybe parsed from another language) should be linked to EDIF cells. We implemented case-insensitive (linear) search for these, which causes an N^2 complexity problem that slows down the reader for very large designs. Switching to case-sensitive search significantly speeds up the process, but there may be incidental cases where the EDIF reader does not link to an existing cell parsed from a different file.

- Runtime flag "edif_keep_existing_view"

For EDIF input.

When stitching designs from multiple files, a view may be defined in more than one file. By default ("edif_keep_existing_view" disabled), the view being currently read survives, replacing the existing view. This may slow down the process because the existing view and all of its references in the Netlist Database has to be updated.

Enabling "edif_keep_existing_view" allows the reader to ignore the (duplicated) view being currently read. All references to the view being ignored will be updated to point to the existing view in the Netlist Database. Only the references to the current view (in the current read operation) need to be updated to point to the existing view.

How to save computer resources

2025-10-10T17:36:45Z

Vince:

There are compile flags & runtime flags that may help to reduce memory consumption and/or runtime.
Below are some common ones.

- Compile flag "VERIFIC_MEMORY_MANAGER" in util/VerificSystem.h
Highly recommended.

Enables the new, zero-overhead, Verific memory manager. Typically reduces memory usage of the Verific software by an additional 20% over the default system memory manager.
- Compile flag "DB_USE_PORT_ORDERED_PORTREF" in database/DBCompileFlags.h
Highly recommended.

Organizes the PortRef structures in an ordered array rather than a hash table. This saves a significant amount of memory since PortRefs are no longer individually allocated,
and the overhead of a hash table is also saved.

- Compile flag "VERILOG_QUICK_PARSE_V_FILES" in verilog/VeriCompileFlags.h
Normally a -v file may contain multiple module definitions. The Verilog parser is supposed to pick only the required modules from that file.

However, the file may not contain any of the required modules; instead it is a large file containing many other modules of no interest. In such a case, analyzing and creating a parse tree for the full file will consume much time and memory.

To prevent this, we provide this compile flag to quickly parse the file and see if it is actually required or not, without creating the parse tree. If it is not required we will ignore the file, otherwise we will fully parse it and pick the required modules.

- Compile flag "VERIFIC_LINEFILE_INCLUDES_COLUMNS" in util/VerificSystem.h
If you don't need the starting and ending locations including column info, turn this flag off.

For more details, see [[LineFile data from input files|LineFile data from input files]]
- Runtime flag "veri_improve_include_dir_processing_runtime_for_network_file_system"
Adds directory caching for include directories with simple files (files without a directory specification).

We read the contents of the directory on first encountering it while checking for an include file. Subsequent searches will find the file in the cache instead of the actual disk.

The cache is automatically cleared at the end of the veri_file::Analyze() or veri_file::AnalyzeMultipleFiles() calls. Note that we cannot keep it alive after the two analyze calls since there could possibly be a chdir() call which would make the cache invalid.
- Runtime flag "veri_share_nodes_in_static_elab"

Reduces memory and runtime for large designs. This flag will ensure that only one node will be created in static elaboration for each unique signature of a module, regardless of whether it is a top module or instantiated. The number of nodes that can be reduced depends on the nature of the design. For more details on this flag check [https://www.verific.com/faq/index.php?title=Source_code_customization_%26_Stable_release_services here]

- Runtime flag "veri_ignore_always_constructs"

This enables a "light-weighed" RTL elaboration. "always" constructs in the input RTL Verilog file will be skipped over.

The output netlist is not complete, but is useful if you are interested only in module interfaces and instantiations.

Note that this flag is active only during RTL elaboration, not analysis. The input files still need to be Verilog-legal.

- Runtime flag "edif_delete_view_contents_after_processing"

For EDIF input.

Highly recommended.

Deletes the "contents" of a "view" after processing it, i.e., after creating the netlist. We still keep the "interface", i.e., ports alive so that the view can be instantiated.

- Runtime flag "edif_link_case_insensitive"

For EDIF input.

EDIF LRM does not define how existing external cells (maybe parsed from another language) should be linked to EDIF cells. We implemented case-insensitive (linear) search for these, which causes an N^2 complexity problem that slows down the reader for very large designs. Switching to case-sensitive search significantly speeds up the process, but there may be incidental cases where the EDIF reader does not link to an existing cell parsed from a different file.

- Runtime flag "edif_keep_existing_view"

For EDIF input.

When stitching designs from multiple files, a view may be defined in more than one file. By default ("edif_keep_existing_view" disabled), the view being currently read survives, replacing the existing view. This may slow down the process because the existing view and all of its references in the Netlist Database has to be updated.

Enabling "edif_keep_existing_view" allows the reader to ignore the (duplicated) view being currently read. All references to the view being ignored will be updated to point to the existing view in the Netlist Database. Only the references to the current view (in the current read operation) need to be updated to point to the existing view.

Parse tree node sharing in Static Elaboration

2025-10-10T17:31:18Z

Vince:

The static elaboration process internally creates a fully instantiated hierarchy tree where each node represents a top level or instantiations of design units.

Consider the following design :

<nowiki>
module top () ;
parameter LOOP_LIMIT = 200 ;
genvar i ;
for ( i=0; i<LOOP_LIMIT; i++) begin : in_top
mid m() ;
end
endmodule

module mid () ;
genvar i ;
for ( i=0; i<100; i++) begin : in_mid
bot #(i/10) b() ;
end
endmodule

module bot () ;
parameter P = 0 ;
reg [P:0] w1 ;
endmodule
</nowiki>

By default static elaboration will create a hierarchy tree with 20201 nodes (1 for module 'top', 200 for 'mid', and 20000 for 'bot') for this design.

Note that if the runtime flag 'veri_alternative_generate_elab' is set, additional nodes will be created for each generate block (200 block nodes for block 'in_top' and 20000 for 'in_mid') resulting in a total of 40401 nodes created.

Static elaboration, being an iterative process, traverses this hierarchy tree multiple times to resolve hierarchical names, defparams, and bind statements. It evaluates parameters and elaborates generate constructs. This may lead to long runtimes for big designs with many modules and instantiations. Moreover a large amount of memory may be required to create this many nodes.

The runtime flag "veri_share_nodes_in_static_elab" was introduced to reduce runtime and memory for large designs. It will ensure that only one node will be created in static elaboration for each unique signature of a module (top or instantiated). So for the above design, elaboration will use only 1 node for module 'mid' as it has no parameter overwrite. However, module 'bot' will have multiple signatures like 'bot(P=1)', 'bot(P=2)' etc and so multiple nodes will be created for module 'bot'. If a design contains hierarchical names, more nodes can be created to resolve such names.

The number of nodes that can be reduced largely depends on the nature of the design, which in turn reflects on the runtime and memory improvements.

Limitation: For VHDL or mixed language designs, nodes are created for VHDL instances and top levels as well. However, VHDL nodes are currently not shared under this runtime flag. It applies only to the Verilog/SystemVerilog nodes.

Parse tree node sharing in Static Elaboration

2025-10-10T17:29:12Z

Vince:

The static elaboration process internally creates a fully instantiated hierarchy tree where each node represents a top level or instantiations of design units.

Consider the following design :

<nowiki>
module top () ;
parameter LOOP_LIMIT = 200 ;
genvar i ;
for ( i=0; i<LOOP_LIMIT; i++) begin : in_top
mid m() ;
end
endmodule

module mid () ;
genvar i ;
for ( i=0; i<100; i++) begin : in_mid
bot #(i/10) b() ;
end
endmodule

module bot () ;
parameter P = 0 ;
reg [P:0] w1 ;
endmodule
</nowiki>

By default static elaboration will create a hierarchy tree with 20201 nodes (1 for module 'top', 200 for 'mid', and 20000 for 'bot') for this design.

Note that if the runtime flag 'veri_alternative_generate_elab' is set, additional nodes will be created for each generate block (200 block nodes for block 'in_top' and 20000 for 'in_mid') resulting in a total of 40401 nodes created.

Static elaboration, being an iterative process, traverses this hierarchy tree multiple times to resolve hierarchical names, defparams, and bind statements. It evaluates parameters and elaborates generate constructs. This may lead to long runtimes for big designs with many modules and instantiations. Moreover a large amount of memory may be required to create this many nodes.

The runtime flag "veri_share_nodes_in_static_elab" was introduced to reduce runtime and memory for large designs. It will ensure that only one node will be created in static elaboration for each unique signature of a module (top or instantiated). So for the above design, elaboration will use only 1 node for module 'mid' as it has no parameter overwrite. However, module 'bot' will have multiple signatures like 'bot(P=1)', 'bot(P=2)' etc and so multiple nodes will be created for module 'bot'. If a design contains hierarchical names, more nodes can be created to resolve such names.

The number of nodes that can be reduced largely depends on the nature of the design, which in turn reflects on the runtime and memory improvements.

Limitation: For VHDL or mixed language designs, nodes are created for VHDL instances and top levels. However, such VHDL nodes are not shared yet under this runtime flag. It applies only to the Verilog/SystemVerilog nodes.

Parse tree node sharing in Static Elaboration

2025-10-10T17:27:14Z

Vince: Created page with "The static elaboration process internally creates a fully instantiated hierarchy tree where each node represents a top level or instantiations of design units. Consider the..."

The static elaboration process internally creates a fully instantiated hierarchy tree where each node represents a top level or instantiations of design units.

Consider the following design :

module top () ;
parameter LOOP_LIMIT = 200 ;
genvar i ;
for ( i=0; i<LOOP_LIMIT; i++) begin : in_top
mid m() ;
end
endmodule

module mid () ;
genvar i ;
for ( i=0; i<100; i++) begin : in_mid
bot #(i/10) b() ;
end
endmodule

module bot () ;
parameter P = 0 ;
reg [P:0] w1 ;
endmodule

By default static elaboration will create a hierarchy tree with 20201 nodes (1 for module 'top', 200 for 'mid', and 20000 for 'bot') for this design.

Note that if the runtime flag 'veri_alternative_generate_elab' is set, additional nodes will be created for each generate block (200 block nodes for block 'in_top' and 20000 for 'in_mid') resulting in a total of 40401 nodes created.

Static elaboration, being an iterative process, traverses this hierarchy tree multiple times to resolve hierarchical names, defparams, and bind statements. It evaluates parameters and elaborates generate constructs. This may lead to long runtimes for big designs with many modules and instantiations. Moreover a large amount of memory may be required to create this many nodes.

The runtime flag "veri_share_nodes_in_static_elab" was introduced to reduce runtime and memory for large designs. It will ensure that only one node will be created in static elaboration for each unique signature of a module (top or instantiated). So for the above design, elaboration will use only 1 node for module 'mid' as it has no parameter overwrite. However, module 'bot' will have multiple signatures like 'bot(P=1)', 'bot(P=2)' etc and so multiple nodes will be created for module 'bot'. If a design contains hierarchical names, more nodes can be created to resolve such names.

The number of nodes that can be reduced largely depends on the nature of the design, which in turn reflects on the runtime and memory improvements.

Limitation: For VHDL or mixed language designs, nodes are created for VHDL instances and top levels. However, such VHDL nodes are not shared yet under this runtime flag. It applies only to the Verilog/SystemVerilog nodes.

Main Page

2025-10-10T17:10:57Z

Vince:

'''General'''
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
* [[Source code customization & Stable release services | Source code customization & Stable release services]]
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]
* [[Release version | How do I tell the version of a Verific software release? ]]
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
* [[LineFile data from input files | LineFile data from input files]]
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]
* [[Preserving user nets - preventing nets from being optimized away | Preserving user nets - preventing nets from being optimized away]]
* [[Python pretty-printer for gdb | Python pretty-printer for gdb]]
* [[Yosys-Verific Integration | Yosys-Verific integration]]
* [[How to enable long paths on Windows? | How to enable long paths on Windows?]]

'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Port Expressions]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[Modules with '_1' '_2' suffix in their names | Verilog: After static elaboration, there are modules with "_1", "_2", ..., suffix in their names. Why?]]
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
* [[Notes on analysis | SystemVerilog: Notes on analysis]]
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
* [[Parse tree node sharing in Static Elaboration | SystemVerilog: Parse tree node sharing in Static Elaboration.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units/interfaces with "_default" or "or "_1, _2" suffix in their names. What are they?]]
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
'''Netlist Database'''
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]
* [[System attributes | Netlist Database: System attributes]]

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''Scripting languages: TCL, Perl, Python'''
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]

'''Code examples'''
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]
* [[How to use MessageCallBackHandler Class | Util/C++: How to use MessageCallBackHandler Class]]
* [[How to use RegisterPragmaRefCallBack() | Util/C++: How to use RegisterPragmaRefCallBack()]]
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
* [[Extract clock enable | Database/C++: Extract clock enable]]
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
* [[Post processing port resolution of black boxes | Database/C++: Post processing port resolution of black boxes]]
* [[Finding hierarchical paths of a Netlist | Database/C++: Finding hierarchical paths of a Netlist]]
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]
* [[Type Range example | Database/Verilog/C++: Type Range example (simple)]]
* [[Type Range example with multi-dimensional arrays| Database/Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
* [[Using TypeRange table to retrieve the originating type-range for an id | Database/Verilog/C++: Using TypeRange table to retrieve the originating type-range for an id]]
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
* [[How to ignore certain modules while analyzing input RTL files | Verilog/C++: How to ignore certain modules while analyzing input RTL files]]
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
* [[In Verilog parsetree adding names to unnamed instances | Verilog/C++: In Verilog parsetree adding names to unnamed instances]]
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
* [[Getting design hierarchy from input RTL files | Verilog/C++/Python: Getting design hierarchy from input RTL files]]
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]
* [[Parse select modules only and ignore the rest | Verilog/C++: Parse select modules only and ignore the rest]]
* [[Create DOT diagram of parse tree | Verilog/C++: Create DOT diagram of a parse tree]]
* [[How to evaluate a Verilog expression | Verilog/C++: How to evaluate a Verilog expression]]
* [[How to get parameters creation-time initial expression/value after Static Elaboration | Verilog/C++: How to get parameters creation-time initial expression/value after Static Elaboration]]
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
* [[Evaluate 'for-generate' loop | Verilog/C++: Evaluate 'for-generate' loop]]
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
* [[How to replace a statement that has a label | SystemVerilog/C++: How to replace a statement that has a label]]
* [[How to insert/add a statement, or a module item, into a sequential block and a generate block | SystemVerilog/C++: How to insert/add a statement, or a module item, into a sequential block and a generate block]]
* [[Simple examples of VHDL visitor pattern | VHDL/C++: Simple examples of VHDL visitor pattern]]
* [[Traverse instances in parsetree | VHDL/C++: Traverse instances in parsetree]]
* [[How to evaluate a VHDL expression | VHDL/C++: How to evaluate a VHDL expression]]
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]

'''INVIO Code examples'''
* [[Simple port modification | SystemVerilog/Python: Simple port modification]]

Static elaboration

2025-10-10T17:07:39Z

Vince:

'''Q: What does 'static elaboration' do?'''

Static elaboration runs after analysis. It modifies the parsetree. During static elaboration:

* Identify top-level modules and tree of instantiations under this.
* Defparam statements and module instantiations are processed to calculate the parameter values of the modules for every instantiation.
* Hierarchical names are checked for their validity and usage. These hierarchical names remain in designs.
* Generate statements are processed. For generate unrolled, if/case generate selects the correct concurrent statements to be present in the module.
* Instance arrays are flattened.
* Depending on hierarchical name usage and defparam values the same module gets different signatures. They are replicated and proper values are passed within them hierarchically before attaching them to the corresponding instantiations.
* In each module, parameter values are replaced with constant values by evaluating the constant expression assigned to them. Constant expressions include constant function calls, some system function calls AMS function calls and all operators.
* Function and task calls are checked for their validity (if they are defined in higher level of hierarchy and used in lower level).

Sequential code, blocking assignments, tasks and functions are left as is because they are not part of any static context. Only exception are constant function calls - they are replaced with their return values.

If the purpose of the application is to synthesize the design (RTL elaboration), static elaboration is not needed.

Runtime flag 'veri_replace_const_exprs' when set to 1 is to replace following constant expressions with literals:

* Bounds of packed and unpacked ranges in all data declarations.
* Default values of all declared objects if those are constant.
* Delay values
* Reject and error limits of VeriPathPulse values.
* Indexed expressions only if the indexed expression is a bit-select on the LHS of a continuous assignment or output/inout port of module or gate instantiation.

Using 'veri_replace_const_exprs' makes an extra pass on the elaborated parsetree, increasing total time.

There are other runtime flags controlling static elaboration process, e.g.

veri_cleanup_base_modules
veri_copy_top_before_static_elab
veri_do_not_uniquify_interface_instances
veri_preserve_array_instances
veri_preserve_interface_array_instances
veri_share_nodes_in_static_elab
vhdl_uniquify_all_instances
vhdl_copy_top_before_static_elab
vhdl_replace_const_exprs
...

Please see vhdl/VhdlRuntimeFlags.h and verilog/VeriRuntimeFlags.h for a complete list and for more details.

How to save computer resources

2025-10-10T16:51:32Z

Vince:

There are compile flags & runtime flags that may help to reduce memory consumption and/or runtime.
Below are some common ones.

- Compile flag "VERIFIC_MEMORY_MANAGER" in util/VerificSystem.h
Highly recommended.

Enables the new, zero-overhead, Verific memory manager. Typically reduces memory usage of the Verific software by an additional 20% over the default system memory manager.
- Compile flag "DB_USE_PORT_ORDERED_PORTREF" in database/DBCompileFlags.h
Highly recommended.

Organizes the PortRef structures in an ordered array rather than a hash table. This saves a significant amount of memory since PortRefs are no longer individually allocated,
and the overhead of a hash table is also saved.

- Compile flag "VERILOG_QUICK_PARSE_V_FILES" in verilog/VeriCompileFlags.h
Normally a -v file may contain multiple module definitions. The Verilog parser is supposed to pick only the required modules from that file.

However, the file may not contain any of the required modules; instead it is a large file containing many other modules of no interest. In such a case, analyzing and creating a parse tree for the full file will consume much time and memory.

To prevent this, we provide this compile flag to quickly parse the file and see if it is actually required or not, without creating the parse tree. If it is not required we will ignore the file, otherwise we will fully parse it and pick the required modules.

- Compile flag "VERIFIC_LINEFILE_INCLUDES_COLUMNS" in util/VerificSystem.h
If you don't need the starting and ending locations including column info, turn this flag off.

For more details, see [[LineFile data from input files|LineFile data from input files]]
- Runtime flag "veri_improve_include_dir_processing_runtime_for_network_file_system"
Adds directory caching for include directories with simple files (files without a directory specification).

We read the contents of the directory on first encountering it while checking for an include file. Subsequent searches will find the file in the cache instead of the actual disk.

The cache is automatically cleared at the end of the veri_file::Analyze() or veri_file::AnalyzeMultipleFiles() calls. Note that we cannot keep it alive after the two analyze calls since there could possibly be a chdir() call which would make the cache invalid.
- Runtime flag "veri_share_nodes_in_static_elab"

Reduces memory and runtime for large designs. This flag will ensure that only one node will be created in static elaboration for each unique signature of a module, regardless of whether it is a top module or instantiated. The number of nodes that can be reduced depends on the nature of the design. For more details on this flag check [https://www.verific.com/faq/index.php?title=Source_code_customization_%26_Stable_release_services here]

The output netlist is not complete, but is useful if you are interested only in module interfaces and instantiations.

Note that this flag is active only during RTL elaboration, not analysis. The input files still need to be Verilog-legal.
- Runtime flag "veri_ignore_always_constructs"

This enables a "light-weighed" RTL elaboration. "always" constructs in the input RTL Verilog file will be skipped over.

- Runtime flag "edif_delete_view_contents_after_processing"

For EDIF input.

Highly recommended.

Deletes the "contents" of a "view" after processing it, i.e., after creating the netlist. We still keep the "interface", i.e., ports alive so that the view can be instantiated.

- Runtime flag "edif_link_case_insensitive"

For EDIF input.

EDIF LRM does not define how existing external cells (maybe parsed from another language) should be linked to EDIF cells. We implemented case-insensitive (linear) search for these, which causes an N^2 complexity problem that slows down the reader for very large designs. Switching to case-sensitive search significantly speeds up the process, but there may be incidental cases where the EDIF reader does not link to an existing cell parsed from a different file.

- Runtime flag "edif_keep_existing_view"

For EDIF input.

When stitching designs from multiple files, a view may be defined in more than one file. By default ("edif_keep_existing_view" disabled), the view being currently read survives, replacing the existing view. This may slow down the process because the existing view and all of its references in the Netlist Database has to be updated.

Enabling "edif_keep_existing_view" allows the reader to ignore the (duplicated) view being currently read. All references to the view being ignored will be updated to point to the existing view in the Netlist Database. Only the references to the current view (in the current read operation) need to be updated to point to the existing view.

Support IEEE 1735 encryption standard

2024-10-29T20:28:39Z

Vince:

'''Q: Does Verific provide support for IEEE 1735 encryption standard?'''

''Note: This article mentions only "encryption/decryption '''algorithms'''," but the same arguments also apply to "encryption/decryption '''keys'''."''

Verific provides APIs with which our licensees can plug in their proprietary encryption/decryption algorithms.

For technical details, please see:

[http://www.verific.com/docs/index.php?title=Parsing_Protected_and_IEEE_1735_Encrypted_RTL_Files Parsing Protected and IEEE 1735 Encrypted RTL Files]
(contact Verific Tech Support if you don't have credentials for Verific Documentation).

There are application examples in Verific's software distribution:

examples/verilog/parse_encrypted_RTL
examples/verilog/parse_encrypted_RTL_1735style

Verific does not implement nor provide our own encryption/decryption algorithms for several reasons:

* If Verific were to provide encryption algorithms, we would have to provide the decryption algorithms. Verific has always been shipping source code and is not set up to ship binaries. If Verific shipped the implementations of the encryption/decryption algorithms in the form of C++ source code, that would defeat the purpose of encryption in the first place.

* If Verific provided encryption/decryption algorithms, we would ship the same implementations to all of our licensees. Many licensees of our licensees are direct competitors of each other. A company would not want its competitors to have access to its encryption/decryption algorithms.

* As a provider of encryption/decryption algorithms, Verific would be responsible for providing measures to prevent security breaches. Since the encryption/decryption implementations would be shipped to multiple licensees, there would be no guarantee that the algorithms would enjoy the same protection as the licensees' IPs would. It is not fair nor practical to expect Verific to bear this responsibility.

So the task of encryption/decryption implementations is appropriately reserved to the licensee.

'''Mixing preprocessor directives and encryption blocks'''

The IEEE-1735 LRM is not clear about the precedence of protected blocks and `ifdef macros. In fact there is a suggestion in Annex C.3 to ''not'' mix encrypted blocks and macros since the behavior could be ambiguous:

''The SystemVerilog language has non-pragma preprocessor block syntaxes such as text-replacement macro definitions and conditional compilation `ifdefs. There are also known, non-LRM, tool pragma, and smart comment extensions that control behaviors such as coverage and synthesis for blocks of code. The relative precedence of these syntaxes is often unclear and the resulting HDL interpretation may be tool-dependent. HDL authors are advised to avoid these source ambiguities where possible.''

Lets take this example:

module test ;
`ifdef UNDEFINED_MACRO
`pragma protect begin_protected
`endif
endmodule

For the above code, popular simulators produce ERRORs even if UNDEFINED_MACRO is not defined in the RTL. Apparently, the macro block does not cause the protected area to be ignored even though it is in the inactive region.

Also, both `ifdef and `protected behave like text processing directives. They do not really follow language rules/semantics the way other constructs such as functions/modules, etc., do. For example, a tool that encrypts a design containing a protection envelop does not care about other Verilog constructs including any macros present. This is required so that the encrypted design can still include macros in the encrypted block and can refer to them later when the block is expanded.

Support IEEE 1735 encryption standard

2024-10-29T16:35:18Z

Vince:

Create DOT diagram of parse tree

2024-08-28T21:14:46Z

Vince:

This example parses the r4000 design in the <verific>/example_designs/verilog directory and writes out a Graphviz DOT-format file that represents a simple diagram view of the design.

There are several tools that can visualize DOT files. On Linux distributions you can install 'dot'. You would run this command to create a PDF output of the C++ application below

dot -Tpdf pp_out.dot -o r4000.pdf

C++:
<nowiki>
#include <iostream>
#include "veri_file.h"
#include "VeriModule.h"
#include "VeriId.h"
#include "VeriExpression.h"
#include "Map.h"

using namespace std ;
#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main()
{
char ppfile_nm[32] = "pp_out.dot";
char transition[64] ;
unsigned module_cnt = 0 ;
unsigned field_cnt = 0 ;
Array transition_table ;
Array instantiation_table ;
Array module_table ;

ofstream ofs(ppfile_nm, std::ios::out) ;

if (!veri_file::Analyze("r4000.v", veri_file::SYSTEM_VERILOG)) return 1 ;

ofs << "digraph Verific {" << endl ;
ofs << " rankdir = LR" << endl ;
ofs << " node [shape=plaintext]" << endl ;
ofs << " edge [dir=forward]" << endl ;

Array *tops = veri_file::GetTopModules() ;

MapIter mi ;
VeriModule *mod, *top ;
unsigned i ;
FOREACH_VERILOG_MODULE(mi, mod) {
if (!mod || mod->IsPackage() || mod->IsRootModule()) continue ;
module_table.Insert(mod) ;
}

unsigned mc ;
FOREACH_ARRAY_ITEM(&module_table, mc, mod) {
ofs << " cell" << module_cnt ;
ofs << " [label=< <TABLE BORDER=\"0\" CELLBORDER=\"1\" CELLSPACING=\"0\">" << endl ;

unsigned found = 0 ;
FOREACH_ARRAY_ITEM(tops, i, top) {
if (Strings::compare(top->Name(), mod->Name())) {
found = 1 ;
break ;
}
}

if (found)
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt++ << "\" COLOR=\"red\" BGCOLOR=\"yellow\"> <FONT COLOR=\"red\">MODULE : " << mod->Name() << "</FONT> </TD> </TR>" << endl ;
else
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt++ << "\" BGCOLOR=\"gray\">MODULE : " << mod->Name() << "</TD> </TR>" << endl ;

Array *ports = mod->GetPorts();
if (ports) {
VeriIdDef *port ;
FOREACH_ARRAY_ITEM(ports, i, port) {
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt++ << "\"> port : " << port->Name() << "</TD> </TR>" << endl ;
}
}

Array *params = mod->GetParameters();
if (params) {
VeriIdDef *param ;
FOREACH_ARRAY_ITEM(params, i, param) {
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt++ << "\"> parameter : " << param->Name() ;
VeriExpression *initvalue = param->GetInitialValue();
if (initvalue)
ofs << " = " << initvalue->GetPrettyPrintedString() << "</TD> </TR>" << endl ;
}
}

Array *module_items = mod->GetModuleItems() ;
VeriModuleItem *module_item ;
FOREACH_ARRAY_ITEM(module_items, i, module_item) {
switch (module_item->GetClassId()) {
case ID_VERIMODULEINSTANTIATION:
{
VeriModuleInstantiation *mod_inst = static_cast<VeriModuleInstantiation*>(module_item) ;
unsigned j ;
VeriInstId *inst_id ;
FOREACH_ARRAY_ITEM(mod_inst->GetIds(), j, inst_id) {
if (!inst_id) continue ;

instantiation_table.Insert(inst_id) ;
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt << "\"> instantiation : " << mod_inst->GetModuleName() << " : " << inst_id->InstName() << "</TD> </TR>" << endl ;
unsigned k ;
VeriModule *inst ;
FOREACH_ARRAY_ITEM(&module_table, k, inst) {
if (Strings::compare(inst_id->GetModuleReference(), inst->Name())) {
sprintf (transition, " cell%d:f%d -> cell%d:f0 ;", module_cnt, field_cnt, k) ;
char *trans = Strings::save(transition) ;
transition_table.Insert(trans) ;
}
}
field_cnt++ ;
}
}
default : ;
}
}

ofs << " </TABLE> >] ;" << endl ;
field_cnt = 0 ;
module_cnt++ ;
}

ofs << endl ;

char *trans ;
FOREACH_ARRAY_ITEM(&transition_table, i, trans) {
ofs << trans << endl ;
}

ofs << "}" << endl ;
ofs.close();

return 0 ;
}
</nowiki>

Create DOT diagram of parse tree

2024-08-28T21:12:56Z

Vince:

This example parses the r4000 design in the <verific>/example_designs/verilog directory and writes out a Graphviz DOT-format file that represents a simple diagram view of the design.

There are several tools that can visualize DOT files. On Linux distributions you can install 'dot'. You would run this command to create a PDF output of the C++ application below

dot -Tpdf pp_out.dot -o r4000.pdf

C++:
<nowiki>
#include <iostream>
#include "veri_file.h"
#include "VeriModule.h"
#include "VeriId.h"
#include "VeriExpression.h"
#include "Map.h"

using namespace std ;
#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main()
{
char ppfile_nm[32] = "pp_out.dot";
char transition[64] ;
unsigned module_cnt = 0 ;
unsigned field_cnt = 0 ;
Array transition_table ;
Array instantiation_table ;
Array module_table ;

ofstream ofs(ppfile_nm, std::ios::out) ;

if (!veri_file::Analyze("r4000.v", veri_file::SYSTEM_VERILOG)) return 1 ;

ofs << "digraph Verific {" << endl ;
ofs << " rankdir = LR" << endl ;
ofs << " node [shape=plaintext]" << endl ;
ofs << " edge [dir=forward]" << endl ;

Array *tops = veri_file::GetTopModules() ;

MapIter mi ;
VeriModule *mod, *top ;
unsigned i ;
FOREACH_VERILOG_MODULE(mi, mod) {
if (!mod || mod->IsPackage() || mod->IsRootModule()) continue ;
module_table.Insert(mod) ;
}

unsigned mc ;
FOREACH_ARRAY_ITEM(&module_table, mc, mod) {
ofs << " cell" << module_cnt ;
ofs << " [label=< <TABLE BORDER=\"0\" CELLBORDER=\"1\" CELLSPACING=\"0\">" << endl ;

unsigned found = 0 ;
FOREACH_ARRAY_ITEM(tops, i, top) {
if (Strings::compare(top->Name(), mod->Name())) {
found = 1 ;
break ;
}
}

if (found)
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt++ << "\" COLOR=\"red\" BGCOLOR=\"yellow\"> <FONT COLOR=\"red\">MODULE : " << mod->Name() << "</FONT> </TD> </TR>" << endl ;
else
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt++ << "\" BGCOLOR=\"gray\">MODULE : " << mod->Name() << "</TD> </TR>" << endl ;

Array *ports = mod->GetPorts();
if (ports) {
VeriIdDef *port ;
FOREACH_ARRAY_ITEM(ports, i, port) {
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt++ << "\"> port : " << port->Name() << "</TD> </TR>" << endl ;
}
}

Array *params = mod->GetParameters();
if (params) {
VeriIdDef *param ;
FOREACH_ARRAY_ITEM(params, i, param) {
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt++ << "\"> parameter : " << param->Name() ;
VeriExpression *initvalue = param->GetInitialValue();
if (initvalue)
ofs << " = " << initvalue->GetPrettyPrintedString() << "</TD> </TR>" << endl ;
}
}

Array *module_items = mod->GetModuleItems() ;
VeriModuleItem *module_item ;
FOREACH_ARRAY_ITEM(module_items, i, module_item) {
switch (module_item->GetClassId()) {
case ID_VERIMODULEINSTANTIATION:
{
VeriModuleInstantiation *mod_inst = static_cast<VeriModuleInstantiation*>(module_item) ;
unsigned j ;
VeriInstId *inst_id ;
FOREACH_ARRAY_ITEM(mod_inst->GetIds(), j, inst_id) {
if (!inst_id) continue ;

instantiation_table.Insert(inst_id) ;
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt << "\"> instantiation : " << mod_inst->GetModuleName() << " : " << inst_id->InstName() << "</TD> </TR>" << endl ;
unsigned k ;
VeriModule *inst ;
FOREACH_ARRAY_ITEM(&module_table, k, inst) {
if (Strings::compare(inst_id->GetModuleReference(), inst->Name())) {
sprintf (transition, " cell%d:f%d -> cell%d:f0 ;", module_cnt, field_cnt, k) ;
char *trans = Strings::save(transition) ;
transition_table.Insert(trans) ;
}
}

field_cnt++ ;
}
}
default : ;
}
}

ofs << " </TABLE> >] ;" << endl ;
field_cnt = 0 ;
module_cnt++ ;
}

ofs << endl ;

char *trans ;
FOREACH_ARRAY_ITEM(&transition_table, i, trans) {
ofs << trans << endl ;
}

ofs << "}" << endl ;
ofs.close();

return 0 ;
}
</nowiki>

Yosys-Verific Integration

2024-08-23T16:05:25Z

Vince:

Yosys is an open source platform that works with a suite of EDA tools. It is possible for a Verific user to integrate Verific with Yosys, which would replace the open source language parsers with Verific's industry-standard ones. Below are several points of interest :

* The minimum requirement to use open source Yosys (as downloaded from YosysHQ https://github.com/yosyshq/yosys) together with Verific software is to have either the VHDL or Verilog/SystemVerilog parser and the RTL elaborator licensed from Verific.

* For users of Verific who have the above minimum configuration and additionally license Verific's Static elaborator, you have the option to purchase a patch of language extensions from YosysHQ to enable basic formal verification functionality in the Yosys open source suite.

* If comprehensive formal verification functionality is desired, the recommended option is to go with the TabbyCAD commercial suite from YosysHQ. A TabbyCAD customer would gain full access to YosysHQ's support, training, and other services.

For more details on integrating with Yosys, please refer to this link :

https://yosyshq.readthedocs.io/projects/yosys/en/latest/yosys_internals/extending_yosys/build_verific.html

Yosys-Verific Integration

2024-08-17T04:24:49Z

Vince: Created page with "Yosys is an open source platform that works with a suite of EDA tools. It is possible for a Verific user to integrate Verific with Yosys, which would replace the open source..."

Yosys is an open source platform that works with a suite of EDA tools. It is possible for a Verific user to integrate Verific with Yosys, which would replace the open source language parsers with Verific's industry-standard ones. Below are several points of interest :

* The minimum requirement to use open source Yosys (as downloaded from YosysHQ https://github.com/yosyshq/yosys) together with Verific software is to have either the VHDL or Verilog/SystemVerilog parser and the RTL elaborator licensed from Verific.

* For users of Verific who have the above minimum configuration and additionally license Verific's Static elaborator, you have the option to purchase a patch of language extensions from YosysHQ to enable basic formal verification functionality in the Yosys open source suite.

* If comprehensive formal verification functionality is desired, the recommended option is to go with the TabbyCAD commercial suite from YosysHQ. A TabbyCAD customer would gain full access to YosysHQ's support, training, and other services.

For more details on integrating with Yosys, please refer to this link :

https://tyrtd.readthedocs.io/en/krys-docs_verific/yosys_internals/extending_yosys/build_verific.html

Main Page

2024-08-17T04:18:45Z

Vince:

'''General'''
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
* [[Source code customization & Stable release services | Source code customization & Stable release services]]
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]
* [[Release version | How do I tell the version of a Verific software release? ]]
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
* [[LineFile data from input files | LineFile data from input files]]
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]
* [[Preserving user nets - preventing nets from being optimized away | Preserving user nets - preventing nets from being optimized away]]
* [[Python pretty-printer for gdb | Python pretty-printer for gdb]]
* [[Yosys-Verific Integration | Yosys-Verific integration]]

'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Port Expressions]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[Modules with '_1' '_2' suffix in their names | Verilog: After static elaboration, there are modules with "_1", "_2", ..., suffix in their names. Why?]]
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
* [[Notes on analysis | SystemVerilog: Notes on analysis]]
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units/interfaces with "_default" suffix in their names. Why? And what are they?]]
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
'''Netlist Database'''
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]
* [[System attributes | Netlist Database: System attributes]]

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''Scripting languages: TCL, Perl, Python'''
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]

'''Code examples'''
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]
* [[How to use MessageCallBackHandler Class | Util/C++: How to use MessageCallBackHandler Class]]
* [[How to use RegisterPragmaRefCallBack() | Util/C++: How to use RegisterPragmaRefCallBack()]]
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
* [[Extract clock enable | Database/C++: Extract clock enable]]
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
* [[Post processing port resolution of black boxes | Database/C++: Post processing port resolution of black boxes]]
* [[Finding hierarchical paths of a Netlist | Database/C++: Finding hierarchical paths of a Netlist]]
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]
* [[Type Range example | Database/Verilog/C++: Type Range example (simple)]]
* [[Type Range example with multi-dimensional arrays| Database/Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
* [[Using TypeRange table to retrieve the originating type-range for an id | Database/Verilog/C++: Using TypeRange table to retrieve the originating type-range for an id]]
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
* [[How to ignore certain modules while analyzing input RTL files | Verilog/C++: How to ignore certain modules while analyzing input RTL files]]
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
* [[In Verilog parsetree adding names to unnamed instances | Verilog/C++: In Verilog parsetree adding names to unnamed instances]]
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]
* [[Parse select modules only and ignore the rest | Verilog/C++: Parse select modules only and ignore the rest]]
* [[Create DOT diagram of parse tree | Verilog/C++: Create DOT diagram of a parse tree]]
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
* [[Evaluate 'for-generate' loop | Verilog/C++: Evaluate 'for-generate' loop]]
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
* [[Simple examples of VHDL visitor pattern | VHDL/C++: Simple examples of VHDL visitor pattern]]
* [[Traverse instances in parsetree | VHDL/C++: Traverse instances in parsetree]]
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]

Traverse instances in parsetree

2024-07-23T04:44:18Z

Vince:

C++:
<nowiki>
// Verific utilities
#include "Array.h" // Make class Array available
#include "Set.h" // Make class Set available
#include "Message.h" // Make message handlers available
#include "Strings.h" // Definition of class to manipulate, copy, concatenate, create etc...
// Verific Verilog parser
#include "VeriModule.h"
#include "veri_file.h"

// Verific VHDL parser
#include "vhdl_file.h"
#include "VhdlIdDef.h"
#include "VhdlScope.h"
#include "VhdlStatement.h"
#include "VhdlName.h" // Definition of VhdlName
#include "VhdlUnits.h" // Definition of VhdlLibrary

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

// Routines for traversing the entity instances in DFS order and print them.
static void PrintDesignUnit(const VhdlStatement *stmt) ;
static void TraverseVhdl(const VhdlPrimaryUnit *top, const char *arch_name) ;

int main(int argc, const char **argv)
{

vhdl_file::SetDefaultLibraryPath("../vdbs") ;

if (!veri_file::Analyze("test.v")) return 1 ;
if (!vhdl_file::Analyze("test.vhd")) return 1 ;

VhdlLibrary *lib = vhdl_file::GetLibrary("work") ;
VhdlPrimaryUnit *top_entity = lib ? lib->GetPrimUnit("comp") : 0 ; // Get the top-level entity
if (!top_entity) {
return 1 ;
}

if (!vhdl_file::Elaborate("comp", "work", 0, 0, 1)) {
return 2 ;
}

Message::PrintLine("\n") ;
top_entity->Info("Start hierarchy traversal here at VHDL top level unit '%s'", top_entity->Name()) ;
Message::PrintLine("\n") ;
TraverseVhdl(top_entity, 0 /*architecture name*/) ; // Traverse top level unit and the hierarchy under it
return 0 ; // all good
}

// Traverse an entity and the hierarchy under it:
static void
TraverseVhdl(const VhdlPrimaryUnit *unit, const char *arch_name)
{
// Find the architecture of the unit:
VhdlSecondaryUnit *arch = unit? unit->GetSecondaryUnit(arch_name) : 0 ;
// Find the scope:
VhdlScope *scope = arch ? arch->LocalScope() : 0 ;

// Get the declared ids from that scope:
Map *ids = scope ? scope->DeclArea() : 0 ;
MapIter mi ;
VhdlIdDef *id ;
FOREACH_MAP_ITEM(ids, mi, 0, &id) {
if (!id) continue ;
VhdlStatement *stmt = id->GetStatement() ;
if (!stmt) continue ;
// Routine to print the hierarchy:
PrintDesignUnit(stmt) ;
}
}

// Print the hierarchy
static void PrintDesignUnit(const VhdlStatement *stmt)
{
if (!stmt) return ;

// Get the array of statements, for loop/block statements
// we get an array of statements and recursively go to the
// inner most statement and print the hierarchy.
Array *stmts = stmt->GetStatements() ;
unsigned ai ;
VhdlStatement *inner_stmt ;
FOREACH_ARRAY_ITEM(stmts, ai, inner_stmt) {
PrintDesignUnit(inner_stmt) ;
}

VhdlIdDef *inst_unit = stmt->GetInstantiatedUnit() ; // Get the instantiated unit id for instances only
if (!inst_unit) return ; // Not an instance level

// Processing instance
VhdlIdDef *id = stmt->GetLabel() ;
Message::PrintLine("Processing instance : ", id ? id->Name() : 0) ;

if (inst_unit->IsComponent()) { // instance of component
Message::PrintLine("Component instance, name of component is ", inst_unit->Name()) ;
Message::PrintLine("\n") ;
}

VhdlPrimaryUnit *prim_unit = inst_unit ? inst_unit->GetPrimaryUnit() : 0 ; // Get the primary unit
if (!prim_unit) return ;

if (prim_unit->IsVerilogModule()) { // instance of Verilog module
// Get instantiated verilog module
VeriModule *veri_module = vhdl_file::GetVerilogModuleFromlib(inst_unit->GetContainingLibraryName(), inst_unit->Name()) ;
if (!veri_module) return ;
Message::PrintLine("instantiated Verilog module : ", veri_module->Name()) ;
Message::PrintLine("\n") ;
} else { // Instance of vhdl unit
VhdlName *instantiated_unit_name = stmt->GetInstantiatedUnitNameNode() ;
// Find the architecture name and traverse the vhdl design
const char *arch_name = instantiated_unit_name ? instantiated_unit_name->ArchitectureNameAspect(): 0 ;
Message::PrintLine("instantiated VHDL unit : ", prim_unit->Name()) ;
Message::PrintLine("architecture name : ", arch_name ? arch_name : 0) ;
Message::PrintLine("\n") ;
TraverseVhdl(prim_unit, arch_name) ; // Traverse the VHDL unit
}
}
</nowiki>

Python script:
<nowiki>
#!/usr/bin/python

import sys
sys.path.append('../../pythonmain/install')
import Verific

def TraverseVhdl(unit, arch_name):
# Find the architecture of the unit:
if not unit: return
arch = unit.GetSecondaryUnit(arch_name)
if not arch: return
# Find the scope:
scope = arch.LocalScope()
if not scope: return

# Get the declared ids from that scope:
ids = Verific.VhdlIdDefMapIter(scope.DeclArea())
id = ids.First()
while (id):
stmt = id.GetStatement()
if not stmt:
id = ids.Next()
continue
# Routine to print the hierarchy:
PrintDesignUnit(stmt)
id = ids.Next()

def PrintDesignUnit(stmt):
if not stmt: return

# Get the array of statements, for loop/block statements
# we get an array of statements and recursively go to the
# inner most statement and print the hierarchy.
stmts = Verific.VhdlStatementArrayIter(stmt.GetStatements())
inner_stmt = stmts.First()
while (inner_stmt):
PrintDesignUnit(inner_stmt)
inner_stmt = stmts.Next()

inst_unit = stmt.GetInstantiatedUnit() # Get the instantiated unit id for instances only
if not inst_unit: return # Not an instance level

# Processing instance
id = stmt.GetLabel()
if not id: return
Verific.Message.PrintLine("Processing instance : ", id.Name())

if inst_unit.IsComponent():
Verific.Message.PrintLine("Component instance, name of component is ", inst_unit.Name())
Verific.Message.PrintLine("\n")

prim_unit = inst_unit.GetPrimaryUnit()
if not prim_unit: return

if prim_unit.IsVerilogModule():
# Get instantiated verilog module
veri_module = Verific.vhdl_file.GetVerilogModuleFromlib(inst_unit.GetContainingLibraryName(), inst_unit.Name())
if not veri_module: return
Verific.Message.PrintLine("instantiated Verilog module : ", veri_module.Name())
Verific.Message.PrintLine("\n")
else:
instantiated_unit_name = stmt.GetInstantiatedUnitNameNode()
if not instantiated_unit_name: return
# Find the architecture name and traverse the vhdl design
arch_name = instantiated_unit_name.ArchitectureNameAspect()
if not arch_name: return
Verific.Message.PrintLine("instantiated VHDL unit : ", prim_unit.Name())
Verific.Message.PrintLine("architecture name : ", arch_name)
Verific.Message.PrintLine("\n")
TraverseVhdl(prim_unit, arch_name) # Traverse the VHDL unit

# Set default library path to auto-load standard packages
if not Verific.vhdl_file.SetDefaultLibraryPath("../../vhdl_packages/vdbs_1993"):
print ("Error during analysis, exiting")
sys.exit(1)

# Analyze the design
if not Verific.veri_file.Analyze("test.v", Verific.veri_file.SYSTEM_VERILOG, "work"):
print ("Analyze failure. Exiting")
sys.exit(2)

if not Verific.vhdl_file.Analyze("test.vhd", "work", Verific.vhdl_file.VHDL_93):
print ("Analyze failure. Exiting")
sys.exit(2)

# Get the library
lib = Verific.vhdl_file.GetLibrary("work")
if not lib:
print ("Can't get library 'work'")
sys.exit(3)

# Check all the primary units of the library
top_entity = lib.GetPrimUnit("comp")
if not top_entity:
sys.exit(4)

if not Verific.vhdl_file.Elaborate("comp", "work", None, None, 1):
sys.exit(5)

Verific.Message.PrintLine("\n")
top_entity.Info("Start hierarchy traversal here at VHDL top level unit '%s'", top_entity.Name())
Verific.Message.PrintLine("\n")
TraverseVhdl(top_entity, None)
</nowiki>

test.vhd:
<nowiki>
entity child is -- instantiated in test module in Verilog design
generic (p : integer := 3);
port (S1, S2: out bit_vector (p downto 0);
I1 : in bit_vector (p downto 0));
end ;

architecture arch of child is
begin
S1 <= I1 ;
S2 <= not I1 ;
end ;

entity comp is -- top-level unit

port(X, Y: in BIT_VECTOR(3 DOWNTO 0);
S1, S2: out bit_vector (3 DOWNTO 0);
S3, S4: out bit_vector (3 DOWNTO 0);
Sum, Carry: out BIT);

end;

architecture Structure of comp is

component child is
generic (p : integer) ;
port (S1, S2: out BIT_VECTOR(p DOWNTO 0);
I1 : in BIT_VECTOR(p downto 0));
end component;

begin

L1: entity work.xor_gate generic map (4)
port map (X, Y, Sum);

L2 : component child generic map (3) port map(S1, S2, X) ;
blk : block
begin
L3 : entity work.child(arch) generic map (3) port map(S3, S4, X) ;
end block ;

end;
</nowiki>

test.v:
<nowiki>
module xor_gate (CompIn1, CompIn2, CompOut); // Instantiated in 'comp' entity in VHDL file test.vhd
parameter p = 10 ;
input [3:0]CompIn1;
input [3:0]CompIn2;
output CompOut;
endmodule
</nowiki>

Run:
<nowiki>
[hoa@awing0 HD]$ test-linux
-- Analyzing Verilog file 'test.v' (VERI-1482)
-- Analyzing VHDL file 'test.vhd' (VHDL-1481)
-- Restoring VHDL unit 'std.standard' from file '../vdbs/std/standard.vdb' (VHDL-1493)
test.vhd(1): INFO: analyzing entity 'child' (VHDL-1012)
test.vhd(7): INFO: analyzing architecture 'arch' (VHDL-1010)
test.vhd(13): INFO: analyzing entity 'comp' (VHDL-1012)
test.vhd(22): INFO: analyzing architecture 'structure' (VHDL-1010)
-- Restoring VHDL unit 'vl.vl_types' from file '../vdbs/vl/vl_types.vdb' (VHDL-1493)
test.vhd(13): INFO: processing 'comp(Structure)' (VHDL-1067)
test.vhd(33): INFO: switching to Verilog mode to elaborate module 'xor_gate' (VHDL-1399)
test.v(1): INFO: compiling module 'xor_gate(p=4)' (VERI-1018)
test.vhd(33): INFO: returning to VHDL mode to continue with elaboration (VHDL-1400)
test.vhd(1): INFO: processing 'child_default(arch)' (VHDL-1067)
--

test.vhd(20): INFO: Start hierarchy traversal here at VHDL top level unit 'comp'
--

-- Processing instance : l1
-- instantiated Verilog module : xor_gate(p=4)
--

-- Processing instance : l2
-- instantiated VHDL unit : child_default
-- architecture name : arch
--

-- Processing instance : l3
-- instantiated VHDL unit : child_default
-- architecture name : arch
--

[hoa@awing0 HD]$
</nowiki>

Traverse instances in parsetree

2024-07-23T04:40:54Z

Vince:

C++:
<nowiki>
// Verific utilities
#include "Array.h" // Make class Array available
#include "Set.h" // Make class Set available
#include "Message.h" // Make message handlers available
#include "Strings.h" // Definition of class to manipulate, copy, concatenate, create etc...
// Verific Verilog parser
#include "VeriModule.h"
#include "veri_file.h"

// Verific VHDL parser
#include "vhdl_file.h"
#include "VhdlIdDef.h"
#include "VhdlScope.h"
#include "VhdlStatement.h"
#include "VhdlName.h" // Definition of VhdlName
#include "VhdlUnits.h" // Definition of VhdlLibrary

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

// Routines for traversing the entity instances in DFS order and print them.
static void PrintDesignUnit(const VhdlStatement *stmt) ;
static void TraverseVhdl(const VhdlPrimaryUnit *top, const char *arch_name) ;

int main(int argc, const char **argv)
{

vhdl_file::SetDefaultLibraryPath("../vdbs") ;

if (!veri_file::Analyze("test.v")) return 1 ;
if (!vhdl_file::Analyze("test.vhd")) return 1 ;

VhdlLibrary *lib = vhdl_file::GetLibrary("work") ;
VhdlPrimaryUnit *top_entity = lib ? lib->GetPrimUnit("comp") : 0 ; // Get the top-level entity
if (!top_entity) {
return 1 ;
}

if (!vhdl_file::Elaborate("comp", "work", 0, 0, 1)) {
return 2 ;
}

Message::PrintLine("\n") ;
top_entity->Info("Start hierarchy traversal here at VHDL top level unit '%s'", top_entity->Name()) ;
Message::PrintLine("\n") ;
TraverseVhdl(top_entity, 0 /*architecture name*/) ; // Traverse top level unit and the hierarchy under it
return 0 ; // all good
}

// Traverse an entity and the hierarchy under it:
static void
TraverseVhdl(const VhdlPrimaryUnit *unit, const char *arch_name)
{
// Find the architecture of the unit:
VhdlSecondaryUnit *arch = unit? unit->GetSecondaryUnit(arch_name) : 0 ;
// Find the scope:
VhdlScope *scope = arch ? arch->LocalScope() : 0 ;

// Get the declared ids from that scope:
Map *ids = scope ? scope->DeclArea() : 0 ;
MapIter mi ;
VhdlIdDef *id ;
FOREACH_MAP_ITEM(ids, mi, 0, &id) {
if (!id) continue ;
VhdlStatement *stmt = id->GetStatement() ;
if (!stmt) continue ;
// Routine to print the hierarchy:
PrintDesignUnit(stmt) ;
}
}

// Print the hierarchy
static void PrintDesignUnit(const VhdlStatement *stmt)
{
if (!stmt) return ;

// Get the array of statements, for loop/block statements
// we get an array of statements and recursively go to the
// inner most statement and print the hierarchy.
Array *stmts = stmt->GetStatements() ;
unsigned ai ;
VhdlStatement *inner_stmt ;
FOREACH_ARRAY_ITEM(stmts, ai, inner_stmt) {
PrintDesignUnit(inner_stmt) ;
}

VhdlIdDef *inst_unit = stmt->GetInstantiatedUnit() ; // Get the instantiated unit id for instances only
if (!inst_unit) return ; // Not an instance level

// Processing instance
VhdlIdDef *id = stmt->GetLabel() ;
Message::PrintLine("Processing instance : ", id ? id->Name() : 0) ;

if (inst_unit->IsComponent()) { // instance of component
Message::PrintLine("Component instance, name of component is ", inst_unit->Name()) ;
Message::PrintLine("\n") ;
}

VhdlPrimaryUnit *prim_unit = inst_unit ? inst_unit->GetPrimaryUnit() : 0 ; // Get the primary unit
if (!prim_unit) return ;

if (prim_unit->IsVerilogModule()) { // instance of Verilog module
// Get instantiated verilog module
VeriModule *veri_module = vhdl_file::GetVerilogModuleFromlib(inst_unit->GetContainingLibraryName(), inst_unit->Name()) ;
if (!veri_module) return ;
Message::PrintLine("instantiated Verilog module : ", veri_module->Name()) ;
Message::PrintLine("\n") ;
} else { // Instance of vhdl unit
VhdlName *instantiated_unit_name = stmt->GetInstantiatedUnitNameNode() ;
// Find the architecture name and traverse the vhdl design
const char *arch_name = instantiated_unit_name ? instantiated_unit_name->ArchitectureNameAspect(): 0 ;
Message::PrintLine("instantiated VHDL unit : ", prim_unit->Name()) ;
Message::PrintLine("architecture name : ", arch_name ? arch_name : 0) ;
Message::PrintLine("\n") ;
TraverseVhdl(prim_unit, arch_name) ; // Traverse the VHDL unit
}
}
</nowiki>

test.vhd:
<nowiki>
entity child is -- instantiated in test module in Verilog design
generic (p : integer := 3);
port (S1, S2: out bit_vector (p downto 0);
I1 : in bit_vector (p downto 0));
end ;

architecture arch of child is
begin
S1 <= I1 ;
S2 <= not I1 ;
end ;

entity comp is -- top-level unit

port(X, Y: in BIT_VECTOR(3 DOWNTO 0);
S1, S2: out bit_vector (3 DOWNTO 0);
S3, S4: out bit_vector (3 DOWNTO 0);
Sum, Carry: out BIT);

end;

architecture Structure of comp is

component child is
generic (p : integer) ;
port (S1, S2: out BIT_VECTOR(p DOWNTO 0);
I1 : in BIT_VECTOR(p downto 0));
end component;

begin

L1: entity work.xor_gate generic map (4)
port map (X, Y, Sum);

L2 : component child generic map (3) port map(S1, S2, X) ;
blk : block
begin
L3 : entity work.child(arch) generic map (3) port map(S3, S4, X) ;
end block ;

end;
</nowiki>

test.v:
<nowiki>
module xor_gate (CompIn1, CompIn2, CompOut); // Instantiated in 'comp' entity in VHDL file test.vhd
parameter p = 10 ;
input [3:0]CompIn1;
input [3:0]CompIn2;
output CompOut;
endmodule
</nowiki>

Run:
<nowiki>
[hoa@awing0 HD]$ test-linux
-- Analyzing Verilog file 'test.v' (VERI-1482)
-- Analyzing VHDL file 'test.vhd' (VHDL-1481)
-- Restoring VHDL unit 'std.standard' from file '../vdbs/std/standard.vdb' (VHDL-1493)
test.vhd(1): INFO: analyzing entity 'child' (VHDL-1012)
test.vhd(7): INFO: analyzing architecture 'arch' (VHDL-1010)
test.vhd(13): INFO: analyzing entity 'comp' (VHDL-1012)
test.vhd(22): INFO: analyzing architecture 'structure' (VHDL-1010)
-- Restoring VHDL unit 'vl.vl_types' from file '../vdbs/vl/vl_types.vdb' (VHDL-1493)
test.vhd(13): INFO: processing 'comp(Structure)' (VHDL-1067)
test.vhd(33): INFO: switching to Verilog mode to elaborate module 'xor_gate' (VHDL-1399)
test.v(1): INFO: compiling module 'xor_gate(p=4)' (VERI-1018)
test.vhd(33): INFO: returning to VHDL mode to continue with elaboration (VHDL-1400)
test.vhd(1): INFO: processing 'child_default(arch)' (VHDL-1067)
--

test.vhd(20): INFO: Start hierarchy traversal here at VHDL top level unit 'comp'
--

-- Processing instance : l1
-- instantiated Verilog module : xor_gate(p=4)
--

-- Processing instance : l2
-- instantiated VHDL unit : child_default
-- architecture name : arch
--

-- Processing instance : l3
-- instantiated VHDL unit : child_default
-- architecture name : arch
--

[hoa@awing0 HD]$
</nowiki>

Python:
<nowiki>
#!/usr/bin/python

import sys
sys.path.append('../../pythonmain/install')
import Verific

def TraverseVhdl(unit, arch_name):
# Find the architecture of the unit:
if not unit: return
arch = unit.GetSecondaryUnit(arch_name)
if not arch: return
# Find the scope:
scope = arch.LocalScope()
if not scope: return

# Get the declared ids from that scope:
ids = Verific.VhdlIdDefMapIter(scope.DeclArea())
id = ids.First()
while (id):
stmt = id.GetStatement()
if not stmt:
id = ids.Next()
continue
# Routine to print the hierarchy:
PrintDesignUnit(stmt)
id = ids.Next()

def PrintDesignUnit(stmt):
if not stmt: return

# Get the array of statements, for loop/block statements
# we get an array of statements and recursively go to the
# inner most statement and print the hierarchy.
stmts = Verific.VhdlStatementArrayIter(stmt.GetStatements())
inner_stmt = stmts.First()
while (inner_stmt):
PrintDesignUnit(inner_stmt)
inner_stmt = stmts.Next()

inst_unit = stmt.GetInstantiatedUnit() # Get the instantiated unit id for instances only
if not inst_unit: return # Not an instance level

# Processing instance
id = stmt.GetLabel()
if not id: return
Verific.Message.PrintLine("Processing instance : ", id.Name())

if inst_unit.IsComponent():
Verific.Message.PrintLine("Component instance, name of component is ", inst_unit.Name())
Verific.Message.PrintLine("\n")

prim_unit = inst_unit.GetPrimaryUnit()
if not prim_unit: return

if prim_unit.IsVerilogModule():
# Get instantiated verilog module
veri_module = Verific.vhdl_file.GetVerilogModuleFromlib(inst_unit.GetContainingLibraryName(), inst_unit.Name())
if not veri_module: return
Verific.Message.PrintLine("instantiated Verilog module : ", veri_module.Name())
Verific.Message.PrintLine("\n")
else:
instantiated_unit_name = stmt.GetInstantiatedUnitNameNode()
if not instantiated_unit_name: return
# Find the architecture name and traverse the vhdl design
arch_name = instantiated_unit_name.ArchitectureNameAspect()
if not arch_name: return
Verific.Message.PrintLine("instantiated VHDL unit : ", prim_unit.Name())
Verific.Message.PrintLine("architecture name : ", arch_name)
Verific.Message.PrintLine("\n")
TraverseVhdl(prim_unit, arch_name) # Traverse the VHDL unit

# Set default library path to auto-load standard packages
if not Verific.vhdl_file.SetDefaultLibraryPath("../../vhdl_packages/vdbs_1993"):
print ("Error during analysis, exiting")
sys.exit(1)

# Analyze the design
if not Verific.veri_file.Analyze("test.v", Verific.veri_file.SYSTEM_VERILOG, "work"):
print ("Analyze failure. Exiting")
sys.exit(2)

if not Verific.vhdl_file.Analyze("test.vhd", "work", Verific.vhdl_file.VHDL_93):
print ("Analyze failure. Exiting")
sys.exit(2)

# Get the library
lib = Verific.vhdl_file.GetLibrary("work")
if not lib:
print ("Can't get library 'work'")
sys.exit(3)

# Check all the primary units of the library
top_entity = lib.GetPrimUnit("comp")
if not top_entity:
sys.exit(4)

if not Verific.vhdl_file.Elaborate("comp", "work", None, None, 1):
sys.exit(5)

Verific.Message.PrintLine("\n")
top_entity.Info("Start hierarchy traversal here at VHDL top level unit '%s'", top_entity.Name())
Verific.Message.PrintLine("\n")
TraverseVhdl(top_entity, None)
</nowiki>

Create DOT diagram of parse tree

2024-01-13T02:08:40Z

Vince:

This example parses the r4000 design in the <verific>/example_designs/verilog directory and writes out a Graphviz DOT-format file that represents a simple diagram view of the design.

There are several tools that can visualize DOT files. On Linux distributions you can install 'dot'. You would run this command to create a PDF output of the C++ application below

dot -Tpdf pp_out.dot -o r4000.pdf

C++:
<nowiki>
#include <iostream>
#include "veri_file.h"
#include "VeriModule.h"
#include "VeriId.h"
#include "VeriExpression.h"
#include "VeriVisitor.h"
#include "Map.h"

using namespace std ;
#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main() {

char ppfile_nm[32] = "pp_out.dot";
char transition[64] ;
unsigned module_cnt = 0 ;
unsigned field_cnt = 0 ;
Array transition_table ;
Array instantiation_table ;
Array module_table ;

ofstream ofs(ppfile_nm, std::ios::out) ;

if (!veri_file::Analyze("r4000.v", veri_file::SYSTEM_VERILOG)) return 1 ;

ofs << "digraph Verific {" << endl ;
ofs << " rankdir = LR" << endl ;
ofs << " node [shape=plaintext]" << endl ;
ofs << " edge [dir=forward]" << endl ;

MapIter mi ;
unsigned i ;
VeriModule *mod ;

FOREACH_VERILOG_MODULE(mi, mod)
module_table.Insert(mod) ;

FOREACH_VERILOG_MODULE(mi, mod) {
ofs << " cell" << module_cnt ;
ofs << " [label=< <TABLE BORDER=\"0\" CELLBORDER=\"1\" CELLSPACING=\"0\">" << endl ;
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt++ << "\" BGCOLOR=\"gray\">MODULE : " << mod->Name() << "</TD> </TR>" << endl ;

Array *ports = mod->GetPorts();
if (ports) {
VeriIdDef *port ;
FOREACH_ARRAY_ITEM(ports, i, port) {
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt++ << "\"> port : " << port->Name() << "</TD> </TR>" << endl ;
}
}

Array *params = mod->GetParameters();
if (params) {
VeriIdDef *param ;
FOREACH_ARRAY_ITEM(params, i, param) {
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt++ << "\"> parameter : " << param->Name() ;
VeriExpression *initvalue = param->GetInitialValue();
if (initvalue)
ofs << " = " << initvalue->GetPrettyPrintedString() << "</TD> </TR>" << endl ;
}
}

Array *module_items = mod->GetModuleItems() ;
VeriModuleItem *module_item ;
FOREACH_ARRAY_ITEM(module_items, i, module_item) {
switch (module_item->GetClassId()) {
case ID_VERIMODULEINSTANTIATION:
{
VeriModuleInstantiation *mod_inst = static_cast<VeriModuleInstantiation*>(module_item) ;
unsigned j ;
VeriInstId *inst_id ;
FOREACH_ARRAY_ITEM(mod_inst->GetIds(), j, inst_id) {
if (!inst_id) continue ;

instantiation_table.Insert(inst_id) ;
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt << "\"> instantiations : " << mod_inst->GetModuleName() << " : " << inst_id->InstName() << "</TD> </TR>" << endl ;
unsigned k ;
FOREACH_ARRAY_ITEM(&module_table, k, mod) {
if (Strings::compare(inst_id->GetModuleReference(), mod->Name())) {
sprintf (transition, " cell%d:f%d -> cell%d:f0 ;", module_cnt, field_cnt, k) ;
char *trans = Strings::save(transition) ;
transition_table.Insert(trans) ;
}
}
field_cnt++ ;
}
}
default : ;
}
}

ofs << " </TABLE> >] ;" << endl ;
field_cnt = 0 ;
module_cnt++ ;
}

ofs << endl ;

char *trans ;
FOREACH_ARRAY_ITEM(&transition_table, i, trans) {
ofs << trans << endl ;
}

ofs << "}" << endl ;
ofs.close();

return 0 ;
}
</nowiki>

Create DOT diagram of parse tree

2024-01-13T02:05:44Z

Vince:

This example parses the r4000 design in the <verific>/example_designs/verilog directory and writes out a Graphviz DOT-format file that represents a simple diagram view of the design.

There are several tools that can visualize DOT files. On Linux distributions you can install 'dot'. You would run this command to view the output of the C++ application below

dot -Tpdf pp_out.dot -o r4000.pdf

C++:
<nowiki>
#include <iostream>
#include "veri_file.h"
#include "VeriModule.h"
#include "VeriId.h"
#include "VeriExpression.h"
#include "VeriVisitor.h"
#include "Map.h"

using namespace std ;
#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main() {

char ppfile_nm[32] = "pp_out.dot";
char transition[64] ;
unsigned module_cnt = 0 ;
unsigned field_cnt = 0 ;
Array transition_table ;
Array instantiation_table ;
Array module_table ;

ofstream ofs(ppfile_nm, std::ios::out) ;

if (!veri_file::Analyze("r4000.v", veri_file::SYSTEM_VERILOG)) return 1 ;

ofs << "digraph Verific {" << endl ;
ofs << " rankdir = LR" << endl ;
ofs << " node [shape=plaintext]" << endl ;
ofs << " edge [dir=forward]" << endl ;

MapIter mi ;
unsigned i ;
VeriModule *mod ;

FOREACH_VERILOG_MODULE(mi, mod)
module_table.Insert(mod) ;

FOREACH_VERILOG_MODULE(mi, mod) {
ofs << " cell" << module_cnt ;
ofs << " [label=< <TABLE BORDER=\"0\" CELLBORDER=\"1\" CELLSPACING=\"0\">" << endl ;
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt++ << "\" BGCOLOR=\"gray\">MODULE : " << mod->Name() << "</TD> </TR>" << endl ;

Array *ports = mod->GetPorts();
if (ports) {
VeriIdDef *port ;
FOREACH_ARRAY_ITEM(ports, i, port) {
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt++ << "\"> port : " << port->Name() << "</TD> </TR>" << endl ;
}
}

Array *params = mod->GetParameters();
if (params) {
VeriIdDef *param ;
FOREACH_ARRAY_ITEM(params, i, param) {
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt++ << "\"> parameter : " << param->Name() ;
VeriExpression *initvalue = param->GetInitialValue();
if (initvalue)
ofs << " = " << initvalue->GetPrettyPrintedString() << "</TD> </TR>" << endl ;
}
}

Array *module_items = mod->GetModuleItems() ;
VeriModuleItem *module_item ;
FOREACH_ARRAY_ITEM(module_items, i, module_item) {
switch (module_item->GetClassId()) {
case ID_VERIMODULEINSTANTIATION:
{
VeriModuleInstantiation *mod_inst = static_cast<VeriModuleInstantiation*>(module_item) ;
unsigned j ;
VeriInstId *inst_id ;
FOREACH_ARRAY_ITEM(mod_inst->GetIds(), j, inst_id) {
if (!inst_id) continue ;

instantiation_table.Insert(inst_id) ;
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt << "\"> instantiations : " << mod_inst->GetModuleName() << " : " << inst_id->InstName() << "</TD> </TR>" << endl ;
unsigned k ;
FOREACH_ARRAY_ITEM(&module_table, k, mod) {
if (Strings::compare(inst_id->GetModuleReference(), mod->Name())) {
sprintf (transition, " cell%d:f%d -> cell%d:f0 ;", module_cnt, field_cnt, k) ;
char *trans = Strings::save(transition) ;
transition_table.Insert(trans) ;
}
}
field_cnt++ ;
}
}
default : ;
}
}

ofs << " </TABLE> >] ;" << endl ;
field_cnt = 0 ;
module_cnt++ ;
}

ofs << endl ;

char *trans ;
FOREACH_ARRAY_ITEM(&transition_table, i, trans) {
ofs << trans << endl ;
}

ofs << "}" << endl ;
ofs.close();

return 0 ;
}
</nowiki>

Main Page

2024-01-13T01:59:54Z

Vince:

'''General'''
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
* [[Source code customization & Stable release services | Source code customization & Stable release services]]
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]
* [[Release version | How do I tell the version of a Verific software release? ]]
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
* [[LineFile data from input files | LineFile data from input files]]
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]
* [[Preserving user nets - preventing nets from being optimized away | Preserving user nets - preventing nets from being optimized away]]
* [[Python pretty-printer for gdb | Python pretty-printer for gdb]]

'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Port Expressions]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[Modules with '_1' '_2' suffix in their names | Verilog: After static elaboration, there are modules with "_1", "_2", ..., suffix in their names. Why?]]
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
* [[Notes on analysis | SystemVerilog: Notes on analysis]]
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units/interfaces with "_default" suffix in their names. Why? And what are they?]]
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
'''Netlist Database'''
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]
* [[System attributes | Netlist Database: System attributes]]

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''Scripting languages: TCL, Perl, Python'''
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]

'''Code examples'''
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]
* [[How to use MessageCallBackHandler Class | Util/C++: How to use MessageCallBackHandler Class]]
* [[How to use RegisterPragmaRefCallBack() | Util/C++: How to use RegisterPragmaRefCallBack()]]
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
* [[Extract clock enable | Database/C++: Extract clock enable]]
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
* [[Finding hierarchical paths of a Netlist | Database/C++: Finding hierarchical paths of a Netlist]]
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
* [[Type Range example | Verilog/C++: Type Range example (simple)]]
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
* [[How to ignore certain modules while analyzing input RTL files | Verilog/C++: How to ignore certain modules while analyzing input RTL files]]
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
* [[In Verilog parsetree adding names to unnamed instances | Verilog/C++: In Verilog parsetree adding names to unnamed instances]]
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]
* [[Parse select modules only and ignore the rest | Verilog/C++: Parse select modules only and ignore the rest]]
* [[Create DOT diagram of parse tree | Verilog/C++: Create DOT diagram of a parse tree]]
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
* [[Evaluate 'for-generate' loop | Verilog/C++: Evaluate 'for-generate' loop]]
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
* [[Simple examples of VHDL visitor pattern | VHDL/C++: Simple examples of VHDL visitor pattern]]
* [[Traverse instances in parsetree | VHDL/C++: Traverse instances in parsetree]]
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]

Create DOT diagram of parse tree

2024-01-13T01:57:22Z

Vince: Created page with "This example parses the r4000 design in the <verific>/example_designs/verilog directory and writes out a Graphviz DOT-format file that represents a simple diagram view of th..."

This example parses the r4000 design in the <verific>/example_designs/verilog directory and writes out a Graphviz DOT-format file that represents a simple diagram view of the design.

There are several tools that can visualize DOT files. On Linux distributions you can install 'dot'. For the output of the application below you would run

dot -Tpdf pp_out.dot -o r4000.pdf

C++:
<nowiki>
#include <iostream>
#include "veri_file.h"
#include "VeriModule.h"
#include "VeriId.h"
#include "VeriExpression.h"
#include "VeriVisitor.h"
#include "Map.h"

using namespace std ;
#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main() {

char ppfile_nm[32] = "pp_out.dot";
char transition[64] ;
unsigned module_cnt = 0 ;
unsigned field_cnt = 0 ;
Array transition_table ;
Array instantiation_table ;
Array module_table ;

ofstream ofs(ppfile_nm, std::ios::out) ;

if (!veri_file::Analyze("r4000.v", veri_file::SYSTEM_VERILOG)) return 1 ;

ofs << "digraph Verific {" << endl ;
ofs << " rankdir = LR" << endl ;
ofs << " node [shape=plaintext]" << endl ;
ofs << " edge [dir=forward]" << endl ;

MapIter mi ;
unsigned i ;
VeriModule *mod ;

FOREACH_VERILOG_MODULE(mi, mod)
module_table.Insert(mod) ;

FOREACH_VERILOG_MODULE(mi, mod) {
ofs << " cell" << module_cnt ;
ofs << " [label=< <TABLE BORDER=\"0\" CELLBORDER=\"1\" CELLSPACING=\"0\">" << endl ;
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt++ << "\" BGCOLOR=\"gray\">MODULE : " << mod->Name() << "</TD> </TR>" << endl ;

Array *ports = mod->GetPorts();
if (ports) {
VeriIdDef *port ;
FOREACH_ARRAY_ITEM(ports, i, port) {
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt++ << "\"> port : " << port->Name() << "</TD> </TR>" << endl ;
}
}

Array *params = mod->GetParameters();
if (params) {
VeriIdDef *param ;
FOREACH_ARRAY_ITEM(params, i, param) {
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt++ << "\"> parameter : " << param->Name() ;
VeriExpression *initvalue = param->GetInitialValue();
if (initvalue)
ofs << " = " << initvalue->GetPrettyPrintedString() << "</TD> </TR>" << endl ;
}
}

Array *module_items = mod->GetModuleItems() ;
VeriModuleItem *module_item ;
FOREACH_ARRAY_ITEM(module_items, i, module_item) {
switch (module_item->GetClassId()) {
case ID_VERIMODULEINSTANTIATION:
{
VeriModuleInstantiation *mod_inst = static_cast<VeriModuleInstantiation*>(module_item) ;
unsigned j ;
VeriInstId *inst_id ;
FOREACH_ARRAY_ITEM(mod_inst->GetIds(), j, inst_id) {
if (!inst_id) continue ;

instantiation_table.Insert(inst_id) ;
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt << "\"> instantiations : " << mod_inst->GetModuleName() << " : " << inst_id->InstName() << "</TD> </TR>" << endl ;
unsigned k ;
FOREACH_ARRAY_ITEM(&module_table, k, mod) {
if (Strings::compare(inst_id->GetModuleReference(), mod->Name())) {
sprintf (transition, " cell%d:f%d -> cell%d:f0 ;", module_cnt, field_cnt, k) ;
char *trans = Strings::save(transition) ;
transition_table.Insert(trans) ;
}
}
field_cnt++ ;
}
}
default : ;
}
}

ofs << " </TABLE> >] ;" << endl ;
field_cnt = 0 ;
module_cnt++ ;
}

ofs << endl ;

char *trans ;
FOREACH_ARRAY_ITEM(&transition_table, i, trans) {
ofs << trans << endl ;
}

ofs << "}" << endl ;
ofs.close();

return 0 ;
}
</nowiki>

Main Page

2024-01-13T01:38:06Z

Vince:

'''General'''
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
* [[Source code customization & Stable release services | Source code customization & Stable release services]]
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]
* [[Release version | How do I tell the version of a Verific software release? ]]
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
* [[LineFile data from input files | LineFile data from input files]]
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]
* [[Preserving user nets - preventing nets from being optimized away | Preserving user nets - preventing nets from being optimized away]]
* [[Python pretty-printer for gdb | Python pretty-printer for gdb]]

'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Port Expressions]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[Modules with '_1' '_2' suffix in their names | Verilog: After static elaboration, there are modules with "_1", "_2", ..., suffix in their names. Why?]]
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
* [[Notes on analysis | SystemVerilog: Notes on analysis]]
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units/interfaces with "_default" suffix in their names. Why? And what are they?]]
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
'''Netlist Database'''
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]
* [[System attributes | Netlist Database: System attributes]]

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''Scripting languages: TCL, Perl, Python'''
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]

'''Code examples'''
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]
* [[How to use MessageCallBackHandler Class | Util/C++: How to use MessageCallBackHandler Class]]
* [[How to use RegisterPragmaRefCallBack() | Util/C++: How to use RegisterPragmaRefCallBack()]]
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
* [[Extract clock enable | Database/C++: Extract clock enable]]
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
* [[Finding hierarchical paths of a Netlist | Database/C++: Finding hierarchical paths of a Netlist]]
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
* [[Type Range example | Verilog/C++: Type Range example (simple)]]
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
* [[How to ignore certain modules while analyzing input RTL files | Verilog/C++: How to ignore certain modules while analyzing input RTL files]]
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
* [[In Verilog parsetree adding names to unnamed instances | Verilog/C++: In Verilog parsetree adding names to unnamed instances]]
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]
* [[Parse select modules only and ignore the rest | Verilog/C++: Parse select modules only and ignore the rest]]
* [[Create DOT diagram of parse tree | Verilog/C++: Create DOT diagram of parse tree]]
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
* [[Evaluate 'for-generate' loop | Verilog/C++: Evaluate 'for-generate' loop]]
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
* [[Simple examples of VHDL visitor pattern | VHDL/C++: Simple examples of VHDL visitor pattern]]
* [[Traverse instances in parsetree | VHDL/C++: Traverse instances in parsetree]]
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]

Modules/design units with " default" suffix in their names

2023-10-23T15:37:41Z

Vince:

'''Q: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they? '''

Static elaboration process is a multiple-iteration process and modules/design units may be modified differently in each iteration.

We need to keep original version of modules/design units as they are immediately after analysis so that they can be copied for different parameter/generic settings in each iteration and body of copied modules/design units can be elaborated (generate unroll, array instance processing, etc.) differently for each parameter/generic setting.

Another reason to copy instantiated modules/design units with "_default" name is in mixed language elaboration. Here a Verilog module may instantiate a VHDL entity which has been elaborated earlier with different generic values. In that case during Verilog elaboration we will not get original contents of instantiated entity.

Moreover, to support incremental elaboration we need to keep original modules/design units, as lower level units can be elaborated earlier.

In Verilog, we have a runtime-flag "veri_remove_suffix_default_from_copied_module_names" to rename modules from "<orig_name>_default" to "<orig_name>". This will work only when runtime-flag "veri_cleanup_base_modules" is set.

'''Q: What about interfaces with "_default" suffix in their names? Why? And what are they? '''

SystemVerilog interfaces can be used in any of the following ways :

* As interface instantiations.
* As interface ports.
* As virtual interfaces.
* As hierarchical names.

If an interface is used in a virtual interface declaration, interface instance, or port of a top-level module, the interface will be copied to '<interface_name>_default', even if none of its parameters are overwritten. This copied interface will be the one that is elaborated and specified in the virtual interface declaration, interface instance, or top-level module port. Every instantiated module containing interface type ports will also be copied during static elaboration since its interface port names may have been modified as well.

Virtual interfaces can appear in many different parts of a design, and may or may not be associated with interface instances. Virtual interfaces are not stored in Verific's pseudo-tree, so after static elaboration we do not know whether an interface is used as a virtual interface or not, or where it is being used. Without this knowledge, we cannot arbitrarily change all the references of an interface from '<interface_name>_default' to '<interface_name> because the references may become invalid. Because of this, we do not have flags to remove the '_default' from the interface names as we do for modules.

The '_default_<n>' suffix may also be added due to the presence of hierarchical references in an interface or bind statements containing interface instantiations.

Main Page

2023-10-23T15:36:38Z

Vince:

'''General'''
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
* [[Source code customization & Stable release services | Source code customization & Stable release services]]
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]
* [[Release version | How do I tell the version of a Verific software release? ]]
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
* [[LineFile data from input files | LineFile data from input files]]
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]
* [[Preserving user nets - preventing nets from being optimized away | Preserving user nets - preventing nets from being optimized away]]
* [[Python pretty-printer for gdb | Python pretty-printer for gdb]]

'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Port Expressions]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[Modules with '_1' '_2' suffix in their names | Verilog: After static elaboration, there are modules with "_1", "_2", ..., suffix in their names. Why?]]
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
* [[Notes on analysis | SystemVerilog: Notes on analysis]]
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units/interfaces with "_default" suffix in their names. Why? And what are they?]]
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
'''Netlist Database'''
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]
* [[System attributes | Netlist Database: System attributes]]

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''Scripting languages: TCL, Perl, Python'''
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]

'''Code examples'''
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]
* [[How to use RegisterPragmaRefCallBack() | Util/C++: How to use RegisterPragmaRefCallBack()]]
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
* [[Extract clock enable | Database/C++: Extract clock enable]]
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
* [[Finding hierarchical paths of a Netlist | Database/C++: Finding hierarchical paths of a Netlist]]
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
* [[Type Range example | Verilog/C++: Type Range example (simple)]]
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
* [[How to ignore certain modules while analyzing input RTL files | Verilog/C++: How to ignore certain modules while analyzing input RTL files]]
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
* [[In Verilog parsetree adding names to unnamed instances | Verilog/C++: In Verilog parsetree adding names to unnamed instances]]
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]
* [[Parse select modules only and ignore the rest | Verilog/C++: Parse select modules only and ignore the rest]]
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
* [[Evaluate 'for-generate' loop | Verilog/C++: Evaluate 'for-generate' loop]]
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
* [[Simple examples of VHDL visitor pattern | VHDL/C++: Simple examples of VHDL visitor pattern]]
* [[Traverse instances in parsetree | VHDL/C++: Traverse instances in parsetree]]
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]

Modules/design units with " default" suffix in their names

2023-10-23T15:29:19Z

Vince:

'''Q: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they? '''

Static elaboration process is a multiple-iteration process and modules/design units may be modified differently in each iteration.

We need to keep original version of modules/design units as they are immediately after analysis so that they can be copied for different parameter/generic settings in each iteration and body of copied modules/design units can be elaborated (generate unroll, array instance processing, etc.) differently for each parameter/generic setting.

Another reason to copy instantiated modules/design units with "_default" name is in mixed language elaboration. Here a Verilog module may instantiate a VHDL entity which has been elaborated earlier with different generic values. In that case during Verilog elaboration we will not get original contents of instantiated entity.

Moreover, to support incremental elaboration we need to keep original modules/design units, as lower level units can be elaborated earlier.

In Verilog, we have a runtime-flag "veri_remove_suffix_default_from_copied_module_names" to rename modules from "<orig_name>_default" to "<orig_name>". This will work only when runtime-flag "veri_cleanup_base_modules" is set.

'''Q: What about interfaces with "_default" suffix in their names? Why? And what are they? '''

Interfaces can be used in any of the following ways :

* As interface instantiations.
* As interface ports.
* As virtual interfaces.
* As hierarchical names.

If an interface is used in a virtual interface declaration, interface instance, or port of a top-level module, the interface will be copied to '<interface_name>_default', even if none of its parameters are overwritten. This copied interface will be the one that is elaborated and specified in the virtual interface declaration, interface instance, or top-level module port. Every instantiated module containing interface type ports will also be copied during static elaboration since its interface port names may have been modified as well.

Virtual interfaces can appear in many different parts of a design, and may or may not be associated with interface instances. Virtual interfaces are not stored in Verific's pseudo-tree, so after static elaboration we do not know whether an interface is used as a virtual interface or not, or where it is being used. Without this knowledge, we cannot arbitrarily change all the references of an interface from '<interface_name>_default' to '<interface_name> because the references may become invalid. Because of this, we do not have flags to remove the '_default' from the interface names as we do for modules.

The '_default_<n>' suffix may also be added due to the presence of hierarchical references in an interface or bind statements containing interface instantiations.

Instance - Module binding order

2023-04-19T18:04:10Z

Vince:

'''Q: Verilog has many ways to find modules not in the file being directly read: -L, -v, -y, .... There may be more than one module of the same name. What is the order of binding?'''

The order of searching for modules is:

# While parsing:
## `uselib
## -work (present working library)
## -L
## -y/-v (their order in an f-file is considered)
# While elaborating:
## configurations
## already resolved module from analysis, ie, order of parsing (above)

Compile-time/run-time flags

2023-03-03T03:31:58Z

Vince:

'''Q: Are there options to control Verific software's behavior?'''

There are compile-time flags and run-time flags ([https://www.verific.com/faq/index.php?title=Compile-time/run-time_flags Verific Runtime Flags]) to control Verific software's behavior.

When compile-time flags are changed, it will be necessary to rebuild the software for the flags to take effect. These flags reside in the following files:

database/DBCompileFlags.h
hdl_file_sort/HdlFileSortCompileFlags.h
synlib/SynlibCompileFlags.h
util/VerificSystem.h
verilog_nl/VeriNetlistCompileFlags.h
verilog/VeriCompileFlags.h
vhdl/VhdlCompileFlags.h

If the behavior of the software needs to be changed dynamically, this can be accomplished using run-time flags. With run-time flags, toggling of behavior can occur at any time without requiring re-compilation of the software. In most cases setting a flag to '1' will enable it and setting to '0' will disable it, although there are some flags that may take on other values, such as 'veri_loop_limit' = 10000, and 'db_record_naming_style' = "%s.%s". Run-time flags reside in the following files:

database/DBRuntimeFlags.h
edif/EdifRuntimeFlags.h
hier_tree/HierRuntimeFlags.h
pct/PCTRuntimeFlags.h
synlib/SynlibRuntimeFlags.h
upf/UpfRuntimeFlags.h
util/RuntimeFlags.cpp
verilog_nl/VeriNetlistRuntimeFlags.h
verilog/VeriRuntimeFlags.h
vhdl/VhdlRuntimeFlags.h

Note that depending on your Verific product configuration, you may or may not have all the files listed above. Also, most of the compile-time flags have an equivalent run-time flag to facilitate toggling of the desired behavior. For a full list of Verific's run-time flags with descriptions of their functionality, please refer to this page: [https://www.verific.com/docs/index.php?title=RuntimeFlags Verific Runtime Flags]

For C++, use the following APIs to control the run-time flags:
<nowiki>
RuntimeFlags::SetVar() - Set a run-time flag to a particular value (value is a non-negative integer or 0)
RuntimeFlags::GetVar() - Get the value of a run-time flag (for flags that return a non-negative integer or 0)
RuntimeFlags::SetStringVar() - Set a run-time flag to a particular string value
RuntimeFlags::GetStringVar() - Get the value of a run-time flag (for flags that return a string value)
</nowiki>

Below are examples on how to call these APIs:
<nowiki>
RuntimeFlags::SetVar("veri_preserve_comments", 1) ; // enable flag 'veri_preserve_comments'
RuntimeFlags::GetVar("veri_preserve_comments") ; // retrieve the value of 'veri_preserve_comments'
RuntimeFlags::SetStringVar("db_interface_modport_field_separator", "_") ; // set "db_interface_modport_field_separator" to be "_"
RuntimeFlags::GetStringVar("db_array_naming_style") ; // retrieve the value of 'db_array_naming_style'
</nowiki>

For Tcl scripting, use the following commands to control the run-time flags:
<nowiki>
set_runtime_flag - Set a run-time flag to a particular value
get_runtime_flag - Get the value of a run-time flag
</nowiki>

Below are examples on how to call these commands:
<nowiki>
set_runtime_flag "db_array_naming_style" "%s\[%d\]"
get_runtime_flag "veri_preserve_comments"
</nowiki>

Compile-time/run-time flags

2023-03-03T03:19:09Z

Vince:

'''Q: Are there options to control Verific software's behavior?'''

There are compile-time flags and run-time flags to control Verific software's behavior.

When compile-time flags are changed, it will be necessary to rebuild the software for the flags to take effect. These flags reside in the following files:

database/DBCompileFlags.h
hdl_file_sort/HdlFileSortCompileFlags.h
synlib/SynlibCompileFlags.h
util/VerificSystem.h
verilog_nl/VeriNetlistCompileFlags.h
verilog/VeriCompileFlags.h
vhdl/VhdlCompileFlags.h

If the behavior of the software needs to be changed dynamically, this can be accomplished using run-time flags. With run-time flags, toggling of behavior can occur at any time without requiring re-compilation of the software. In most cases setting a flag to '1' will enable it and setting to '0' will disable it, although there are some flags that may take on other values, such as 'veri_loop_limit' = 10000, and 'db_record_naming_style' = "%s.%s". Run-time flags reside in the following files:

database/DBRuntimeFlags.h
edif/EdifRuntimeFlags.h
hier_tree/HierRuntimeFlags.h
pct/PCTRuntimeFlags.h
synlib/SynlibRuntimeFlags.h
upf/UpfRuntimeFlags.h
util/RuntimeFlags.cpp
verilog_nl/VeriNetlistRuntimeFlags.h
verilog/VeriRuntimeFlags.h
vhdl/VhdlRuntimeFlags.h

Note that depending on your Verific product configuration, you may or may not have all the files listed above. Also, most of the compile-time flags have an equivalent run-time flag to facilitate toggling of the desired behavior. For a full list of Verific's run-time flags with descriptions of their functionality, please refer to this page: [https://www.verific.com/docs/index.php?title=RuntimeFlags Verific Runtime Flags]

For C++, use the following APIs to control the run-time flags:
<nowiki>
RuntimeFlags::SetVar() - Set a run-time flag to a particular value (value is a non-negative integer or 0)
RuntimeFlags::GetVar() - Get the value of a run-time flag (for flags that return a non-negative integer or 0)
RuntimeFlags::SetStringVar() - Set a run-time flag to a particular string value
RuntimeFlags::GetStringVar() - Get the value of a run-time flag (for flags that return a string value)
</nowiki>

Below are examples on how to call these APIs:
<nowiki>
RuntimeFlags::SetVar("veri_preserve_comments", 1) ; // enable flag 'veri_preserve_comments'
RuntimeFlags::GetVar("veri_preserve_comments") ; // retrieve the value of 'veri_preserve_comments'
RuntimeFlags::SetStringVar("db_interface_modport_field_separator", "_") ; // set "db_interface_modport_field_separator" to be "_"
RuntimeFlags::GetStringVar("db_array_naming_style") ; // retrieve the value of 'db_array_naming_style'
</nowiki>

For Tcl scripting, use the following commands to control the run-time flags:
<nowiki>
set_runtime_flag - Set a run-time flag to a particular value
get_runtime_flag - Get the value of a run-time flag
</nowiki>

Below are examples on how to call these commands:
<nowiki>
set_runtime_flag "db_array_naming_style" "%s\[%d\]"
get_runtime_flag "veri_preserve_comments"
</nowiki>

Compile-time/run-time flags

2023-03-03T03:11:49Z

Vince:

'''Q: Are there options to control Verific software's behavior?'''

There are compile-time flags and run-time flags to control Verific software's behavior.

When compile-time flags are changed, it will be necessary to rebuild the software for the flags to take effect. These flags reside in the following files:

database/DBCompileFlags.h
hdl_file_sort/HdlFileSortCompileFlags.h
synlib/SynlibCompileFlags.h
util/VerificSystem.h
verilog_nl/VeriNetlistCompileFlags.h
verilog/VeriCompileFlags.h
vhdl/VhdlCompileFlags.h

If the behavior of the software needs to be changed dynamically, this can be accomplished using run-time flags. With run-time flags, toggling of behavior can occur at any time without requiring re-compilation of the software. In most cases setting a flag to '1' will enable it and setting to '0' will disable it, although there are some flags that may take on other values, such as 'veri_loop_limit' = 10000, and 'db_record_naming_style' = "%s.%s". Run-time flags reside in the following files:

database/DBRuntimeFlags.h
edif/EdifRuntimeFlags.h
hier_tree/HierRuntimeFlags.h
pct/PCTRuntimeFlags.h
synlib/SynlibRuntimeFlags.h
upf/UpfRuntimeFlags.h
util/RuntimeFlags.cpp
verilog_nl/VeriNetlistRuntimeFlags.h
verilog/VeriRuntimeFlags.h
vhdl/VhdlRuntimeFlags.h

Note that depending on your Verific product configuration, you may or may not have all the files listed above. Also, most of the compile-time flags have an equivalent run-time flag to facilitate toggling of the desired behavior. For a full list of Verific's run-time flags with descriptions of their functionality, please refer to this page: [https://www.verific.com/docs/index.php?title=RuntimeFlags Verific Runtime Flags]

For C++, use the following APIs to control the run-time flags:
<nowiki>
RuntimeFlags::SetVar() - Set a run-time flag to a particular value (value is a non-negative integer or 0)
RuntimeFlags::GetVar() - Get the value of a run-time flag (for flags that return a non-negative integer or 0)
RuntimeFlags::SetStringVar() - Set a run-time flag to a particular string value
RuntimeFlags::GetStringVar() - Get the value of a run-time flag (for flags that return a string value)
</nowiki>

Below are some examples on how to call these APIs:
<nowiki>
RuntimeFlags::SetVar("veri_preserve_comments", 1) ; // enable flag 'veri_preserve_comments'
RuntimeFlags::GetVar("veri_preserve_comments") ; // retrieve the value of 'veri_preserve_comments'
RuntimeFlags::SetStringVar("db_interface_modport_field_separator", "_") ; // set "db_interface_modport_field_separator" to be "_"
RuntimeFlags::GetStringVar("db_array_naming_style") ; // retrieve the value of 'db_array_naming_style'
</nowiki>

For Tcl scripting, use the following commands to control the run-time flags:
<nowiki>
set_runtime_flag - Set a run-time flag to a particular value
get_runtime_flag - Get the value of a run-time flag
</nowiki>

Below are some examples on how to call these commands:
<nowiki>
set_runtime_flag "db_array_naming_style" "%s\[%d\]"
get_runtime_flag "veri_preserve_comments"
</nowiki>

Compile-time/run-time flags

2023-03-03T03:05:28Z

Vince:

'''Q: Are there options to control Verific software's behavior?'''

There are compile-time flags and run-time flags to control Verific software's behavior.

When compile-time flags are changed, it will be necessary to rebuild the software for the flags to take effect. These flags reside in the following files:

database/DBCompileFlags.h
hdl_file_sort/HdlFileSortCompileFlags.h
synlib/SynlibCompileFlags.h
util/VerificSystem.h
verilog_nl/VeriNetlistCompileFlags.h
verilog/VeriCompileFlags.h
vhdl/VhdlCompileFlags.h

If the behavior of the software needs to be changed dynamically, this can be accomplished using run-time flags. With run-time flags, toggling of behavior can occur at any time without requiring re-compilation of the software. In most cases setting a flag to '1' will enable it and setting to '0' will disable it, although there are some flags that may take on other values, such as 'veri_loop_limit' = 10000, and 'db_record_naming_style' = "%s.%s". Run-time flags reside in the following files:

database/DBRuntimeFlags.h
edif/EdifRuntimeFlags.h
hier_tree/HierRuntimeFlags.h
pct/PCTRuntimeFlags.h
synlib/SynlibRuntimeFlags.h
upf/UpfRuntimeFlags.h
util/RuntimeFlags.cpp
verilog_nl/VeriNetlistRuntimeFlags.h
verilog/VeriRuntimeFlags.h
vhdl/VhdlRuntimeFlags.h

Note that depending on your Verific product configuration, you may or may not have all the files listed above. Also, most of the compile-time flags have an equivalent run-time flag to facilitate toggling of the desired behavior. For a full list of Verific's run-time flags with descriptions of their functionality, please refer to this page: [https://www.verific.com/docs/index.php?title=RuntimeFlags Verific Runtime Flags]

For C++, use the following APIs to control the run-time flags:
<nowiki>
RuntimeFlags::SetVar() - Set a run-time flag to a particular value (value is a non-negative integer or 0)
RuntimeFlags::GetVar() - Get the value of a run-time flag (for flags that return a non-negative integer or 0)
RuntimeFlags::SetStringVar() - Set a run-time flag to a particular string value
RuntimeFlags::GetStringVar() - Get the value of a run-time flag (for flags that return a string value)
</nowiki>

Below are some examples on how to call these APIs:
<nowiki>
RuntimeFlags::SetVar("veri_preserve_comments", 1) ; // enable flag 'veri_preserve_comments'
RuntimeFlags::GetVar("veri_preserve_comments") ; // retrieve the value of 'veri_preserve_comments'
RuntimeFlags::SetStringVar("db_interface_modport_field_separator", "_") ; // set "db_interface_modport_field_separator" to be "_"
RuntimeFlags::GetStringVar("db_array_naming_style") ; // retrieve the value of 'db_array_naming_style'
</nowiki>

For Tcl scripting, use the following commands to control the run-time flags:
<nowiki>
set_runtime_flag - Set a run-time flag to a particular value
get_runtime_flag - Get the value of a run-time flag
</nowiki>

Below are some examples on how to call these commands:
<nowiki>
set_runtime_flag "db_array_naming_style" "%s\[%d\]"
get_runtime_flag "veri_preserve_comments"
</nowiki>

How to ignore parameters/generics in elaboration

2023-02-17T18:14:08Z

Vince:

'''Q:Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?'''

Specific parameters/generics of specific modules/units can be ignored during elaboration. Related APIs are:

vhdl_file::GetIgnoreGeneric()
vhdl_file::SetIgnoreGeneric()
vhdl_file::RemoveAllIgnoreGeneric()

veri_file::GetIgnoreParameter()
veri_file::SetIgnoreParameter()
veri_file::RemoveAllIgnoreParameter()

Below is an example as how to ignore all parameters in a library:

<nowiki>
veri_file::AnalyzeMultipleFiles(veri_files, veri_file::SYSTEM_VERILOG, "work", veri_file::MFCU);

/*** Go through library "work" in the parsetree,
find all parameters,
and set "ignored" on all of them.
Or you can select the parameters to ignore ***/
MapIter mi;
VeriModule *module ;
VeriLibrary *work_lib = veri_file::GetLibrary("work", 1);

FOREACH_VERILOG_MODULE_IN_LIBRARY (work_lib, mi, module) { // do this for each module
if (!module) continue;
Array *parameters = module->GetParameters(); // collect all parameters
if (!parameters) continue;
unsigned i;
VeriIdDef *param_id;
FOREACH_ARRAY_ITEM(parameters, i, param_id) { // do this for each parameter of the module
if (!param_id) continue;
veri_file::SetIgnoreParameter(work_lib->GetName(), module->Name(), param_id->Name());
}
}

if (!veri_file::Elaborate("top", "work", 0)) {
return 1 ;
}
</nowiki>

Pretty-print a module and the packages imported by the module

2022-09-23T00:08:11Z

Vince:

C++:
<nowiki>
#include <iostream>
#include <fstream>

#include "veri_file.h"
#include "VeriModule.h"
#include "VeriId.h"
#include "VeriScope.h"

#include "Map.h"

using namespace std ;

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main(int argc, const char **argv)
{
const char *file = (argc > 1) ? argv[1] : "test.sv" ;

// Analyze the files (AnalyzeMultipleFiles API is the recommended one):
Array files(1) ;
files.InsertLast(file) ;
if (!veri_file::AnalyzeMultipleFiles(&files, veri_file::SYSTEM_VERILOG)) return 1 ;

MapIter mi ;
VeriModule *module ;
FOREACH_VERILOG_MODULE(mi, module){
if (!module) continue ;
if (module->IsPackage()) continue ; // no need to dive into package

// Get the scope of the module:
VeriScope *scope = module->GetScope() ;

char *outputfilename = Strings::save(module->Name(), "_pp_out.v");
std::ofstream f(outputfilename, std::ios::out) ;

// Get the scope that this module/scope is using:
// This also includes the compilation unit in the list, if any/required:
Set *using_scopes = (scope) ? scope->GetUsing() : 0 ;

// Print all those scopes/modules before printing the module itself:
SetIter si ;
VeriScope *using_scope ;
FOREACH_SET_ITEM(using_scopes, si, &using_scope) {
VeriIdDef *mod_id = using_scope->GetContainingModule() ;
VeriModule *mod = (mod_id) ? mod_id->GetModule() : 0 ;
if (!mod) continue ;
if (mod->IsPackage()) {
std::cout << ">>> Module '" << module->Name() << "' uses package '" << mod->Name() << "' <<<\n";
}
f << "// Printing package " << mod->Name() << endl ;
mod->PrettyPrint(f, 0) ;
}

// Now print the module:
f << "// Printing module " << module->Name() << endl ;
module->PrettyPrint(f, 0) ;
f.close() ;
}

return 0 ;
}
</nowiki>

Input Verilog:
<nowiki>
package PKG1 ;
typedef int my_int ;
endpackage

typedef byte my_byte ;

module test ;
import PKG1::* ;
my_int int1 ;
my_byte byte1 ;
endmodule
</nowiki>

Pretty-printed output:
<nowiki>
// Printing package PKG1

package PKG1 ;
typedef int my_int ;
endpackage

// Printing package $unit_test_sv

typedef byte my_byte ;

// Printing module test

module test ;
import PKG1:: * ;
my_int int1 ;
my_byte byte1 ;
endmodule
</nowiki>

Python pretty-printer for gdb

2022-09-13T18:28:27Z

Vince:

If gdb (GNU debugger) was compiled with Python support, it is possible to run Python scripts from within gdb. Below is an example of how to create a custom pretty-printer for Verific's VeriTreeNode using gdb's Python interface.

The Python script itself looks like this
<nowiki>
import gdb
import re

class VeriVhdlTreeNodePrinter:
def __init__(self, val):
self.val = val

def to_string(self):
eval_string = f"(({self.val.type.name}*){self.val.address})->GetPrettyPrintedString()"
return gdb.parse_and_eval(eval_string).string()

def verific_pp_func(val):
lookup_tag = val.type.tag
if lookup_tag is None:
return None

regex = re.compile("^(Verific::)?(Veri|Vhdl)(\w)+$")
if regex.match(lookup_tag):
return VeriVhdlTreeNodePrinter(val)
return None

gdb.pretty_printers.append(verific_pp_func)
</nowiki>
To automate sourcing of the Python script on gdb startup, add the following line to your ~/.gdbinit :

source ~/verific_pp.py

The script calls Verific's GetPrettyPrintedString() API which essentially pretty prints the VeriTreeNode. It takes an object and not a pointer. Printing the pointer will still print the value of the pointer as per usual gdb behavior.

Note that if a class has a name starting with Veri but is not derived from VeriTreeNode, gdb produces the following message :

(gdb) print *pointer_to_VeriLibrary_which_is_not_derived_from_VeriTreeNode
$2 = Python Exception <class 'gdb.error'> Couldn't find method VeriLibrary::GetPrettyPrintedString:
(gdb)

The same will happen for VeriValue/VhdlValue/VeriBaseValue, etc, because these classes do not have the GetPrettyPrintedString() API. The pretty printer can be customized to exclude such classes, or modified to handle these other cases. This is just a regular regex rule.

Here is the output from an example run :
<nowiki>
gdb ./test-linux-g
Reading symbols from test-linux-g...
(gdb) break 62
Breakpoint 1 at 0x306b50: file test.cpp, line 62.
(gdb) run
Starting program: test-linux-g
[Thread debugging using libthread_db enabled]
Using host libthread_db library "/lib/x86_64-linux-gnu/libthread_db.so.1".
-- Analyzing Verilog file 'test.v' (VERI-1482)
test.v(1): INFO: compiling module 'top' (VERI-1018)
-- module: top
-- param: P1
-- initial expression: 8

Breakpoint 1, main (argc=1, argv=0x7fffffffe0b8) at test.cpp:62
62 Message::PrintLine(" initial value: ", Strings::itoa(int_val)) ;
(gdb) p *module_item
$1 = {<Verific::VeriTreeNode> = {<Verific::VeriNode> = {
_vptr.VeriNode = 0x5555565bcd18 <vtable for Verific::VeriDataDecl+16>, static _present_scope = 0x0,
static _container_scope_arr = 0x0, static _sva_clock_expr = 0x0, static _default_clock = 0x0,
static _default_disable_iff_cond = 0x0, static _has_disable_iff = 0, static _id_ref = 0x0,
static _name_list = 0x0, static _inside_clocked_sequence = 0, static _contains_event_control = 0,
static _contains_delay_control = 0, static _contains_even_id_in_body = 0, static _multiple_inferred_clock = 0,
static _in_property_expr = 0, static _in_checker = 0, static _in_fork_join_none_or_any = 0,
static _in_bind_directive = 0, static _hier_name_to_allow_mod_name = 0, static _do_not_recurse_packed_dims = 0,
static _processing_param = 0x0, static _processing_expr = 0x0, static _msgs = 0x55555666b870,
static _relaxed_msgs = 0x0, static _udp_edge_chars = 0x0, static _verilog_keywords = 0x0,
static _verilog_tokens = 0x0, static _system_tasks = 0x0, static _ref_count_map = 0x0,
static _attribute_map = 0x0, static _map_of_comment_arr = 0x0, static _global_clocking = 0x0,
static _var_usage_running = 0, static _is_static_elab = 0, static _is_rtl_elab = 0,
static _func_pointer_stack = 0x0, static _func_stack = 0x0, static _mutual_recursion_count = 0,
static _max_mutual_recursion_count = 0, static _within_seq_area = 0, static _within_generate_endgenerate = 0,
static _under_default_clock = 0, static _default_disable_defined = 0, static _has_delay_or_event_control = 0,
static _processing_operand = 0, static _potential_always_loop = 0, static _reresolve_idrefs = 0,
static _ignore_ams_in_rtl_elab = 0, static _follow_lrm_for_constant_func = 0, static _evaluated_vals = 0x0,
static _evaluated_constraints = 0x0, static _p_evaluated_vals = 0x0, static _p_evaluated_constraints = 0x0,
static _unnamedscope_vs_decl_ids = 0x0, static _check_linefile_of_import = 1}, _linefile = 8589934594},
_qualifiers = 0}
(gdb) p *val
$2 = {_vptr.VeriBaseValue = 0x55555654b280 <vtable for Verific::VeriInteger+16>}
(gdb) source verific_pp.py
(gdb) p *module_item
$3 = parameter P1 = 8 ;

(gdb) p *val
$4 = 8
(gdb)
</nowiki>
Notice how before activating the Python pretty-printer, gdb prints out a lot of information when calling 'p *module_item' or 'p *val' . With the pretty-printer, it now prints only the value from GetPrettyPrintedString().

Python pretty-printer for gdb

2022-09-13T18:10:28Z

Vince:

If gdb (GNU debugger) was compiled with Python support, it is possible to run Python scripts from within gdb. Below is an example of how to create a custom pretty-printer for Verific's VeriTreeNode using gdb's Python interface.

The Python script itself looks like this
<nowiki>
import gdb
import re

class VeriVhdlTreeNodePrinter:
def __init__(self, val):
self.val = val

def to_string(self):
eval_string = f"(({self.val.type.name}*){self.val.address})->GetPrettyPrintedString()"
return gdb.parse_and_eval(eval_string).string()

def verific_pp_func(val):
lookup_tag = val.type.tag
if lookup_tag is None:
return None

regex = re.compile("^(Verific::)?(Veri|Vhdl)(\w)+$")
if regex.match(lookup_tag):
return VeriVhdlTreeNodePrinter(val)
return None

gdb.pretty_printers.append(verific_pp_func)
</nowiki>
To automate sourcing of the Python script on gdb startup, add the following line to your ~/.gdbinit :

source ~/verific_pp.py

The script calls Verific's GetPrettyPrintedString() API which essentially pretty prints the VeriTreeNode. It takes an object and not a pointer. Printing the pointer will still print the value of the pointer as per usual gdb behavior.

Note that if a class has a name starting with Veri but is not derived from VeriTreeNode, gdb produces the following message :

(gdb) print *pointer_to_VeriLibrary_which_is_not_derived_from_VeriTreeNode
$2 = Python Exception <class 'gdb.error'> Couldn't find method VeriLibrary::GetPrettyPrintedString:
(gdb)

The same will happen for VeriValue/VhdlValue/VeriBaseValue, etc, because these classes do not have the GetPrettyPrintedString() API. The pretty printer can be customized to exclude such classes, or modified to handle these other cases. This is just a regular regex rule.

Here is the output from an example run :
<nowiki>
gdb ./test-linux-g
Reading symbols from test-linux-g...
(gdb) break 62
Breakpoint 1 at 0x306b50: file test.cpp, line 62.
(gdb) run
Starting program: test-linux-g
[Thread debugging using libthread_db enabled]
Using host libthread_db library "/lib/x86_64-linux-gnu/libthread_db.so.1".
-- Analyzing Verilog file 'test.v' (VERI-1482)
test.v(1): INFO: compiling module 'top' (VERI-1018)
-- module: top
-- param: P1
-- initial expression: 8

Breakpoint 1, main (argc=1, argv=0x7fffffffe0b8) at test.cpp:62
62 Message::PrintLine(" initial value: ", Strings::itoa(int_val)) ;
(gdb) '''p *module_item'''
$1 = {<Verific::VeriTreeNode> = {<Verific::VeriNode> = {
_vptr.VeriNode = 0x5555565bcd18 <vtable for Verific::VeriDataDecl+16>, static _present_scope = 0x0,
static _container_scope_arr = 0x0, static _sva_clock_expr = 0x0, static _default_clock = 0x0,
static _default_disable_iff_cond = 0x0, static _has_disable_iff = 0, static _id_ref = 0x0,
static _name_list = 0x0, static _inside_clocked_sequence = 0, static _contains_event_control = 0,
static _contains_delay_control = 0, static _contains_even_id_in_body = 0, static _multiple_inferred_clock = 0,
static _in_property_expr = 0, static _in_checker = 0, static _in_fork_join_none_or_any = 0,
static _in_bind_directive = 0, static _hier_name_to_allow_mod_name = 0, static _do_not_recurse_packed_dims = 0,
static _processing_param = 0x0, static _processing_expr = 0x0, static _msgs = 0x55555666b870,
static _relaxed_msgs = 0x0, static _udp_edge_chars = 0x0, static _verilog_keywords = 0x0,
static _verilog_tokens = 0x0, static _system_tasks = 0x0, static _ref_count_map = 0x0,
static _attribute_map = 0x0, static _map_of_comment_arr = 0x0, static _global_clocking = 0x0,
static _var_usage_running = 0, static _is_static_elab = 0, static _is_rtl_elab = 0,
static _func_pointer_stack = 0x0, static _func_stack = 0x0, static _mutual_recursion_count = 0,
static _max_mutual_recursion_count = 0, static _within_seq_area = 0, static _within_generate_endgenerate = 0,
static _under_default_clock = 0, static _default_disable_defined = 0, static _has_delay_or_event_control = 0,
static _processing_operand = 0, static _potential_always_loop = 0, static _reresolve_idrefs = 0,
static _ignore_ams_in_rtl_elab = 0, static _follow_lrm_for_constant_func = 0, static _evaluated_vals = 0x0,
static _evaluated_constraints = 0x0, static _p_evaluated_vals = 0x0, static _p_evaluated_constraints = 0x0,
static _unnamedscope_vs_decl_ids = 0x0, static _check_linefile_of_import = 1}, _linefile = 8589934594},
_qualifiers = 0}
(gdb) '''p *val'''
$2 = {_vptr.VeriBaseValue = 0x55555654b280 <vtable for Verific::VeriInteger+16>}
(gdb) '''source verific_pp.py'''
(gdb) '''p *module_item'''
$3 = parameter P1 = 8 ;

(gdb) '''p *val'''
$4 = 8
(gdb)
</nowiki>
Notice how before activating the Python pretty-printer, gdb prints out a lot of information when calling 'p *module_item' or 'p *val' . With the pretty-printer, it now prints only the value from GetPrettyPrintedString().

Python pretty-printer for gdb

2022-09-13T18:06:21Z

Vince: Created page with "If gdb (GNU debugger) was compiled with Python support, it is possible to run Python scripts within gdb. Below is an example of how to create a custom pretty-printer for Veri..."

If gdb (GNU debugger) was compiled with Python support, it is possible to run Python scripts within gdb. Below is an example of how to create a custom pretty-printer for Verific's parse tree nodes.

The Python script itself looks like this
<nowiki>
import gdb
import re

class VeriVhdlTreeNodePrinter:
def __init__(self, val):
self.val = val

def to_string(self):
eval_string = f"(({self.val.type.name}*){self.val.address})->GetPrettyPrintedString()"
return gdb.parse_and_eval(eval_string).string()

def verific_pp_func(val):
lookup_tag = val.type.tag
if lookup_tag is None:
return None

regex = re.compile("^(Verific::)?(Veri|Vhdl)(\w)+$")
if regex.match(lookup_tag):
return VeriVhdlTreeNodePrinter(val)
return None

gdb.pretty_printers.append(verific_pp_func)
</nowiki>
To automate sourcing of the Python script on gdb startup, add the following line to your ~/.gdbinit :

source ~/verific_pp.py

The script calls Verific's GetPrettyPrintedString() API which essentially pretty prints the VeriTreeNode. It takes an object and not a pointer. Printing the pointer will still print the value of the pointer as per usual gdb behavior.

Note that if a class has a name starting with Veri but is not derived from VeriTreeNode, gdb produces the following message :

(gdb) print *pointer_to_VeriLibrary_which_is_not_derived_from_VeriTreeNode
$2 = Python Exception <class 'gdb.error'> Couldn't find method VeriLibrary::GetPrettyPrintedString:
(gdb)

The same will happen for VeriValue/VhdlValue/VeriBaseValue, etc, because these classes do not have the GetPrettyPrintedString() API. The pretty printer can be customized to exclude such classes, or modified to handle these other cases. This is just a regular regex rule.

Here is the output from an example run :
<nowiki>
gdb ./test-linux-g
Reading symbols from test-linux-g...
(gdb) break 62
Breakpoint 1 at 0x306b50: file test.cpp, line 62.
(gdb) run
Starting program: test-linux-g
[Thread debugging using libthread_db enabled]
Using host libthread_db library "/lib/x86_64-linux-gnu/libthread_db.so.1".
-- Analyzing Verilog file 'test.v' (VERI-1482)
test.v(1): INFO: compiling module 'top' (VERI-1018)
-- module: top
-- param: P1
-- initial expression: 8

Breakpoint 1, main (argc=1, argv=0x7fffffffe0b8) at test.cpp:62
62 Message::PrintLine(" initial value: ", Strings::itoa(int_val)) ;
(gdb) '''p *module_item'''
$1 = {<Verific::VeriTreeNode> = {<Verific::VeriNode> = {
_vptr.VeriNode = 0x5555565bcd18 <vtable for Verific::VeriDataDecl+16>, static _present_scope = 0x0,
static _container_scope_arr = 0x0, static _sva_clock_expr = 0x0, static _default_clock = 0x0,
static _default_disable_iff_cond = 0x0, static _has_disable_iff = 0, static _id_ref = 0x0,
static _name_list = 0x0, static _inside_clocked_sequence = 0, static _contains_event_control = 0,
static _contains_delay_control = 0, static _contains_even_id_in_body = 0, static _multiple_inferred_clock = 0,
static _in_property_expr = 0, static _in_checker = 0, static _in_fork_join_none_or_any = 0,
static _in_bind_directive = 0, static _hier_name_to_allow_mod_name = 0, static _do_not_recurse_packed_dims = 0,
static _processing_param = 0x0, static _processing_expr = 0x0, static _msgs = 0x55555666b870,
static _relaxed_msgs = 0x0, static _udp_edge_chars = 0x0, static _verilog_keywords = 0x0,
static _verilog_tokens = 0x0, static _system_tasks = 0x0, static _ref_count_map = 0x0,
static _attribute_map = 0x0, static _map_of_comment_arr = 0x0, static _global_clocking = 0x0,
static _var_usage_running = 0, static _is_static_elab = 0, static _is_rtl_elab = 0,
static _func_pointer_stack = 0x0, static _func_stack = 0x0, static _mutual_recursion_count = 0,
static _max_mutual_recursion_count = 0, static _within_seq_area = 0, static _within_generate_endgenerate = 0,
static _under_default_clock = 0, static _default_disable_defined = 0, static _has_delay_or_event_control = 0,
static _processing_operand = 0, static _potential_always_loop = 0, static _reresolve_idrefs = 0,
static _ignore_ams_in_rtl_elab = 0, static _follow_lrm_for_constant_func = 0, static _evaluated_vals = 0x0,
static _evaluated_constraints = 0x0, static _p_evaluated_vals = 0x0, static _p_evaluated_constraints = 0x0,
static _unnamedscope_vs_decl_ids = 0x0, static _check_linefile_of_import = 1}, _linefile = 8589934594},
_qualifiers = 0}
(gdb) '''p *val'''
$2 = {_vptr.VeriBaseValue = 0x55555654b280 <vtable for Verific::VeriInteger+16>}
(gdb) '''source verific_pp.py'''
(gdb) '''p *module_item'''
$3 = parameter P1 = 8 ;

(gdb) '''p *val'''
$4 = 8
(gdb)
</nowiki>
Notice how before activating the Python pretty-printer, gdb prints out a lot of information when calling 'p *module_item' or 'p *val' . With the pretty-printer, it now prints only the value from GetPrettyPrintedString().

Main Page

2022-09-13T17:46:17Z

Vince:

'''General'''
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
* [[Source code customization & Stable release services | Source code customization & Stable release services]]
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]
* [[Release version | How do I tell the version of a Verific software release? ]]
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
* [[LineFile data from input files | LineFile data from input files]]
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]
* [[Preserving user nets - preventing nets from being optimized away | Preserving user nets - preventing nets from being optimized away]]
* [[Python pretty-printer for gdb | Python pretty-printer for gdb]]

'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
* [[Notes on analysis | SystemVerilog: Notes on analysis]]
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]]
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]

* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
'''Netlist Database'''
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]
* [[System attributes | Netlist Database: System attributes]]

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''Scripting languages: TCL, Perl, Python'''
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]

'''Code examples'''
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
* [[Extract clock enable | Database/C++: Extract clock enable]]
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
* [[Type Range example | Verilog/C++: Type Range example (simple)]]
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
* [[How to ignore certain modules while analyzing input RTL files | Verilog/C++: How to ignore certain modules while analyzing input RTL files]]
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]
* [[Parse select modules only and ignore the rest | Verilog/C++: Parse select modules only and ignore the rest]]
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
* [[Simple examples of VHDL visitor pattern | VHDL/C++: Simple examples of VHDL visitor pattern]]
* [[Traverse instances in parsetree | VHDL/C++: Traverse instances in parsetree]]
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]

How to get packed dimensions of enum

2022-05-12T00:46:26Z

Vince:

C++:
<nowiki>
#include "Array.h"
#include "Map.h"
#include "Set.h"
#include "Message.h"
#include "veri_file.h"
#include "VeriModule.h"
#include "VeriScope.h"
#include "VeriId.h"
#include "VeriExpression.h"
#include "veri_file.h"
#include <iostream>

using namespace std;
#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

void GetBaseTypeFromDataType(VeriDataType *);

int main(int argc, char **argv)
{
veri_file::SetInterfaceModportFieldSeparator("::") ;

Array file_names;

if (argc < 2) {
file_names.InsertLast("test.v");
} else {
for (int i = 1; i < argc; i++) {
file_names.InsertLast(argv[i]);
}
}

Array * file_names_ = new Array( file_names);

if (!veri_file::AnalyzeMultipleFiles(file_names_, veri_file::SYSTEM_VERILOG, "work", veri_file::MFCU)) {
std::cout << " Unable to analyze multiple files. Aborting\n";
return 1 ;
}

// Fetching the top module
Array *top_module_array = veri_file::GetTopModules() ;

if (!top_module_array) {
Message::Error(0, "Cannot find any top module in the design") ;
return 4;
}

VeriModule *module = (VeriModule *) top_module_array->GetFirst();

// Creating VPT
module->StaticElaborate( 0);
module->Elaborate( 0, 0, false);

VeriScope* p_scope = module->GetScope();
Map* scope_map = p_scope->GetThisScope();
MapIter mi ;
VeriIdDef *id;

FOREACH_MAP_ITEM(scope_map, mi, 0, &id) {
if (!id ) continue;
std::cout << "Handling Declaration: "<< id->Name() << std::endl;
GetBaseTypeFromDataType(id->GetDataType());
}

return 0;
}

void GetBaseTypeFromDataType(VeriDataType *p_data_type)
{
if(!p_data_type) {
return;
}
unsigned packed_dim = p_data_type->PackedDimension();
switch( p_data_type->GetClassId() ) {
case ID_VERIDATATYPE: {
std::cout << "===== ID_VERIDATATYPE:: p_data_type->Image() = " << p_data_type->Image() << " =====" << std::endl;
std::cout << "===== ID_VERIDATATYPE:: packed_dim = " << packed_dim << std::endl;
if ( packed_dim != 0 ) {
VeriRange const* range = dynamic_cast<VeriRange const*>
(p_data_type->GetDimensions());
VeriRange const* last_dim_range = NULL;
do {
last_dim_range = range;
} while ( range && (range = range->GetNext()) );
if ( last_dim_range && last_dim_range->GetLeft() && last_dim_range->GetRight() ) {
std::cout << "packed_dim->Left = " << last_dim_range->GetLeft()->GetPrettyPrintedString() << std::endl;
std::cout << "packed_dim->Right = " << last_dim_range->GetRight()->GetPrettyPrintedString() << std::endl;
}
}
break;
}
case ID_VERINETDATATYPE:
break;
case ID_VERISTRUCTUNION: {
std::cout << "===== ID_VERISTRUCTUNION:: p_data_type->Image() = " << p_data_type->Image() << " =====" << std::endl;
unsigned i;
Array *decls = p_data_type->GetDecls() ;
VeriDataDecl *decl;
FOREACH_ARRAY_ITEM (decls, i, decl) {
//std::cout << "===== ===== decl " << i << ": " << decl->GetPrettyPrintedString() << std::endl;
VeriDataType *datatype = decl->GetDataType();
(void) GetBaseTypeFromDataType(datatype);
}
break;
}
case ID_VERIENUM : {
std::cout << "===== ID_VERIENUM:: p_data_type->Image() = " << p_data_type->Image() << " =====" << std::endl;
std::cout << "===== ID_VERIENUM:: packed_dim = " << packed_dim << std::endl;
if ( packed_dim != 0 ) {
VeriRange const* range = dynamic_cast<VeriRange const*>
(p_data_type->GetDimensions());
VeriRange const* last_dim_range = NULL;
do {
last_dim_range = range;
} while ( range && (range = range->GetNext()) );

if ( last_dim_range && last_dim_range->GetLeft() && last_dim_range->GetRight() ) {
std::cout << "packed_dim->Left = " << last_dim_range->GetLeft()->GetPrettyPrintedString() << std::endl;
std::cout << "packed_dim->Right = " << last_dim_range->GetRight()->GetPrettyPrintedString() << std::endl;
}
}
VeriEnum* p_enum = dynamic_cast<VeriEnum*>(p_data_type);
VeriDataType* p_base_type = p_enum->GetBaseType();
GetBaseTypeFromDataType (p_base_type);
break;
}
case ID_VERITYPEREF: {
std::cout << "===== ID_VERITYPEREF:: p_data_type->Image() = " << p_data_type->Image() << " =====" << std::endl;
std::cout << "===== ID_VERITYPEREF:: packed_dim = " << packed_dim << std::endl;
GetBaseTypeFromDataType(p_data_type->GetBaseDataType());
break;
}
default:
break;
}
}
</nowiki>

Input Verilog:
<nowiki>
typedef enum bit {a, b} [1:0] data_ctrl_t;

module test (output data_ctrl_t out1 );
struct packed {
logic [7:0] high;
logic [3:0] low;
} word1;
assign out1 = b ;
endmodule
</nowiki>

Run:
<nowiki>
-- Analyzing Verilog file 'test.v' (VERI-1482)
test.v(3): INFO: compiling module 'test' (VERI-1018)
test.v(3): INFO: compiling module 'test' (VERI-1018)
Handling Declaration: out1
===== ID_VERITYPEREF:: p_data_type->Image() = data_ctrl_t =====
===== ID_VERITYPEREF:: packed_dim = 1
===== ID_VERIENUM:: p_data_type->Image() = enum(a,b) =====
===== ID_VERIENUM:: packed_dim = 1
packed_dim->Left = 1
packed_dim->Right = 0
===== ID_VERIDATATYPE:: p_data_type->Image() = bit =====
===== ID_VERIDATATYPE:: packed_dim = 0
Handling Declaration: word1
===== ID_VERISTRUCTUNION:: p_data_type->Image() = struct(high,low) =====
===== ID_VERIDATATYPE:: p_data_type->Image() = logic [7:0] =====
===== ID_VERIDATATYPE:: packed_dim = 1
packed_dim->Left = 7
packed_dim->Right = 0
===== ID_VERIDATATYPE:: p_data_type->Image() = logic [3:0] =====
===== ID_VERIDATATYPE:: packed_dim = 1
packed_dim->Left = 3
packed_dim->Right = 0
</nowiki>

Parse select modules only and ignore the rest

2022-05-02T18:44:53Z

Vince:

There is no API to parse only a subset of modules of a design that contains many modules.
However, this can be accomplished through Verific's processing of v-files.

Below is an outline of the steps involved:

- Register all the input source files as v-files for processing.<br>
- Move all of the modules to the 'work' library.<br>
- Analyze a 'dummy' file that contains only the modules of interest.<br>
- Process the v-files.<br>
- Delete the 'dummy' module itself

C++:
<nowiki>
#include <iostream>
#include "veri_file.h"
#include "VeriModule.h"
#include "VeriLibrary.h"
#include "Map.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main()
{
// Add the 'real' input file(s) to be analyzed as -v file:
veri_file::AddVFile("testa.v") ;
veri_file::AddVFile("testb.v") ;
// Move -v modules into 'work'
RuntimeFlags::SetVar("veri_move_yv_modules_into_work_library", 1) ;

// Analyze dummy file
if (!veri_file::Analyze("dummy.v", veri_file::SYSTEM_VERILOG)) return 1 ;
// Need this to process -v file
veri_file::ProcessUserLibraries() ;

VeriModule *dummy = veri_file::GetModule ("dummy") ;
delete dummy ; // no longer needed

MapIter mi;
VeriModule *module;
FOREACH_VERILOG_MODULE (mi, module) {
std::cout << "*** Module '" << module->Name() << "' in library '" << module->GetLibrary()->GetName() << "'" << s
td::endl ;
}
veri_file::PrettyPrint("pp_out.v", 0) ;
return 0 ;
}
</nowiki>

Source file testa.v:
<nowiki>
module test1 ;
wire ina, inb, inc;
wire outd;
mod1 I0(ina, inb, inc, outd);
endmodule

module test2 ;
wire ina, inb, inc;
wire outd;
mod2 I0(ina, inb, inc, outd);
endmodule
</nowiki>

Source file testb.v:
<nowiki>
module test3 ;
wire ina, inb, inc;
wire outd;
mod3 I0(ina, inb, inc, outd);
endmodule

module test4 ;
wire ina, inb, inc;
wire outd;
mod4 I0(ina, inb, inc, outd);
endmodule

module test5 ;
wire ina, inb, inc;
wire outd;
mod5 I0(ina, inb, inc, outd);
endmodule
</nowiki>

Source file dummy.v -- this contains the modules we want to parse:
<nowiki>
module dummy ();
test2 i2 ();
test3 i3 ();
endmodule
</nowiki>

Result of running the application:
<nowiki>
-- Analyzing Verilog file 'dummy.v' (VERI-1482)
-- Analyzing Verilog file 'testa.v' (VERI-1482)
-- Resolving module 'test2' (VERI-1489)
-- Analyzing Verilog file 'testb.v' (VERI-1482)
-- Resolving module 'test3' (VERI-1489)
-- Analyzing Verilog file 'testa.v' (VERI-1482)
-- Analyzing Verilog file 'testb.v' (VERI-1482)
*** Module 'test2' in library 'work'
*** Module 'test3' in library 'work'
-- Printing all libraries to file 'pp_out.v' (VERI-1492)
</nowiki>

Output file pp_out.v:
<nowiki>
module test2 ;
wire ina, inb, inc ;
wire outd ;
mod2 I0 (ina, inb, inc, outd) ;
endmodule

module test3 ;
wire ina, inb, inc ;
wire outd ;
mod3 I0 (ina, inb, inc, outd) ;
endmodule

</nowiki>

Parse select modules only and ignore the rest

2022-05-02T18:44:19Z

Vince:

There is no API to parse only a subset of modules of a design that contains many modules.
However, this can be accomplished through Verific's processing of v-files.

Below is an outline of the steps involved:

- Register all the input source files as v-files for processing.<br>
- Move all of the modules to the 'work' library.<br>
- Analyze a 'dummy' file that contains only the modules of interest.<br>
- Process the v-files
- Delete the 'dummy' module itself

C++:
<nowiki>
#include <iostream>
#include "veri_file.h"
#include "VeriModule.h"
#include "VeriLibrary.h"
#include "Map.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main()
{
// Add the 'real' input file(s) to be analyzed as -v file:
veri_file::AddVFile("testa.v") ;
veri_file::AddVFile("testb.v") ;
// Move -v modules into 'work'
RuntimeFlags::SetVar("veri_move_yv_modules_into_work_library", 1) ;

// Analyze dummy file
if (!veri_file::Analyze("dummy.v", veri_file::SYSTEM_VERILOG)) return 1 ;
// Need this to process -v file
veri_file::ProcessUserLibraries() ;

VeriModule *dummy = veri_file::GetModule ("dummy") ;
delete dummy ; // no longer needed

MapIter mi;
VeriModule *module;
FOREACH_VERILOG_MODULE (mi, module) {
std::cout << "*** Module '" << module->Name() << "' in library '" << module->GetLibrary()->GetName() << "'" << s
td::endl ;
}
veri_file::PrettyPrint("pp_out.v", 0) ;
return 0 ;
}
</nowiki>

Source file testa.v:
<nowiki>
module test1 ;
wire ina, inb, inc;
wire outd;
mod1 I0(ina, inb, inc, outd);
endmodule

module test2 ;
wire ina, inb, inc;
wire outd;
mod2 I0(ina, inb, inc, outd);
endmodule
</nowiki>

Source file testb.v:
<nowiki>
module test3 ;
wire ina, inb, inc;
wire outd;
mod3 I0(ina, inb, inc, outd);
endmodule

module test4 ;
wire ina, inb, inc;
wire outd;
mod4 I0(ina, inb, inc, outd);
endmodule

module test5 ;
wire ina, inb, inc;
wire outd;
mod5 I0(ina, inb, inc, outd);
endmodule
</nowiki>

Source file dummy.v -- this contains the modules we want to parse:
<nowiki>
module dummy ();
test2 i2 ();
test3 i3 ();
endmodule
</nowiki>

Result of running the application:
<nowiki>
-- Analyzing Verilog file 'dummy.v' (VERI-1482)
-- Analyzing Verilog file 'testa.v' (VERI-1482)
-- Resolving module 'test2' (VERI-1489)
-- Analyzing Verilog file 'testb.v' (VERI-1482)
-- Resolving module 'test3' (VERI-1489)
-- Analyzing Verilog file 'testa.v' (VERI-1482)
-- Analyzing Verilog file 'testb.v' (VERI-1482)
*** Module 'test2' in library 'work'
*** Module 'test3' in library 'work'
-- Printing all libraries to file 'pp_out.v' (VERI-1492)
</nowiki>

Output file pp_out.v:
<nowiki>
module test2 ;
wire ina, inb, inc ;
wire outd ;
mod2 I0 (ina, inb, inc, outd) ;
endmodule

module test3 ;
wire ina, inb, inc ;
wire outd ;
mod3 I0 (ina, inb, inc, outd) ;
endmodule

</nowiki>

Parse select modules only and ignore the rest

2022-05-02T18:39:45Z

Vince:

There is no API to parse only a subset of modules of a design that contains many modules.
However, this can be accomplished through Verific's processing of v-files.

Below is an outline of the steps involved:

- Register all the input source files as v-files for processing.<br>
- Move all of the modules to the 'work' library.<br>
- Analyze a 'dummy' file that contains only the modules of interest.<br>
- Process the v-files

C++:
<nowiki>
#include <iostream>
#include "veri_file.h"
#include "VeriModule.h"
#include "VeriLibrary.h"
#include "Map.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main()
{
// Add the 'real' input file(s) to be analyzed as -v file:
veri_file::AddVFile("testa.v") ;
veri_file::AddVFile("testb.v") ;
// Move -v modules into 'work'
RuntimeFlags::SetVar("veri_move_yv_modules_into_work_library", 1) ;

// Analyze dummy file
if (!veri_file::Analyze("dummy.v", veri_file::SYSTEM_VERILOG)) return 1 ;
// Need this to process -v file
veri_file::ProcessUserLibraries() ;

VeriModule *dummy = veri_file::GetModule ("dummy") ;
delete dummy ; // no longer needed

MapIter mi;
VeriModule *module;
FOREACH_VERILOG_MODULE (mi, module) {
std::cout << "*** Module '" << module->Name() << "' in library '" << module->GetLibrary()->GetName() << "'" << s
td::endl ;
}
veri_file::PrettyPrint("pp_out.v", 0) ;
return 0 ;
}
</nowiki>

Source file testa.v:
<nowiki>
module test1 ;
wire ina, inb, inc;
wire outd;
mod1 I0(ina, inb, inc, outd);
endmodule

module test2 ;
wire ina, inb, inc;
wire outd;
mod2 I0(ina, inb, inc, outd);
endmodule
</nowiki>

Source file testb.v:
<nowiki>
module test3 ;
wire ina, inb, inc;
wire outd;
mod3 I0(ina, inb, inc, outd);
endmodule

module test4 ;
wire ina, inb, inc;
wire outd;
mod4 I0(ina, inb, inc, outd);
endmodule

module test5 ;
wire ina, inb, inc;
wire outd;
mod5 I0(ina, inb, inc, outd);
endmodule
</nowiki>

Source file dummy.v -- this contains the modules we want to parse:
<nowiki>
module dummy ();
test2 i2 ();
test3 i3 ();
endmodule
</nowiki>

Result of running the application:
<nowiki>
-- Analyzing Verilog file 'dummy.v' (VERI-1482)
-- Analyzing Verilog file 'testa.v' (VERI-1482)
-- Resolving module 'test2' (VERI-1489)
-- Analyzing Verilog file 'testb.v' (VERI-1482)
-- Resolving module 'test3' (VERI-1489)
-- Analyzing Verilog file 'testa.v' (VERI-1482)
-- Analyzing Verilog file 'testb.v' (VERI-1482)
*** Module 'test2' in library 'work'
*** Module 'test3' in library 'work'
-- Printing all libraries to file 'pp_out.v' (VERI-1492)
</nowiki>

Output file pp_out.v:
<nowiki>
module test2 ;
wire ina, inb, inc ;
wire outd ;
mod2 I0 (ina, inb, inc, outd) ;
endmodule

module test3 ;
wire ina, inb, inc ;
wire outd ;
mod3 I0 (ina, inb, inc, outd) ;
endmodule

</nowiki>

Parse select modules only and ignore the rest

2022-05-02T18:33:33Z

Vince: Created page with "There is no API to parse only a subset of modules of a design that contains many modules. However, this can be accomplished through Verific's processing of v-files. Below i..."

There is no API to parse only a subset of modules of a design that contains many modules.
However, this can be accomplished through Verific's processing of v-files.

Below is an outline of the steps involved:

- Register all the input source files as v-files for processing.<br>
- Move all of the modules to the 'work' library.<br>
- Analyze a 'dummy' file that contains only the modules of interest.<br>
- Process the v-files

C++:
<nowiki>
#include <iostream>
#include "veri_file.h"
#include "VeriModule.h"
#include "VeriLibrary.h"
#include "Map.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

int main()
{
// Add the 'real' input file(s) to be analyzed as -v file:
veri_file::AddVFile("testa.v") ;
veri_file::AddVFile("testb.v") ;
// Move -v modules into 'work'
RuntimeFlags::SetVar("veri_move_yv_modules_into_work_library", 1) ;

// Analyze dummy file
if (!veri_file::Analyze("dummy.v", veri_file::SYSTEM_VERILOG)) return 1 ;
// Need this to process -v file
veri_file::ProcessUserLibraries() ;

VeriModule *dummy = veri_file::GetModule ("dummy") ;
delete dummy ; // no longer needed

MapIter mi;
VeriModule *module;
FOREACH_VERILOG_MODULE (mi, module) {
std::cout << "*** Module '" << module->Name() << "' in library '" << module->GetLibrary()->GetName() << "'" << s
td::endl ;
}
veri_file::PrettyPrint("pp_out.v", 0) ;
return 0 ;
}
</nowiki>

Source file testa.v:
<nowiki>
module test1 ;
wire ina, inb, inc;
wire outd;
mod1 I0(ina, inb, inc, outd);
endmodule

module test2 ;
wire ina, inb, inc;
wire outd;
mod2 I0(ina, inb, inc, outd);
endmodule
</nowiki>

Source file testb.v:
<nowiki>
module test3 ;
wire ina, inb, inc;
wire outd;
mod3 I0(ina, inb, inc, outd);
endmodule

module test4 ;
wire ina, inb, inc;
wire outd;
mod4 I0(ina, inb, inc, outd);
endmodule

module test5 ;
wire ina, inb, inc;
wire outd;
mod5 I0(ina, inb, inc, outd);
endmodule
</nowiki>

Result of running the application:
<nowiki>
-- Analyzing Verilog file 'dummy.v' (VERI-1482)
-- Analyzing Verilog file 'testa.v' (VERI-1482)
-- Resolving module 'test2' (VERI-1489)
-- Analyzing Verilog file 'testb.v' (VERI-1482)
-- Resolving module 'test3' (VERI-1489)
-- Analyzing Verilog file 'testa.v' (VERI-1482)
-- Analyzing Verilog file 'testb.v' (VERI-1482)
*** Module 'test2' in library 'work'
*** Module 'test3' in library 'work'
-- Printing all libraries to file 'pp_out.v' (VERI-1492)
</nowiki>

Output file pp_out.v:
<nowiki>
module test2 ;
wire ina, inb, inc ;
wire outd ;
mod2 I0 (ina, inb, inc, outd) ;
endmodule

module test3 ;
wire ina, inb, inc ;
wire outd ;
mod3 I0 (ina, inb, inc, outd) ;
endmodule

</nowiki>

Main Page

2022-05-02T18:00:53Z

Vince:

'''General'''
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
* [[Source code customization & Stable release services | Source code customization & Stable release services]]
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]
* [[Release version | How do I tell the version of a Verific software release? ]]
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
* [[LineFile data from input files | LineFile data from input files]]
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]
* [[Preserving user nets - preventing nets from being optimized away | Preserving user nets - preventing nets from being optimized away]]

'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
* [[Notes on analysis | SystemVerilog: Notes on analysis]]
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]]
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]

* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
'''Netlist Database'''
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]
* [[System attributes | Netlist Database: System attributes]]

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''Scripting languages: TCL, Perl, Python'''
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]

'''Code examples'''
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
* [[Extract clock enable | Database/C++: Extract clock enable]]
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
* [[Type Range example | Verilog/C++: Type Range example (simple)]]
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
* [[How to ignore certain modules while analyzing input RTL files | Verilog/C++: How to ignore certain modules while analyzing input RTL files]]
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]
* [[Parse select modules only and ignore the rest | Verilog/C++: Parse select modules only and ignore the rest]]
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]

Main Page

2022-04-01T18:26:20Z

Vince:

'''General'''
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
* [[Source code customization & Stable release services | Source code customization & Stable release services]]
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]
* [[Release version | How do I tell the version of a Verific software release? ]]
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
* [[LineFile data from input files | LineFile data from input files]]
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]
* [[Preserving user nets - preventing nets from being optimized away | Preserving user nets - preventing nets from being optimized away]]

'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
* [[Notes on analysis | SystemVerilog: Notes on analysis]]
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]]
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]

* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
'''Netlist Database'''
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]
* [[System attributes | Netlist Database: System attributes]]

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''Scripting languages: TCL, Perl, Python'''
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]

'''Code examples'''
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
* [[Extract clock enable | Database/C++: Extract clock enable]]
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
* [[Type Range example | Verilog/C++: Type Range example (simple)]]
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]

Main Page

2022-04-01T18:25:39Z

Vince:

'''General'''
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
* [[Source code customization & Stable release services | Source code customization & Stable release services]]
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]
* [[Release version | How do I tell the version of a Verific software release? ]]
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
* [[LineFile data from input files | LineFile data from input files]]
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]
* [[Preserving user nets | Preserving user nets - preventing nets from being optimized away]]

'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
* [[Notes on analysis | SystemVerilog: Notes on analysis]]
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]]
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]

* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
'''Netlist Database'''
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]
* [[System attributes | Netlist Database: System attributes]]

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''Scripting languages: TCL, Perl, Python'''
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]

'''Code examples'''
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
* [[Extract clock enable | Database/C++: Extract clock enable]]
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
* [[Type Range example | Verilog/C++: Type Range example (simple)]]
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]

Preserving nets

2022-04-01T18:24:24Z

Vince: Redirected page to Preserving user nets - preventing nets from being optimized away

#REDIRECT [[Preserving user nets - preventing nets from being optimized away]]

Main Page

2022-04-01T18:20:58Z

Vince:

'''General'''
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
* [[Source code customization & Stable release services | Source code customization & Stable release services]]
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]
* [[Release version | How do I tell the version of a Verific software release? ]]
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
* [[LineFile data from input files | LineFile data from input files]]
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]
* [[Preserving nets | Preserving user nets - preventing nets from being optimized away]]

'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
* [[Notes on analysis | SystemVerilog: Notes on analysis]]
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]]
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]

* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
'''Netlist Database'''
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]
* [[System attributes | Netlist Database: System attributes]]

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''Scripting languages: TCL, Perl, Python'''
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]

'''Code examples'''
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
* [[Extract clock enable | Database/C++: Extract clock enable]]
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
* [[Type Range example | Verilog/C++: Type Range example (simple)]]
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]

Main Page

2022-04-01T18:20:03Z

Vince:

'''General'''
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]
* [[Source code customization & Stable release services | Source code customization & Stable release services]]
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]
* [[Verific data structures | What are the data structures in Verific?]]
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]
* [[Release version | How do I tell the version of a Verific software release? ]]
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]
* [[LineFile data from input files | LineFile data from input files]]
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]
* [[Preserving user nets | Preserving user nets - preventing nets from being optimized away]]

'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]
* [[Notes on analysis | SystemVerilog: Notes on analysis]]
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]]
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]

* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]
'''Netlist Database'''
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]
* [[System attributes | Netlist Database: System attributes]]

'''Output'''
* [[Output file formats | What language formats does Verific support as output?]]

'''Scripting languages: TCL, Perl, Python'''
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]

'''Code examples'''
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]
* [[Extract clock enable | Database/C++: Extract clock enable]]
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]
* [[Type Range example | Verilog/C++: Type Range example (simple)]]
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]]
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]

Preserving user nets - preventing nets from being optimized away

2022-04-01T18:17:38Z

Vince:

'''Q: How do I preserve user-declared nets so that they don't get optimized away? I would like to see them written out to the netlist file.'''

There are two approaches :
* globally preserve all user nets
* preserve only selective nets

1. Globally preserve all user nets

The following flags need to be set to have global effect :

set_runtime_flag db_preserve_user_nets 1
set_runtime_flag veri_preserve_user_nets 1 # if using Verilog/SystemVerilog
set_runtime_flag vhdl_preserve_user_nets 1 # if using VHDL

2. Preserve only selective nets

Setting an attribute on a net will prevent it from being optimized away. The attribute can be any attribute, as seen in the examples below.

Verilog :

module test (input i, output o);
(* any *) wire willstay;
wire willgo;
(* another = "any" *) reg willstaytoo;
assign o = ~i;
endmodule

This is the output Verilog netlist :
//
// Verific Verilog Description of module test
//
module test (i, o); // test2.v(1)
input i; // test2.v(1)
output o; // test2.v(1)

wire willstay /* verific any=1 */ ; // test2.v(2)
wire willstaytoo /* verific another="any" */ ; // test2.v(4)

not (o, i) ; // test2.v(5)

endmodule

VHDL :

library ieee;
use ieee.std_logic_1164.all ;
entity test is
port (i : in bit; o : out bit) ;
end entity test;
architecture arch of test is
signal willstay : bit ;
signal willgo : bit ;
signal willstaytoo : bit ;
attribute any : string ;
attribute any of willstay : signal is "" ;
attribute another : string ;
attribute another of willstaytoo : signal is "any" ;
begin
o <= not i ;
end arch ;

This is the output VHDL netlist :
--
-- Verific VHDL Description of module test
--
library ieee ;
use ieee.std_logic_1164.all ;
entity test is
port (i: in std_logic; -- test2.vhd(4)
o: out std_logic -- test2.vhd(4)
);
end entity test; -- test2.vhd(3)
architecture arch of test is
signal willstay : std_logic; -- any="" -- test2.vhd(8)
signal willstaytoo : std_logic; -- another="any" -- test2.vhd(10)
begin
o <= not i; -- test2.vhd(16)
end architecture arch; -- test2.vhd(3)

Preserving user nets - preventing nets from being optimized away

2022-04-01T18:16:48Z

Vince: Vince moved page Preserving user nets --preventing nets from being optimized away to Preserving user nets - preventing nets from being optimized away

'''Q: How do I preserve user-declared nets so that they don't get optimized away? I would like to see them written out to the netlist file.'''

There are two approaches :
* globally preserve all user nets
* preserve only selective nets

1. Globally preserve all user nets

The following flags need to be set for global effect :

set_runtime_flag db_preserve_user_nets 1
set_runtime_flag veri_preserve_user_nets 1 # if using Verilog/SystemVerilog
set_runtime_flag vhdl_preserve_user_nets 1 # if using VHDL

2. Preserve only selective nets

Setting an attribute on a net will prevent it from being optimized away. The attribute can be any attribute, as seen in the examples below.

Verilog :

module test (input i, output o);
(* any *) wire willstay;
wire willgo;
(* another = "any" *) reg willstaytoo;
assign o = ~i;
endmodule

This is the output Verilog netlist :
//
// Verific Verilog Description of module test
//
module test (i, o); // test2.v(1)
input i; // test2.v(1)
output o; // test2.v(1)

wire willstay /* verific any=1 */ ; // test2.v(2)
wire willstaytoo /* verific another="any" */ ; // test2.v(4)

not (o, i) ; // test2.v(5)

endmodule

VHDL :

library ieee;
use ieee.std_logic_1164.all ;
entity test is
port (i : in bit; o : out bit) ;
end entity test;
architecture arch of test is
signal willstay : bit ;
signal willgo : bit ;
signal willstaytoo : bit ;
attribute any : string ;
attribute any of willstay : signal is "" ;
attribute another : string ;
attribute another of willstaytoo : signal is "any" ;
begin
o <= not i ;
end arch ;

This is the output VHDL netlist :
--
-- Verific VHDL Description of module test
--
library ieee ;
use ieee.std_logic_1164.all ;
entity test is
port (i: in std_logic; -- test2.vhd(4)
o: out std_logic -- test2.vhd(4)
);
end entity test; -- test2.vhd(3)
architecture arch of test is
signal willstay : std_logic; -- any="" -- test2.vhd(8)
signal willstaytoo : std_logic; -- another="any" -- test2.vhd(10)
begin
o <= not i; -- test2.vhd(16)
end architecture arch; -- test2.vhd(3)

Preserving user nets --preventing nets from being optimized away

2022-04-01T18:16:48Z

Vince: Vince moved page Preserving user nets --preventing nets from being optimized away to Preserving user nets - preventing nets from being optimized away

#REDIRECT [[Preserving user nets - preventing nets from being optimized away]]