https://www.verific.com/faq/api.php?action=feedcontributions&user=Vince&feedformat=atomVerific Design Automation FAQ - User contributions [en]2024-03-29T00:57:17ZUser contributionsMediaWiki 1.26.3https://www.verific.com/faq/index.php?title=Create_DOT_diagram_of_parse_tree&diff=882Create DOT diagram of parse tree2024-01-13T02:08:40Z<p>Vince: </p>
<hr />
<div>This example parses the r4000 design in the <verific>/example_designs/verilog directory and writes out a Graphviz DOT-format file that represents a simple diagram view of the design.<br />
<br />
There are several tools that can visualize DOT files. On Linux distributions you can install 'dot'. You would run this command to create a PDF output of the C++ application below <br />
<br />
dot -Tpdf pp_out.dot -o r4000.pdf<br />
<br />
<br />
C++:<br />
<nowiki><br />
#include <iostream><br />
#include "veri_file.h"<br />
#include "VeriModule.h"<br />
#include "VeriId.h"<br />
#include "VeriExpression.h"<br />
#include "VeriVisitor.h"<br />
#include "Map.h"<br />
<br />
using namespace std ;<br />
#ifdef VERIFIC_NAMESPACE<br />
using namespace Verific ;<br />
#endif<br />
<br />
int main() {<br />
<br />
char ppfile_nm[32] = "pp_out.dot";<br />
char transition[64] ;<br />
unsigned module_cnt = 0 ;<br />
unsigned field_cnt = 0 ;<br />
Array transition_table ;<br />
Array instantiation_table ;<br />
Array module_table ;<br />
<br />
ofstream ofs(ppfile_nm, std::ios::out) ;<br />
<br />
if (!veri_file::Analyze("r4000.v", veri_file::SYSTEM_VERILOG)) return 1 ;<br />
<br />
ofs << "digraph Verific {" << endl ;<br />
ofs << " rankdir = LR" << endl ;<br />
ofs << " node [shape=plaintext]" << endl ;<br />
ofs << " edge [dir=forward]" << endl ;<br />
<br />
MapIter mi ;<br />
unsigned i ;<br />
VeriModule *mod ;<br />
<br />
FOREACH_VERILOG_MODULE(mi, mod)<br />
module_table.Insert(mod) ;<br />
<br />
FOREACH_VERILOG_MODULE(mi, mod) {<br />
ofs << " cell" << module_cnt ;<br />
ofs << " [label=< <TABLE BORDER=\"0\" CELLBORDER=\"1\" CELLSPACING=\"0\">" << endl ; <br />
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt++ << "\" BGCOLOR=\"gray\">MODULE : " << mod->Name() << "</TD> </TR>" << endl ;<br />
<br />
Array *ports = mod->GetPorts();<br />
if (ports) {<br />
VeriIdDef *port ;<br />
FOREACH_ARRAY_ITEM(ports, i, port) {<br />
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt++ << "\"> port : " << port->Name() << "</TD> </TR>" << endl ;<br />
}<br />
}<br />
<br />
Array *params = mod->GetParameters();<br />
if (params) {<br />
VeriIdDef *param ;<br />
FOREACH_ARRAY_ITEM(params, i, param) {<br />
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt++ << "\"> parameter : " << param->Name() ;<br />
VeriExpression *initvalue = param->GetInitialValue();<br />
if (initvalue)<br />
ofs << " = " << initvalue->GetPrettyPrintedString() << "</TD> </TR>" << endl ;<br />
}<br />
}<br />
<br />
Array *module_items = mod->GetModuleItems() ;<br />
VeriModuleItem *module_item ;<br />
FOREACH_ARRAY_ITEM(module_items, i, module_item) {<br />
switch (module_item->GetClassId()) {<br />
case ID_VERIMODULEINSTANTIATION:<br />
{<br />
VeriModuleInstantiation *mod_inst = static_cast<VeriModuleInstantiation*>(module_item) ;<br />
unsigned j ;<br />
VeriInstId *inst_id ;<br />
FOREACH_ARRAY_ITEM(mod_inst->GetIds(), j, inst_id) {<br />
if (!inst_id) continue ;<br />
<br />
instantiation_table.Insert(inst_id) ;<br />
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt << "\"> instantiations : " << mod_inst->GetModuleName() << " : " << inst_id->InstName() << "</TD> </TR>" << endl ;<br />
unsigned k ;<br />
FOREACH_ARRAY_ITEM(&module_table, k, mod) {<br />
if (Strings::compare(inst_id->GetModuleReference(), mod->Name())) {<br />
sprintf (transition, " cell%d:f%d -> cell%d:f0 ;", module_cnt, field_cnt, k) ;<br />
char *trans = Strings::save(transition) ;<br />
transition_table.Insert(trans) ;<br />
}<br />
}<br />
field_cnt++ ;<br />
}<br />
}<br />
default : ;<br />
}<br />
}<br />
<br />
ofs << " </TABLE> >] ;" << endl ;<br />
field_cnt = 0 ;<br />
module_cnt++ ;<br />
}<br />
<br />
ofs << endl ;<br />
<br />
char *trans ;<br />
FOREACH_ARRAY_ITEM(&transition_table, i, trans) {<br />
ofs << trans << endl ;<br />
}<br />
<br />
ofs << "}" << endl ;<br />
ofs.close();<br />
<br />
return 0 ;<br />
}<br />
</nowiki></div>Vincehttps://www.verific.com/faq/index.php?title=Create_DOT_diagram_of_parse_tree&diff=881Create DOT diagram of parse tree2024-01-13T02:05:44Z<p>Vince: </p>
<hr />
<div>This example parses the r4000 design in the <verific>/example_designs/verilog directory and writes out a Graphviz DOT-format file that represents a simple diagram view of the design.<br />
<br />
There are several tools that can visualize DOT files. On Linux distributions you can install 'dot'. You would run this command to view the output of the C++ application below <br />
<br />
dot -Tpdf pp_out.dot -o r4000.pdf<br />
<br />
<br />
C++:<br />
<nowiki><br />
#include <iostream><br />
#include "veri_file.h"<br />
#include "VeriModule.h"<br />
#include "VeriId.h"<br />
#include "VeriExpression.h"<br />
#include "VeriVisitor.h"<br />
#include "Map.h"<br />
<br />
using namespace std ;<br />
#ifdef VERIFIC_NAMESPACE<br />
using namespace Verific ;<br />
#endif<br />
<br />
int main() {<br />
<br />
char ppfile_nm[32] = "pp_out.dot";<br />
char transition[64] ;<br />
unsigned module_cnt = 0 ;<br />
unsigned field_cnt = 0 ;<br />
Array transition_table ;<br />
Array instantiation_table ;<br />
Array module_table ;<br />
<br />
ofstream ofs(ppfile_nm, std::ios::out) ;<br />
<br />
if (!veri_file::Analyze("r4000.v", veri_file::SYSTEM_VERILOG)) return 1 ;<br />
<br />
ofs << "digraph Verific {" << endl ;<br />
ofs << " rankdir = LR" << endl ;<br />
ofs << " node [shape=plaintext]" << endl ;<br />
ofs << " edge [dir=forward]" << endl ;<br />
<br />
MapIter mi ;<br />
unsigned i ;<br />
VeriModule *mod ;<br />
<br />
FOREACH_VERILOG_MODULE(mi, mod)<br />
module_table.Insert(mod) ;<br />
<br />
FOREACH_VERILOG_MODULE(mi, mod) {<br />
ofs << " cell" << module_cnt ;<br />
ofs << " [label=< <TABLE BORDER=\"0\" CELLBORDER=\"1\" CELLSPACING=\"0\">" << endl ; <br />
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt++ << "\" BGCOLOR=\"gray\">MODULE : " << mod->Name() << "</TD> </TR>" << endl ;<br />
<br />
Array *ports = mod->GetPorts();<br />
if (ports) {<br />
VeriIdDef *port ;<br />
FOREACH_ARRAY_ITEM(ports, i, port) {<br />
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt++ << "\"> port : " << port->Name() << "</TD> </TR>" << endl ;<br />
}<br />
}<br />
<br />
Array *params = mod->GetParameters();<br />
if (params) {<br />
VeriIdDef *param ;<br />
FOREACH_ARRAY_ITEM(params, i, param) {<br />
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt++ << "\"> parameter : " << param->Name() ;<br />
VeriExpression *initvalue = param->GetInitialValue();<br />
if (initvalue)<br />
ofs << " = " << initvalue->GetPrettyPrintedString() << "</TD> </TR>" << endl ;<br />
}<br />
}<br />
<br />
Array *module_items = mod->GetModuleItems() ;<br />
VeriModuleItem *module_item ;<br />
FOREACH_ARRAY_ITEM(module_items, i, module_item) {<br />
switch (module_item->GetClassId()) {<br />
case ID_VERIMODULEINSTANTIATION:<br />
{<br />
VeriModuleInstantiation *mod_inst = static_cast<VeriModuleInstantiation*>(module_item) ;<br />
unsigned j ;<br />
VeriInstId *inst_id ;<br />
FOREACH_ARRAY_ITEM(mod_inst->GetIds(), j, inst_id) {<br />
if (!inst_id) continue ;<br />
<br />
instantiation_table.Insert(inst_id) ;<br />
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt << "\"> instantiations : " << mod_inst->GetModuleName() << " : " << inst_id->InstName() << "</TD> </TR>" << endl ;<br />
unsigned k ;<br />
FOREACH_ARRAY_ITEM(&module_table, k, mod) {<br />
if (Strings::compare(inst_id->GetModuleReference(), mod->Name())) {<br />
sprintf (transition, " cell%d:f%d -> cell%d:f0 ;", module_cnt, field_cnt, k) ;<br />
char *trans = Strings::save(transition) ;<br />
transition_table.Insert(trans) ;<br />
}<br />
}<br />
field_cnt++ ;<br />
}<br />
}<br />
default : ;<br />
}<br />
}<br />
<br />
ofs << " </TABLE> >] ;" << endl ;<br />
field_cnt = 0 ;<br />
module_cnt++ ;<br />
}<br />
<br />
ofs << endl ;<br />
<br />
char *trans ;<br />
FOREACH_ARRAY_ITEM(&transition_table, i, trans) {<br />
ofs << trans << endl ;<br />
}<br />
<br />
ofs << "}" << endl ;<br />
ofs.close();<br />
<br />
return 0 ;<br />
}<br />
</nowiki></div>Vincehttps://www.verific.com/faq/index.php?title=Main_Page&diff=880Main Page2024-01-13T01:59:54Z<p>Vince: </p>
<hr />
<div>'''General'''<br />
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]<br />
* [[Source code customization & Stable release services | Source code customization & Stable release services]]<br />
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]<br />
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]<br />
* [[Verific data structures | What are the data structures in Verific?]]<br />
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]<br />
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]<br />
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]<br />
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]<br />
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]<br />
* [[Release version | How do I tell the version of a Verific software release? ]]<br />
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]<br />
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]<br />
* [[LineFile data from input files | LineFile data from input files]]<br />
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]<br />
* [[Preserving user nets - preventing nets from being optimized away | Preserving user nets - preventing nets from being optimized away]]<br />
* [[Python pretty-printer for gdb | Python pretty-printer for gdb]]<br />
<br />
'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''<br />
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]<br />
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]<br />
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]<br />
* [[Verilog ports being renamed | Verilog: Port Expressions]]<br />
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]<br />
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]<br />
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]<br />
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]<br />
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]<br />
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]<br />
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]<br />
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]<br />
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]<br />
* [[Modules with '_1' '_2' suffix in their names | Verilog: After static elaboration, there are modules with "_1", "_2", ..., suffix in their names. Why?]]<br />
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]<br />
* [[Notes on analysis | SystemVerilog: Notes on analysis]]<br />
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]<br />
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]<br />
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]<br />
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]<br />
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]<br />
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]<br />
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]<br />
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]<br />
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]<br />
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]<br />
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]<br />
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]<br />
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]<br />
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units/interfaces with "_default" suffix in their names. Why? And what are they?]]<br />
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]<br />
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]<br />
'''Netlist Database'''<br />
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]<br />
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]<br />
* [[System attributes | Netlist Database: System attributes]]<br />
<br />
'''Output'''<br />
* [[Output file formats | What language formats does Verific support as output?]]<br />
<br />
'''Scripting languages: TCL, Perl, Python'''<br />
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]<br />
<br />
'''Code examples'''<br />
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]<br />
* [[How to use MessageCallBackHandler Class | Util/C++: How to use MessageCallBackHandler Class]]<br />
* [[How to use RegisterPragmaRefCallBack() | Util/C++: How to use RegisterPragmaRefCallBack()]]<br />
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]<br />
* [[Extract clock enable | Database/C++: Extract clock enable]]<br />
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]<br />
* [[Finding hierarchical paths of a Netlist | Database/C++: Finding hierarchical paths of a Netlist]]<br />
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]<br />
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]<br />
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]<br />
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]<br />
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]<br />
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]<br />
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]<br />
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]<br />
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]<br />
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]<br />
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]<br />
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]<br />
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]<br />
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]<br />
* [[Type Range example | Verilog/C++: Type Range example (simple)]]<br />
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]<br />
* [[How to ignore certain modules while analyzing input RTL files | Verilog/C++: How to ignore certain modules while analyzing input RTL files]]<br />
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]<br />
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]] <br />
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]<br />
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]<br />
* [[In Verilog parsetree adding names to unnamed instances | Verilog/C++: In Verilog parsetree adding names to unnamed instances]]<br />
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]<br />
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]<br />
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]<br />
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]<br />
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]<br />
* [[Parse select modules only and ignore the rest | Verilog/C++: Parse select modules only and ignore the rest]]<br />
* [[Create DOT diagram of parse tree | Verilog/C++: Create DOT diagram of a parse tree]]<br />
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]<br />
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]<br />
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]<br />
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]<br />
* [[Evaluate 'for-generate' loop | Verilog/C++: Evaluate 'for-generate' loop]]<br />
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]<br />
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]<br />
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]<br />
* [[Simple examples of VHDL visitor pattern | VHDL/C++: Simple examples of VHDL visitor pattern]]<br />
* [[Traverse instances in parsetree | VHDL/C++: Traverse instances in parsetree]]<br />
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]</div>Vincehttps://www.verific.com/faq/index.php?title=Create_DOT_diagram_of_parse_tree&diff=879Create DOT diagram of parse tree2024-01-13T01:57:22Z<p>Vince: Created page with "This example parses the r4000 design in the <verific>/example_designs/verilog directory and writes out a Graphviz DOT-format file that represents a simple diagram view of th..."</p>
<hr />
<div>This example parses the r4000 design in the <verific>/example_designs/verilog directory and writes out a Graphviz DOT-format file that represents a simple diagram view of the design.<br />
<br />
There are several tools that can visualize DOT files. On Linux distributions you can install 'dot'. For the output of the application below you would run<br />
<br />
dot -Tpdf pp_out.dot -o r4000.pdf<br />
<br />
<br />
C++:<br />
<nowiki><br />
#include <iostream><br />
#include "veri_file.h"<br />
#include "VeriModule.h"<br />
#include "VeriId.h"<br />
#include "VeriExpression.h"<br />
#include "VeriVisitor.h"<br />
#include "Map.h"<br />
<br />
using namespace std ;<br />
#ifdef VERIFIC_NAMESPACE<br />
using namespace Verific ;<br />
#endif<br />
<br />
int main() {<br />
<br />
char ppfile_nm[32] = "pp_out.dot";<br />
char transition[64] ;<br />
unsigned module_cnt = 0 ;<br />
unsigned field_cnt = 0 ;<br />
Array transition_table ;<br />
Array instantiation_table ;<br />
Array module_table ;<br />
<br />
ofstream ofs(ppfile_nm, std::ios::out) ;<br />
<br />
if (!veri_file::Analyze("r4000.v", veri_file::SYSTEM_VERILOG)) return 1 ;<br />
<br />
ofs << "digraph Verific {" << endl ;<br />
ofs << " rankdir = LR" << endl ;<br />
ofs << " node [shape=plaintext]" << endl ;<br />
ofs << " edge [dir=forward]" << endl ;<br />
<br />
MapIter mi ;<br />
unsigned i ;<br />
VeriModule *mod ;<br />
<br />
FOREACH_VERILOG_MODULE(mi, mod)<br />
module_table.Insert(mod) ;<br />
<br />
FOREACH_VERILOG_MODULE(mi, mod) {<br />
ofs << " cell" << module_cnt ;<br />
ofs << " [label=< <TABLE BORDER=\"0\" CELLBORDER=\"1\" CELLSPACING=\"0\">" << endl ; <br />
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt++ << "\" BGCOLOR=\"gray\">MODULE : " << mod->Name() << "</TD> </TR>" << endl ;<br />
<br />
Array *ports = mod->GetPorts();<br />
if (ports) {<br />
VeriIdDef *port ;<br />
FOREACH_ARRAY_ITEM(ports, i, port) {<br />
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt++ << "\"> port : " << port->Name() << "</TD> </TR>" << endl ;<br />
}<br />
}<br />
<br />
Array *params = mod->GetParameters();<br />
if (params) {<br />
VeriIdDef *param ;<br />
FOREACH_ARRAY_ITEM(params, i, param) {<br />
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt++ << "\"> parameter : " << param->Name() ;<br />
VeriExpression *initvalue = param->GetInitialValue();<br />
if (initvalue)<br />
ofs << " = " << initvalue->GetPrettyPrintedString() << "</TD> </TR>" << endl ;<br />
}<br />
}<br />
<br />
Array *module_items = mod->GetModuleItems() ;<br />
VeriModuleItem *module_item ;<br />
FOREACH_ARRAY_ITEM(module_items, i, module_item) {<br />
switch (module_item->GetClassId()) {<br />
case ID_VERIMODULEINSTANTIATION:<br />
{<br />
VeriModuleInstantiation *mod_inst = static_cast<VeriModuleInstantiation*>(module_item) ;<br />
unsigned j ;<br />
VeriInstId *inst_id ;<br />
FOREACH_ARRAY_ITEM(mod_inst->GetIds(), j, inst_id) {<br />
if (!inst_id) continue ;<br />
<br />
instantiation_table.Insert(inst_id) ;<br />
ofs << " <TR> <TD ALIGN=\"left\" PORT=\"f" << field_cnt << "\"> instantiations : " << mod_inst->GetModuleName() << " : " << inst_id->InstName() << "</TD> </TR>" << endl ;<br />
unsigned k ;<br />
FOREACH_ARRAY_ITEM(&module_table, k, mod) {<br />
if (Strings::compare(inst_id->GetModuleReference(), mod->Name())) {<br />
sprintf (transition, " cell%d:f%d -> cell%d:f0 ;", module_cnt, field_cnt, k) ;<br />
char *trans = Strings::save(transition) ;<br />
transition_table.Insert(trans) ;<br />
}<br />
}<br />
field_cnt++ ;<br />
}<br />
}<br />
default : ;<br />
}<br />
}<br />
<br />
ofs << " </TABLE> >] ;" << endl ;<br />
field_cnt = 0 ;<br />
module_cnt++ ;<br />
}<br />
<br />
ofs << endl ;<br />
<br />
char *trans ;<br />
FOREACH_ARRAY_ITEM(&transition_table, i, trans) {<br />
ofs << trans << endl ;<br />
}<br />
<br />
ofs << "}" << endl ;<br />
ofs.close();<br />
<br />
return 0 ;<br />
}<br />
</nowiki></div>Vincehttps://www.verific.com/faq/index.php?title=Main_Page&diff=878Main Page2024-01-13T01:38:06Z<p>Vince: </p>
<hr />
<div>'''General'''<br />
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]<br />
* [[Source code customization & Stable release services | Source code customization & Stable release services]]<br />
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]<br />
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]<br />
* [[Verific data structures | What are the data structures in Verific?]]<br />
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]<br />
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]<br />
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]<br />
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]<br />
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]<br />
* [[Release version | How do I tell the version of a Verific software release? ]]<br />
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]<br />
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]<br />
* [[LineFile data from input files | LineFile data from input files]]<br />
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]<br />
* [[Preserving user nets - preventing nets from being optimized away | Preserving user nets - preventing nets from being optimized away]]<br />
* [[Python pretty-printer for gdb | Python pretty-printer for gdb]]<br />
<br />
'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''<br />
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]<br />
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]<br />
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]<br />
* [[Verilog ports being renamed | Verilog: Port Expressions]]<br />
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]<br />
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]<br />
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]<br />
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]<br />
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]<br />
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]<br />
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]<br />
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]<br />
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]<br />
* [[Modules with '_1' '_2' suffix in their names | Verilog: After static elaboration, there are modules with "_1", "_2", ..., suffix in their names. Why?]]<br />
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]<br />
* [[Notes on analysis | SystemVerilog: Notes on analysis]]<br />
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]<br />
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]<br />
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]<br />
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]<br />
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]<br />
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]<br />
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]<br />
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]<br />
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]<br />
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]<br />
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]<br />
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]<br />
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]<br />
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units/interfaces with "_default" suffix in their names. Why? And what are they?]]<br />
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]<br />
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]<br />
'''Netlist Database'''<br />
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]<br />
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]<br />
* [[System attributes | Netlist Database: System attributes]]<br />
<br />
'''Output'''<br />
* [[Output file formats | What language formats does Verific support as output?]]<br />
<br />
'''Scripting languages: TCL, Perl, Python'''<br />
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]<br />
<br />
'''Code examples'''<br />
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]<br />
* [[How to use MessageCallBackHandler Class | Util/C++: How to use MessageCallBackHandler Class]]<br />
* [[How to use RegisterPragmaRefCallBack() | Util/C++: How to use RegisterPragmaRefCallBack()]]<br />
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]<br />
* [[Extract clock enable | Database/C++: Extract clock enable]]<br />
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]<br />
* [[Finding hierarchical paths of a Netlist | Database/C++: Finding hierarchical paths of a Netlist]]<br />
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]<br />
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]<br />
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]<br />
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]<br />
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]<br />
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]<br />
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]<br />
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]<br />
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]<br />
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]<br />
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]<br />
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]<br />
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]<br />
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]<br />
* [[Type Range example | Verilog/C++: Type Range example (simple)]]<br />
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]<br />
* [[How to ignore certain modules while analyzing input RTL files | Verilog/C++: How to ignore certain modules while analyzing input RTL files]]<br />
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]<br />
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]] <br />
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]<br />
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]<br />
* [[In Verilog parsetree adding names to unnamed instances | Verilog/C++: In Verilog parsetree adding names to unnamed instances]]<br />
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]<br />
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]<br />
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]<br />
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]<br />
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]<br />
* [[Parse select modules only and ignore the rest | Verilog/C++: Parse select modules only and ignore the rest]]<br />
* [[Create DOT diagram of parse tree | Verilog/C++: Create DOT diagram of parse tree]]<br />
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]<br />
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]<br />
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]<br />
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]<br />
* [[Evaluate 'for-generate' loop | Verilog/C++: Evaluate 'for-generate' loop]]<br />
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]<br />
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]<br />
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]<br />
* [[Simple examples of VHDL visitor pattern | VHDL/C++: Simple examples of VHDL visitor pattern]]<br />
* [[Traverse instances in parsetree | VHDL/C++: Traverse instances in parsetree]]<br />
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]</div>Vincehttps://www.verific.com/faq/index.php?title=Modules/design_units_with_%22_default%22_suffix_in_their_names&diff=863Modules/design units with " default" suffix in their names2023-10-23T15:37:41Z<p>Vince: </p>
<hr />
<div>'''Q: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they? '''<br />
<br />
Static elaboration process is a multiple-iteration process and modules/design units may be modified differently in each iteration.<br />
<br />
We need to keep original version of modules/design units as they are immediately after analysis so that they can be copied for different parameter/generic settings in each iteration and body of copied modules/design units can be elaborated (generate unroll, array instance processing, etc.) differently for each parameter/generic setting.<br />
<br />
Another reason to copy instantiated modules/design units with "_default" name is in mixed language elaboration. Here a Verilog module may instantiate a VHDL entity which has been elaborated earlier with different generic values. In that case during Verilog elaboration we will not get original contents of instantiated entity.<br />
<br />
Moreover, to support incremental elaboration we need to keep original modules/design units, as lower level units can be elaborated earlier.<br />
<br />
In Verilog, we have a runtime-flag "veri_remove_suffix_default_from_copied_module_names" to rename modules from "<orig_name>_default" to "<orig_name>". This will work only when runtime-flag "veri_cleanup_base_modules" is set.<br />
<br />
<br />
'''Q: What about interfaces with "_default" suffix in their names? Why? And what are they? '''<br />
<br />
SystemVerilog interfaces can be used in any of the following ways :<br />
<br />
* As interface instantiations.<br />
* As interface ports.<br />
* As virtual interfaces.<br />
* As hierarchical names.<br />
<br />
If an interface is used in a virtual interface declaration, interface instance, or port of a top-level module, the interface will be copied to '<interface_name>_default', even if none of its parameters are overwritten. This copied interface will be the one that is elaborated and specified in the virtual interface declaration, interface instance, or top-level module port. Every instantiated module containing interface type ports will also be copied during static elaboration since its interface port names may have been modified as well.<br />
<br />
Virtual interfaces can appear in many different parts of a design, and may or may not be associated with interface instances. Virtual interfaces are not stored in Verific's pseudo-tree, so after static elaboration we do not know whether an interface is used as a virtual interface or not, or where it is being used. Without this knowledge, we cannot arbitrarily change all the references of an interface from '<interface_name>_default' to '<interface_name> because the references may become invalid. Because of this, we do not have flags to remove the '_default' from the interface names as we do for modules.<br />
<br />
The '_default_<n>' suffix may also be added due to the presence of hierarchical references in an interface or bind statements containing interface instantiations.</div>Vincehttps://www.verific.com/faq/index.php?title=Main_Page&diff=862Main Page2023-10-23T15:36:38Z<p>Vince: </p>
<hr />
<div>'''General'''<br />
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]<br />
* [[Source code customization & Stable release services | Source code customization & Stable release services]]<br />
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]<br />
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]<br />
* [[Verific data structures | What are the data structures in Verific?]]<br />
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]<br />
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]<br />
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]<br />
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]<br />
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]<br />
* [[Release version | How do I tell the version of a Verific software release? ]]<br />
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]<br />
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]<br />
* [[LineFile data from input files | LineFile data from input files]]<br />
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]<br />
* [[Preserving user nets - preventing nets from being optimized away | Preserving user nets - preventing nets from being optimized away]]<br />
* [[Python pretty-printer for gdb | Python pretty-printer for gdb]]<br />
<br />
'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''<br />
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]<br />
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]<br />
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]<br />
* [[Verilog ports being renamed | Verilog: Port Expressions]]<br />
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]<br />
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]<br />
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]<br />
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]<br />
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]<br />
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]<br />
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]<br />
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]<br />
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]<br />
* [[Modules with '_1' '_2' suffix in their names | Verilog: After static elaboration, there are modules with "_1", "_2", ..., suffix in their names. Why?]]<br />
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]<br />
* [[Notes on analysis | SystemVerilog: Notes on analysis]]<br />
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]<br />
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]<br />
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]<br />
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]<br />
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]<br />
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]<br />
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]<br />
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]<br />
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]<br />
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]<br />
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]<br />
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]<br />
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]<br />
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units/interfaces with "_default" suffix in their names. Why? And what are they?]]<br />
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]<br />
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]<br />
'''Netlist Database'''<br />
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]<br />
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]<br />
* [[System attributes | Netlist Database: System attributes]]<br />
<br />
'''Output'''<br />
* [[Output file formats | What language formats does Verific support as output?]]<br />
<br />
'''Scripting languages: TCL, Perl, Python'''<br />
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]<br />
<br />
'''Code examples'''<br />
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]<br />
* [[How to use RegisterPragmaRefCallBack() | Util/C++: How to use RegisterPragmaRefCallBack()]]<br />
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]<br />
* [[Extract clock enable | Database/C++: Extract clock enable]]<br />
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]<br />
* [[Finding hierarchical paths of a Netlist | Database/C++: Finding hierarchical paths of a Netlist]]<br />
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]<br />
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]<br />
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]<br />
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]<br />
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]<br />
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]<br />
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]<br />
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]<br />
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]<br />
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]<br />
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]<br />
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]<br />
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]<br />
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]<br />
* [[Type Range example | Verilog/C++: Type Range example (simple)]]<br />
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]<br />
* [[How to ignore certain modules while analyzing input RTL files | Verilog/C++: How to ignore certain modules while analyzing input RTL files]]<br />
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]<br />
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]] <br />
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]<br />
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]<br />
* [[In Verilog parsetree adding names to unnamed instances | Verilog/C++: In Verilog parsetree adding names to unnamed instances]]<br />
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]<br />
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]<br />
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]<br />
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]<br />
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]<br />
* [[Parse select modules only and ignore the rest | Verilog/C++: Parse select modules only and ignore the rest]]<br />
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]<br />
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]<br />
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]<br />
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]<br />
* [[Evaluate 'for-generate' loop | Verilog/C++: Evaluate 'for-generate' loop]]<br />
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]<br />
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]<br />
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]<br />
* [[Simple examples of VHDL visitor pattern | VHDL/C++: Simple examples of VHDL visitor pattern]]<br />
* [[Traverse instances in parsetree | VHDL/C++: Traverse instances in parsetree]]<br />
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]</div>Vincehttps://www.verific.com/faq/index.php?title=Modules/design_units_with_%22_default%22_suffix_in_their_names&diff=861Modules/design units with " default" suffix in their names2023-10-23T15:29:19Z<p>Vince: </p>
<hr />
<div>'''Q: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they? '''<br />
<br />
Static elaboration process is a multiple-iteration process and modules/design units may be modified differently in each iteration.<br />
<br />
We need to keep original version of modules/design units as they are immediately after analysis so that they can be copied for different parameter/generic settings in each iteration and body of copied modules/design units can be elaborated (generate unroll, array instance processing, etc.) differently for each parameter/generic setting.<br />
<br />
Another reason to copy instantiated modules/design units with "_default" name is in mixed language elaboration. Here a Verilog module may instantiate a VHDL entity which has been elaborated earlier with different generic values. In that case during Verilog elaboration we will not get original contents of instantiated entity.<br />
<br />
Moreover, to support incremental elaboration we need to keep original modules/design units, as lower level units can be elaborated earlier.<br />
<br />
In Verilog, we have a runtime-flag "veri_remove_suffix_default_from_copied_module_names" to rename modules from "<orig_name>_default" to "<orig_name>". This will work only when runtime-flag "veri_cleanup_base_modules" is set.<br />
<br />
<br />
'''Q: What about interfaces with "_default" suffix in their names? Why? And what are they? '''<br />
<br />
Interfaces can be used in any of the following ways :<br />
<br />
* As interface instantiations.<br />
* As interface ports.<br />
* As virtual interfaces.<br />
* As hierarchical names.<br />
<br />
If an interface is used in a virtual interface declaration, interface instance, or port of a top-level module, the interface will be copied to '<interface_name>_default', even if none of its parameters are overwritten. This copied interface will be the one that is elaborated and specified in the virtual interface declaration, interface instance, or top-level module port. Every instantiated module containing interface type ports will also be copied during static elaboration since its interface port names may have been modified as well.<br />
<br />
Virtual interfaces can appear in many different parts of a design, and may or may not be associated with interface instances. Virtual interfaces are not stored in Verific's pseudo-tree, so after static elaboration we do not know whether an interface is used as a virtual interface or not, or where it is being used. Without this knowledge, we cannot arbitrarily change all the references of an interface from '<interface_name>_default' to '<interface_name> because the references may become invalid. Because of this, we do not have flags to remove the '_default' from the interface names as we do for modules.<br />
<br />
The '_default_<n>' suffix may also be added due to the presence of hierarchical references in an interface or bind statements containing interface instantiations.</div>Vincehttps://www.verific.com/faq/index.php?title=Instance_-_Module_binding_order&diff=839Instance - Module binding order2023-04-19T18:04:10Z<p>Vince: </p>
<hr />
<div>'''Q: Verilog has many ways to find modules not in the file being directly read: -L, -v, -y, .... There may be more than one module of the same name. What is the order of binding?'''<br />
<br />
The order of searching for modules is:<br />
<br />
# While parsing:<br />
## `uselib<br />
## -work (present working library)<br />
## -L<br />
## -y/-v (their order in an f-file is considered)<br />
# While elaborating:<br />
## configurations<br />
## already resolved module from analysis, ie, order of parsing (above)</div>Vincehttps://www.verific.com/faq/index.php?title=Compile-time/run-time_flags&diff=836Compile-time/run-time flags2023-03-03T03:31:58Z<p>Vince: </p>
<hr />
<div>'''Q: Are there options to control Verific software's behavior?'''<br />
<br />
There are compile-time flags and run-time flags ([https://www.verific.com/faq/index.php?title=Compile-time/run-time_flags Verific Runtime Flags]) to control Verific software's behavior. <br />
<br />
When compile-time flags are changed, it will be necessary to rebuild the software for the flags to take effect. These flags reside in the following files:<br />
<br />
database/DBCompileFlags.h<br />
hdl_file_sort/HdlFileSortCompileFlags.h<br />
synlib/SynlibCompileFlags.h<br />
util/VerificSystem.h<br />
verilog_nl/VeriNetlistCompileFlags.h<br />
verilog/VeriCompileFlags.h<br />
vhdl/VhdlCompileFlags.h<br />
<br />
If the behavior of the software needs to be changed dynamically, this can be accomplished using run-time flags. With run-time flags, toggling of behavior can occur at any time without requiring re-compilation of the software. In most cases setting a flag to '1' will enable it and setting to '0' will disable it, although there are some flags that may take on other values, such as 'veri_loop_limit' = 10000, and 'db_record_naming_style' = "%s.%s". Run-time flags reside in the following files:<br />
<br />
database/DBRuntimeFlags.h<br />
edif/EdifRuntimeFlags.h<br />
hier_tree/HierRuntimeFlags.h<br />
pct/PCTRuntimeFlags.h<br />
synlib/SynlibRuntimeFlags.h<br />
upf/UpfRuntimeFlags.h<br />
util/RuntimeFlags.cpp<br />
verilog_nl/VeriNetlistRuntimeFlags.h<br />
verilog/VeriRuntimeFlags.h<br />
vhdl/VhdlRuntimeFlags.h<br />
<br />
Note that depending on your Verific product configuration, you may or may not have all the files listed above. Also, most of the compile-time flags have an equivalent run-time flag to facilitate toggling of the desired behavior. For a full list of Verific's run-time flags with descriptions of their functionality, please refer to this page: [https://www.verific.com/docs/index.php?title=RuntimeFlags Verific Runtime Flags]<br />
<br />
For C++, use the following APIs to control the run-time flags:<br />
<nowiki><br />
RuntimeFlags::SetVar() - Set a run-time flag to a particular value (value is a non-negative integer or 0) <br />
RuntimeFlags::GetVar() - Get the value of a run-time flag (for flags that return a non-negative integer or 0)<br />
RuntimeFlags::SetStringVar() - Set a run-time flag to a particular string value <br />
RuntimeFlags::GetStringVar() - Get the value of a run-time flag (for flags that return a string value) <br />
</nowiki><br />
<br />
Below are examples on how to call these APIs:<br />
<nowiki><br />
RuntimeFlags::SetVar("veri_preserve_comments", 1) ; // enable flag 'veri_preserve_comments' <br />
RuntimeFlags::GetVar("veri_preserve_comments") ; // retrieve the value of 'veri_preserve_comments'<br />
RuntimeFlags::SetStringVar("db_interface_modport_field_separator", "_") ; // set "db_interface_modport_field_separator" to be "_" <br />
RuntimeFlags::GetStringVar("db_array_naming_style") ; // retrieve the value of 'db_array_naming_style' <br />
</nowiki><br />
<br />
For Tcl scripting, use the following commands to control the run-time flags:<br />
<nowiki><br />
set_runtime_flag - Set a run-time flag to a particular value <br />
get_runtime_flag - Get the value of a run-time flag <br />
</nowiki><br />
<br />
Below are examples on how to call these commands:<br />
<nowiki><br />
set_runtime_flag "db_array_naming_style" "%s\[%d\]" <br />
get_runtime_flag "veri_preserve_comments" <br />
</nowiki></div>Vincehttps://www.verific.com/faq/index.php?title=Compile-time/run-time_flags&diff=835Compile-time/run-time flags2023-03-03T03:19:09Z<p>Vince: </p>
<hr />
<div>'''Q: Are there options to control Verific software's behavior?'''<br />
<br />
There are compile-time flags and run-time flags to control Verific software's behavior.<br />
<br />
When compile-time flags are changed, it will be necessary to rebuild the software for the flags to take effect. These flags reside in the following files:<br />
<br />
database/DBCompileFlags.h<br />
hdl_file_sort/HdlFileSortCompileFlags.h<br />
synlib/SynlibCompileFlags.h<br />
util/VerificSystem.h<br />
verilog_nl/VeriNetlistCompileFlags.h<br />
verilog/VeriCompileFlags.h<br />
vhdl/VhdlCompileFlags.h<br />
<br />
If the behavior of the software needs to be changed dynamically, this can be accomplished using run-time flags. With run-time flags, toggling of behavior can occur at any time without requiring re-compilation of the software. In most cases setting a flag to '1' will enable it and setting to '0' will disable it, although there are some flags that may take on other values, such as 'veri_loop_limit' = 10000, and 'db_record_naming_style' = "%s.%s". Run-time flags reside in the following files:<br />
<br />
database/DBRuntimeFlags.h<br />
edif/EdifRuntimeFlags.h<br />
hier_tree/HierRuntimeFlags.h<br />
pct/PCTRuntimeFlags.h<br />
synlib/SynlibRuntimeFlags.h<br />
upf/UpfRuntimeFlags.h<br />
util/RuntimeFlags.cpp<br />
verilog_nl/VeriNetlistRuntimeFlags.h<br />
verilog/VeriRuntimeFlags.h<br />
vhdl/VhdlRuntimeFlags.h<br />
<br />
Note that depending on your Verific product configuration, you may or may not have all the files listed above. Also, most of the compile-time flags have an equivalent run-time flag to facilitate toggling of the desired behavior. For a full list of Verific's run-time flags with descriptions of their functionality, please refer to this page: [https://www.verific.com/docs/index.php?title=RuntimeFlags Verific Runtime Flags]<br />
<br />
For C++, use the following APIs to control the run-time flags:<br />
<nowiki><br />
RuntimeFlags::SetVar() - Set a run-time flag to a particular value (value is a non-negative integer or 0) <br />
RuntimeFlags::GetVar() - Get the value of a run-time flag (for flags that return a non-negative integer or 0)<br />
RuntimeFlags::SetStringVar() - Set a run-time flag to a particular string value <br />
RuntimeFlags::GetStringVar() - Get the value of a run-time flag (for flags that return a string value) <br />
</nowiki><br />
<br />
Below are examples on how to call these APIs:<br />
<nowiki><br />
RuntimeFlags::SetVar("veri_preserve_comments", 1) ; // enable flag 'veri_preserve_comments' <br />
RuntimeFlags::GetVar("veri_preserve_comments") ; // retrieve the value of 'veri_preserve_comments'<br />
RuntimeFlags::SetStringVar("db_interface_modport_field_separator", "_") ; // set "db_interface_modport_field_separator" to be "_" <br />
RuntimeFlags::GetStringVar("db_array_naming_style") ; // retrieve the value of 'db_array_naming_style' <br />
</nowiki><br />
<br />
For Tcl scripting, use the following commands to control the run-time flags:<br />
<nowiki><br />
set_runtime_flag - Set a run-time flag to a particular value <br />
get_runtime_flag - Get the value of a run-time flag <br />
</nowiki><br />
<br />
Below are examples on how to call these commands:<br />
<nowiki><br />
set_runtime_flag "db_array_naming_style" "%s\[%d\]" <br />
get_runtime_flag "veri_preserve_comments" <br />
</nowiki></div>Vincehttps://www.verific.com/faq/index.php?title=Compile-time/run-time_flags&diff=834Compile-time/run-time flags2023-03-03T03:11:49Z<p>Vince: </p>
<hr />
<div>'''Q: Are there options to control Verific software's behavior?'''<br />
<br />
There are compile-time flags and run-time flags to control Verific software's behavior.<br />
<br />
When compile-time flags are changed, it will be necessary to rebuild the software for the flags to take effect. These flags reside in the following files:<br />
<br />
database/DBCompileFlags.h<br />
hdl_file_sort/HdlFileSortCompileFlags.h<br />
synlib/SynlibCompileFlags.h<br />
util/VerificSystem.h<br />
verilog_nl/VeriNetlistCompileFlags.h<br />
verilog/VeriCompileFlags.h<br />
vhdl/VhdlCompileFlags.h<br />
<br />
If the behavior of the software needs to be changed dynamically, this can be accomplished using run-time flags. With run-time flags, toggling of behavior can occur at any time without requiring re-compilation of the software. In most cases setting a flag to '1' will enable it and setting to '0' will disable it, although there are some flags that may take on other values, such as 'veri_loop_limit' = 10000, and 'db_record_naming_style' = "%s.%s". Run-time flags reside in the following files:<br />
<br />
database/DBRuntimeFlags.h<br />
edif/EdifRuntimeFlags.h<br />
hier_tree/HierRuntimeFlags.h<br />
pct/PCTRuntimeFlags.h<br />
synlib/SynlibRuntimeFlags.h<br />
upf/UpfRuntimeFlags.h<br />
util/RuntimeFlags.cpp<br />
verilog_nl/VeriNetlistRuntimeFlags.h<br />
verilog/VeriRuntimeFlags.h<br />
vhdl/VhdlRuntimeFlags.h<br />
<br />
Note that depending on your Verific product configuration, you may or may not have all the files listed above. Also, most of the compile-time flags have an equivalent run-time flag to facilitate toggling of the desired behavior. For a full list of Verific's run-time flags with descriptions of their functionality, please refer to this page: [https://www.verific.com/docs/index.php?title=RuntimeFlags Verific Runtime Flags]<br />
<br />
For C++, use the following APIs to control the run-time flags:<br />
<nowiki><br />
RuntimeFlags::SetVar() - Set a run-time flag to a particular value (value is a non-negative integer or 0) <br />
RuntimeFlags::GetVar() - Get the value of a run-time flag (for flags that return a non-negative integer or 0)<br />
RuntimeFlags::SetStringVar() - Set a run-time flag to a particular string value <br />
RuntimeFlags::GetStringVar() - Get the value of a run-time flag (for flags that return a string value) <br />
</nowiki><br />
<br />
Below are some examples on how to call these APIs:<br />
<nowiki><br />
RuntimeFlags::SetVar("veri_preserve_comments", 1) ; // enable flag 'veri_preserve_comments' <br />
RuntimeFlags::GetVar("veri_preserve_comments") ; // retrieve the value of 'veri_preserve_comments'<br />
RuntimeFlags::SetStringVar("db_interface_modport_field_separator", "_") ; // set "db_interface_modport_field_separator" to be "_" <br />
RuntimeFlags::GetStringVar("db_array_naming_style") ; // retrieve the value of 'db_array_naming_style' <br />
</nowiki><br />
<br />
For Tcl scripting, use the following commands to control the run-time flags:<br />
<nowiki><br />
set_runtime_flag - Set a run-time flag to a particular value <br />
get_runtime_flag - Get the value of a run-time flag <br />
</nowiki><br />
<br />
Below are some examples on how to call these commands:<br />
<nowiki><br />
set_runtime_flag "db_array_naming_style" "%s\[%d\]" <br />
get_runtime_flag "veri_preserve_comments" <br />
</nowiki></div>Vincehttps://www.verific.com/faq/index.php?title=Compile-time/run-time_flags&diff=833Compile-time/run-time flags2023-03-03T03:05:28Z<p>Vince: </p>
<hr />
<div>'''Q: Are there options to control Verific software's behavior?'''<br />
<br />
There are compile-time flags and run-time flags to control Verific software's behavior.<br />
<br />
When compile-time flags are changed, it will be necessary to rebuild the software for the flags to take effect. These flags reside in the following files:<br />
<br />
database/DBCompileFlags.h<br />
hdl_file_sort/HdlFileSortCompileFlags.h<br />
synlib/SynlibCompileFlags.h<br />
util/VerificSystem.h<br />
verilog_nl/VeriNetlistCompileFlags.h<br />
verilog/VeriCompileFlags.h<br />
vhdl/VhdlCompileFlags.h<br />
<br />
If the behavior of the software needs to be changed dynamically, this can be accomplished using run-time flags. With run-time flags, toggling of behavior can occur at any time without requiring re-compilation of the software. In most cases setting a flag to '1' will enable it and setting to '0' will disable it, although there are some flags that may take on other values, such as 'veri_loop_limit' = 10000, and 'db_record_naming_style' = "%s.%s". Run-time flags reside in the following files:<br />
<br />
database/DBRuntimeFlags.h<br />
edif/EdifRuntimeFlags.h<br />
hier_tree/HierRuntimeFlags.h<br />
pct/PCTRuntimeFlags.h<br />
synlib/SynlibRuntimeFlags.h<br />
upf/UpfRuntimeFlags.h<br />
util/RuntimeFlags.cpp<br />
verilog_nl/VeriNetlistRuntimeFlags.h<br />
verilog/VeriRuntimeFlags.h<br />
vhdl/VhdlRuntimeFlags.h<br />
<br />
Note that depending on your Verific product configuration, you may or may not have all the files listed above. Also, most of the compile-time flags have an equivalent run-time flag to facilitate toggling of the desired behavior. For a full list of Verific's run-time flags with descriptions of their functionality, please refer to this page: [https://www.verific.com/docs/index.php?title=RuntimeFlags Verific Runtime Flags]<br />
<br />
For C++, use the following APIs to control the run-time flags:<br />
<nowiki><br />
RuntimeFlags::SetVar() - Set a run-time flag to a particular value (value is a non-negative integer or 0) <br />
RuntimeFlags::GetVar() - Get the value of a run-time flag (for flags that return a non-negative integer or 0)<br />
RuntimeFlags::SetStringVar() - Set a run-time flag to a particular string value <br />
RuntimeFlags::GetStringVar() - Get the value of a run-time flag (for flags that return a string value) <br />
</nowiki><br />
<br />
Below are some examples on how to call these APIs:<br />
<nowiki><br />
RuntimeFlags::SetVar("veri_preserve_comments", 1) ; // enable flag 'veri_preserve_comments' <br />
RuntimeFlags::GetVar("veri_preserve_comments") ; // retrieve the value of 'veri_preserve_comments'<br />
RuntimeFlags::SetStringVar("db_interface_modport_field_separator", "_") ; // set "db_interface_modport_field_separator" to be "_" <br />
RuntimeFlags::GetStringVar("db_array_naming_style") ; // retrieve the value of 'db_array_naming_style' <br />
</nowiki><br />
<br />
<br />
For Tcl scripting, use the following commands to control the run-time flags:<br />
<nowiki><br />
set_runtime_flag - Set a run-time flag to a particular value <br />
get_runtime_flag - Get the value of a run-time flag <br />
</nowiki><br />
<br />
Below are some examples on how to call these commands:<br />
<nowiki><br />
set_runtime_flag "db_array_naming_style" "%s\[%d\]" <br />
get_runtime_flag "veri_preserve_comments" <br />
</nowiki></div>Vincehttps://www.verific.com/faq/index.php?title=How_to_ignore_parameters/generics_in_elaboration&diff=830How to ignore parameters/generics in elaboration2023-02-17T18:14:08Z<p>Vince: </p>
<hr />
<div>'''Q:Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?'''<br />
<br />
Specific parameters/generics of specific modules/units can be ignored during elaboration. Related APIs are:<br />
<br />
vhdl_file::GetIgnoreGeneric()<br />
vhdl_file::SetIgnoreGeneric()<br />
vhdl_file::RemoveAllIgnoreGeneric()<br />
<br />
veri_file::GetIgnoreParameter()<br />
veri_file::SetIgnoreParameter()<br />
veri_file::RemoveAllIgnoreParameter()<br />
<br />
Below is an example as how to ignore all parameters in a library:<br />
<br />
<nowiki><br />
veri_file::AnalyzeMultipleFiles(veri_files, veri_file::SYSTEM_VERILOG, "work", veri_file::MFCU);<br />
<br />
/*** Go through library "work" in the parsetree,<br />
find all parameters,<br />
and set "ignored" on all of them.<br />
Or you can select the parameters to ignore ***/<br />
MapIter mi;<br />
VeriModule *module ;<br />
VeriLibrary *work_lib = veri_file::GetLibrary("work", 1);<br />
<br />
FOREACH_VERILOG_MODULE_IN_LIBRARY (work_lib, mi, module) { // do this for each module<br />
if (!module) continue;<br />
Array *parameters = module->GetParameters(); // collect all parameters<br />
if (!parameters) continue;<br />
unsigned i;<br />
VeriIdDef *param_id;<br />
FOREACH_ARRAY_ITEM(parameters, i, param_id) { // do this for each parameter of the module<br />
if (!param_id) continue;<br />
veri_file::SetIgnoreParameter(work_lib->GetName(), module->Name(), param_id->Name());<br />
}<br />
}<br />
<br />
if (!veri_file::Elaborate("top", "work", 0)) {<br />
return 1 ;<br />
}<br />
</nowiki></div>Vincehttps://www.verific.com/faq/index.php?title=Pretty-print_a_module_and_the_packages_imported_by_the_module&diff=805Pretty-print a module and the packages imported by the module2022-09-23T00:08:11Z<p>Vince: </p>
<hr />
<div>C++:<br />
<nowiki><br />
#include <iostream><br />
#include <fstream><br />
<br />
#include "veri_file.h"<br />
#include "VeriModule.h"<br />
#include "VeriId.h"<br />
#include "VeriScope.h"<br />
<br />
#include "Map.h"<br />
<br />
using namespace std ;<br />
<br />
#ifdef VERIFIC_NAMESPACE<br />
using namespace Verific ;<br />
#endif<br />
<br />
int main(int argc, const char **argv)<br />
{<br />
const char *file = (argc > 1) ? argv[1] : "test.sv" ;<br />
<br />
// Analyze the files (AnalyzeMultipleFiles API is the recommended one):<br />
Array files(1) ;<br />
files.InsertLast(file) ;<br />
if (!veri_file::AnalyzeMultipleFiles(&files, veri_file::SYSTEM_VERILOG)) return 1 ;<br />
<br />
MapIter mi ;<br />
VeriModule *module ;<br />
FOREACH_VERILOG_MODULE(mi, module){<br />
if (!module) continue ;<br />
if (module->IsPackage()) continue ; // no need to dive into package<br />
<br />
// Get the scope of the module:<br />
VeriScope *scope = module->GetScope() ;<br />
<br />
char *outputfilename = Strings::save(module->Name(), "_pp_out.v");<br />
std::ofstream f(outputfilename, std::ios::out) ;<br />
<br />
// Get the scope that this module/scope is using:<br />
// This also includes the compilation unit in the list, if any/required:<br />
Set *using_scopes = (scope) ? scope->GetUsing() : 0 ;<br />
<br />
// Print all those scopes/modules before printing the module itself:<br />
SetIter si ;<br />
VeriScope *using_scope ;<br />
FOREACH_SET_ITEM(using_scopes, si, &using_scope) {<br />
VeriIdDef *mod_id = using_scope->GetContainingModule() ;<br />
VeriModule *mod = (mod_id) ? mod_id->GetModule() : 0 ;<br />
if (!mod) continue ;<br />
if (mod->IsPackage()) {<br />
std::cout << ">>> Module '" << module->Name() << "' uses package '" << mod->Name() << "' <<<\n";<br />
}<br />
f << "// Printing package " << mod->Name() << endl ;<br />
mod->PrettyPrint(f, 0) ;<br />
}<br />
<br />
// Now print the module:<br />
f << "// Printing module " << module->Name() << endl ;<br />
module->PrettyPrint(f, 0) ;<br />
f.close() ;<br />
}<br />
<br />
return 0 ;<br />
}<br />
</nowiki><br />
<br />
Input Verilog:<br />
<nowiki><br />
package PKG1 ;<br />
typedef int my_int ;<br />
endpackage<br />
<br />
typedef byte my_byte ;<br />
<br />
module test ;<br />
import PKG1::* ;<br />
my_int int1 ;<br />
my_byte byte1 ;<br />
endmodule<br />
</nowiki><br />
<br />
Pretty-printed output:<br />
<nowiki><br />
// Printing package PKG1<br />
<br />
package PKG1 ;<br />
typedef int my_int ;<br />
endpackage<br />
<br />
<br />
// Printing package $unit_test_sv<br />
<br />
typedef byte my_byte ;<br />
<br />
<br />
// Printing module test<br />
<br />
module test ;<br />
import PKG1:: * ;<br />
my_int int1 ;<br />
my_byte byte1 ;<br />
endmodule<br />
</nowiki></div>Vincehttps://www.verific.com/faq/index.php?title=Python_pretty-printer_for_gdb&diff=804Python pretty-printer for gdb2022-09-13T18:28:27Z<p>Vince: </p>
<hr />
<div>If gdb (GNU debugger) was compiled with Python support, it is possible to run Python scripts from within gdb. Below is an example of how to create a custom pretty-printer for Verific's VeriTreeNode using gdb's Python interface.<br />
<br />
The Python script itself looks like this<br />
<nowiki><br />
import gdb<br />
import re<br />
<br />
class VeriVhdlTreeNodePrinter:<br />
def __init__(self, val):<br />
self.val = val<br />
<br />
def to_string(self):<br />
eval_string = f"(({self.val.type.name}*){self.val.address})->GetPrettyPrintedString()"<br />
return gdb.parse_and_eval(eval_string).string()<br />
<br />
def verific_pp_func(val):<br />
lookup_tag = val.type.tag<br />
if lookup_tag is None:<br />
return None<br />
<br />
regex = re.compile("^(Verific::)?(Veri|Vhdl)(\w)+$")<br />
if regex.match(lookup_tag):<br />
return VeriVhdlTreeNodePrinter(val)<br />
return None<br />
<br />
gdb.pretty_printers.append(verific_pp_func)<br />
</nowiki><br />
To automate sourcing of the Python script on gdb startup, add the following line to your ~/.gdbinit :<br />
<br />
source ~/verific_pp.py<br />
<br />
The script calls Verific's GetPrettyPrintedString() API which essentially pretty prints the VeriTreeNode. It takes an object and not a pointer. Printing the pointer will still print the value of the pointer as per usual gdb behavior.<br />
<br />
Note that if a class has a name starting with Veri but is not derived from VeriTreeNode, gdb produces the following message :<br />
<br />
(gdb) print *pointer_to_VeriLibrary_which_is_not_derived_from_VeriTreeNode<br />
$2 = Python Exception <class 'gdb.error'> Couldn't find method VeriLibrary::GetPrettyPrintedString:<br />
(gdb)<br />
<br />
The same will happen for VeriValue/VhdlValue/VeriBaseValue, etc, because these classes do not have the GetPrettyPrintedString() API. The pretty printer can be customized to exclude such classes, or modified to handle these other cases. This is just a regular regex rule.<br />
<br />
Here is the output from an example run :<br />
<nowiki><br />
gdb ./test-linux-g<br />
Reading symbols from test-linux-g...<br />
(gdb) break 62<br />
Breakpoint 1 at 0x306b50: file test.cpp, line 62.<br />
(gdb) run<br />
Starting program: test-linux-g<br />
[Thread debugging using libthread_db enabled]<br />
Using host libthread_db library "/lib/x86_64-linux-gnu/libthread_db.so.1".<br />
-- Analyzing Verilog file 'test.v' (VERI-1482)<br />
test.v(1): INFO: compiling module 'top' (VERI-1018)<br />
-- module: top<br />
-- param: P1<br />
-- initial expression: 8<br />
<br />
Breakpoint 1, main (argc=1, argv=0x7fffffffe0b8) at test.cpp:62<br />
62 Message::PrintLine(" initial value: ", Strings::itoa(int_val)) ;<br />
(gdb) p *module_item<br />
$1 = {<Verific::VeriTreeNode> = {<Verific::VeriNode> = {<br />
_vptr.VeriNode = 0x5555565bcd18 <vtable for Verific::VeriDataDecl+16>, static _present_scope = 0x0,<br />
static _container_scope_arr = 0x0, static _sva_clock_expr = 0x0, static _default_clock = 0x0,<br />
static _default_disable_iff_cond = 0x0, static _has_disable_iff = 0, static _id_ref = 0x0,<br />
static _name_list = 0x0, static _inside_clocked_sequence = 0, static _contains_event_control = 0,<br />
static _contains_delay_control = 0, static _contains_even_id_in_body = 0, static _multiple_inferred_clock = 0,<br />
static _in_property_expr = 0, static _in_checker = 0, static _in_fork_join_none_or_any = 0,<br />
static _in_bind_directive = 0, static _hier_name_to_allow_mod_name = 0, static _do_not_recurse_packed_dims = 0,<br />
static _processing_param = 0x0, static _processing_expr = 0x0, static _msgs = 0x55555666b870,<br />
static _relaxed_msgs = 0x0, static _udp_edge_chars = 0x0, static _verilog_keywords = 0x0,<br />
static _verilog_tokens = 0x0, static _system_tasks = 0x0, static _ref_count_map = 0x0,<br />
static _attribute_map = 0x0, static _map_of_comment_arr = 0x0, static _global_clocking = 0x0,<br />
static _var_usage_running = 0, static _is_static_elab = 0, static _is_rtl_elab = 0,<br />
static _func_pointer_stack = 0x0, static _func_stack = 0x0, static _mutual_recursion_count = 0,<br />
static _max_mutual_recursion_count = 0, static _within_seq_area = 0, static _within_generate_endgenerate = 0,<br />
static _under_default_clock = 0, static _default_disable_defined = 0, static _has_delay_or_event_control = 0,<br />
static _processing_operand = 0, static _potential_always_loop = 0, static _reresolve_idrefs = 0,<br />
static _ignore_ams_in_rtl_elab = 0, static _follow_lrm_for_constant_func = 0, static _evaluated_vals = 0x0,<br />
static _evaluated_constraints = 0x0, static _p_evaluated_vals = 0x0, static _p_evaluated_constraints = 0x0,<br />
static _unnamedscope_vs_decl_ids = 0x0, static _check_linefile_of_import = 1}, _linefile = 8589934594},<br />
_qualifiers = 0}<br />
(gdb) p *val<br />
$2 = {_vptr.VeriBaseValue = 0x55555654b280 <vtable for Verific::VeriInteger+16>}<br />
(gdb) source verific_pp.py<br />
(gdb) p *module_item<br />
$3 = parameter P1 = 8 ;<br />
<br />
(gdb) p *val<br />
$4 = 8<br />
(gdb)<br />
</nowiki><br />
Notice how before activating the Python pretty-printer, gdb prints out a lot of information when calling 'p *module_item' or 'p *val' . With the pretty-printer, it now prints only the value from GetPrettyPrintedString().</div>Vincehttps://www.verific.com/faq/index.php?title=Python_pretty-printer_for_gdb&diff=803Python pretty-printer for gdb2022-09-13T18:10:28Z<p>Vince: </p>
<hr />
<div>If gdb (GNU debugger) was compiled with Python support, it is possible to run Python scripts from within gdb. Below is an example of how to create a custom pretty-printer for Verific's VeriTreeNode using gdb's Python interface.<br />
<br />
The Python script itself looks like this<br />
<nowiki><br />
import gdb<br />
import re<br />
<br />
class VeriVhdlTreeNodePrinter:<br />
def __init__(self, val):<br />
self.val = val<br />
<br />
def to_string(self):<br />
eval_string = f"(({self.val.type.name}*){self.val.address})->GetPrettyPrintedString()"<br />
return gdb.parse_and_eval(eval_string).string()<br />
<br />
def verific_pp_func(val):<br />
lookup_tag = val.type.tag<br />
if lookup_tag is None:<br />
return None<br />
<br />
regex = re.compile("^(Verific::)?(Veri|Vhdl)(\w)+$")<br />
if regex.match(lookup_tag):<br />
return VeriVhdlTreeNodePrinter(val)<br />
return None<br />
<br />
gdb.pretty_printers.append(verific_pp_func)<br />
</nowiki><br />
To automate sourcing of the Python script on gdb startup, add the following line to your ~/.gdbinit :<br />
<br />
source ~/verific_pp.py<br />
<br />
The script calls Verific's GetPrettyPrintedString() API which essentially pretty prints the VeriTreeNode. It takes an object and not a pointer. Printing the pointer will still print the value of the pointer as per usual gdb behavior.<br />
<br />
Note that if a class has a name starting with Veri but is not derived from VeriTreeNode, gdb produces the following message :<br />
<br />
(gdb) print *pointer_to_VeriLibrary_which_is_not_derived_from_VeriTreeNode<br />
$2 = Python Exception <class 'gdb.error'> Couldn't find method VeriLibrary::GetPrettyPrintedString:<br />
(gdb)<br />
<br />
The same will happen for VeriValue/VhdlValue/VeriBaseValue, etc, because these classes do not have the GetPrettyPrintedString() API. The pretty printer can be customized to exclude such classes, or modified to handle these other cases. This is just a regular regex rule.<br />
<br />
Here is the output from an example run :<br />
<nowiki><br />
gdb ./test-linux-g<br />
Reading symbols from test-linux-g...<br />
(gdb) break 62<br />
Breakpoint 1 at 0x306b50: file test.cpp, line 62.<br />
(gdb) run<br />
Starting program: test-linux-g<br />
[Thread debugging using libthread_db enabled]<br />
Using host libthread_db library "/lib/x86_64-linux-gnu/libthread_db.so.1".<br />
-- Analyzing Verilog file 'test.v' (VERI-1482)<br />
test.v(1): INFO: compiling module 'top' (VERI-1018)<br />
-- module: top<br />
-- param: P1<br />
-- initial expression: 8<br />
<br />
Breakpoint 1, main (argc=1, argv=0x7fffffffe0b8) at test.cpp:62<br />
62 Message::PrintLine(" initial value: ", Strings::itoa(int_val)) ;<br />
(gdb) '''p *module_item'''<br />
$1 = {<Verific::VeriTreeNode> = {<Verific::VeriNode> = {<br />
_vptr.VeriNode = 0x5555565bcd18 <vtable for Verific::VeriDataDecl+16>, static _present_scope = 0x0,<br />
static _container_scope_arr = 0x0, static _sva_clock_expr = 0x0, static _default_clock = 0x0,<br />
static _default_disable_iff_cond = 0x0, static _has_disable_iff = 0, static _id_ref = 0x0,<br />
static _name_list = 0x0, static _inside_clocked_sequence = 0, static _contains_event_control = 0,<br />
static _contains_delay_control = 0, static _contains_even_id_in_body = 0, static _multiple_inferred_clock = 0,<br />
static _in_property_expr = 0, static _in_checker = 0, static _in_fork_join_none_or_any = 0,<br />
static _in_bind_directive = 0, static _hier_name_to_allow_mod_name = 0, static _do_not_recurse_packed_dims = 0,<br />
static _processing_param = 0x0, static _processing_expr = 0x0, static _msgs = 0x55555666b870,<br />
static _relaxed_msgs = 0x0, static _udp_edge_chars = 0x0, static _verilog_keywords = 0x0,<br />
static _verilog_tokens = 0x0, static _system_tasks = 0x0, static _ref_count_map = 0x0,<br />
static _attribute_map = 0x0, static _map_of_comment_arr = 0x0, static _global_clocking = 0x0,<br />
static _var_usage_running = 0, static _is_static_elab = 0, static _is_rtl_elab = 0,<br />
static _func_pointer_stack = 0x0, static _func_stack = 0x0, static _mutual_recursion_count = 0,<br />
static _max_mutual_recursion_count = 0, static _within_seq_area = 0, static _within_generate_endgenerate = 0,<br />
static _under_default_clock = 0, static _default_disable_defined = 0, static _has_delay_or_event_control = 0,<br />
static _processing_operand = 0, static _potential_always_loop = 0, static _reresolve_idrefs = 0,<br />
static _ignore_ams_in_rtl_elab = 0, static _follow_lrm_for_constant_func = 0, static _evaluated_vals = 0x0,<br />
static _evaluated_constraints = 0x0, static _p_evaluated_vals = 0x0, static _p_evaluated_constraints = 0x0,<br />
static _unnamedscope_vs_decl_ids = 0x0, static _check_linefile_of_import = 1}, _linefile = 8589934594},<br />
_qualifiers = 0}<br />
(gdb) '''p *val'''<br />
$2 = {_vptr.VeriBaseValue = 0x55555654b280 <vtable for Verific::VeriInteger+16>}<br />
(gdb) '''source verific_pp.py'''<br />
(gdb) '''p *module_item'''<br />
$3 = parameter P1 = 8 ;<br />
<br />
(gdb) '''p *val'''<br />
$4 = 8<br />
(gdb)<br />
</nowiki><br />
Notice how before activating the Python pretty-printer, gdb prints out a lot of information when calling 'p *module_item' or 'p *val' . With the pretty-printer, it now prints only the value from GetPrettyPrintedString().</div>Vincehttps://www.verific.com/faq/index.php?title=Python_pretty-printer_for_gdb&diff=802Python pretty-printer for gdb2022-09-13T18:06:21Z<p>Vince: Created page with "If gdb (GNU debugger) was compiled with Python support, it is possible to run Python scripts within gdb. Below is an example of how to create a custom pretty-printer for Veri..."</p>
<hr />
<div>If gdb (GNU debugger) was compiled with Python support, it is possible to run Python scripts within gdb. Below is an example of how to create a custom pretty-printer for Verific's parse tree nodes.<br />
<br />
The Python script itself looks like this<br />
<nowiki><br />
import gdb<br />
import re<br />
<br />
class VeriVhdlTreeNodePrinter:<br />
def __init__(self, val):<br />
self.val = val<br />
<br />
def to_string(self):<br />
eval_string = f"(({self.val.type.name}*){self.val.address})->GetPrettyPrintedString()"<br />
return gdb.parse_and_eval(eval_string).string()<br />
<br />
def verific_pp_func(val):<br />
lookup_tag = val.type.tag<br />
if lookup_tag is None:<br />
return None<br />
<br />
regex = re.compile("^(Verific::)?(Veri|Vhdl)(\w)+$")<br />
if regex.match(lookup_tag):<br />
return VeriVhdlTreeNodePrinter(val)<br />
return None<br />
<br />
gdb.pretty_printers.append(verific_pp_func)<br />
</nowiki><br />
To automate sourcing of the Python script on gdb startup, add the following line to your ~/.gdbinit :<br />
<br />
source ~/verific_pp.py<br />
<br />
The script calls Verific's GetPrettyPrintedString() API which essentially pretty prints the VeriTreeNode. It takes an object and not a pointer. Printing the pointer will still print the value of the pointer as per usual gdb behavior.<br />
<br />
Note that if a class has a name starting with Veri but is not derived from VeriTreeNode, gdb produces the following message :<br />
<br />
(gdb) print *pointer_to_VeriLibrary_which_is_not_derived_from_VeriTreeNode<br />
$2 = Python Exception <class 'gdb.error'> Couldn't find method VeriLibrary::GetPrettyPrintedString:<br />
(gdb)<br />
<br />
The same will happen for VeriValue/VhdlValue/VeriBaseValue, etc, because these classes do not have the GetPrettyPrintedString() API. The pretty printer can be customized to exclude such classes, or modified to handle these other cases. This is just a regular regex rule.<br />
<br />
Here is the output from an example run :<br />
<nowiki><br />
gdb ./test-linux-g<br />
Reading symbols from test-linux-g...<br />
(gdb) break 62<br />
Breakpoint 1 at 0x306b50: file test.cpp, line 62.<br />
(gdb) run<br />
Starting program: test-linux-g<br />
[Thread debugging using libthread_db enabled]<br />
Using host libthread_db library "/lib/x86_64-linux-gnu/libthread_db.so.1".<br />
-- Analyzing Verilog file 'test.v' (VERI-1482)<br />
test.v(1): INFO: compiling module 'top' (VERI-1018)<br />
-- module: top<br />
-- param: P1<br />
-- initial expression: 8<br />
<br />
Breakpoint 1, main (argc=1, argv=0x7fffffffe0b8) at test.cpp:62<br />
62 Message::PrintLine(" initial value: ", Strings::itoa(int_val)) ;<br />
(gdb) '''p *module_item'''<br />
$1 = {<Verific::VeriTreeNode> = {<Verific::VeriNode> = {<br />
_vptr.VeriNode = 0x5555565bcd18 <vtable for Verific::VeriDataDecl+16>, static _present_scope = 0x0,<br />
static _container_scope_arr = 0x0, static _sva_clock_expr = 0x0, static _default_clock = 0x0,<br />
static _default_disable_iff_cond = 0x0, static _has_disable_iff = 0, static _id_ref = 0x0,<br />
static _name_list = 0x0, static _inside_clocked_sequence = 0, static _contains_event_control = 0,<br />
static _contains_delay_control = 0, static _contains_even_id_in_body = 0, static _multiple_inferred_clock = 0,<br />
static _in_property_expr = 0, static _in_checker = 0, static _in_fork_join_none_or_any = 0,<br />
static _in_bind_directive = 0, static _hier_name_to_allow_mod_name = 0, static _do_not_recurse_packed_dims = 0,<br />
static _processing_param = 0x0, static _processing_expr = 0x0, static _msgs = 0x55555666b870,<br />
static _relaxed_msgs = 0x0, static _udp_edge_chars = 0x0, static _verilog_keywords = 0x0,<br />
static _verilog_tokens = 0x0, static _system_tasks = 0x0, static _ref_count_map = 0x0,<br />
static _attribute_map = 0x0, static _map_of_comment_arr = 0x0, static _global_clocking = 0x0,<br />
static _var_usage_running = 0, static _is_static_elab = 0, static _is_rtl_elab = 0,<br />
static _func_pointer_stack = 0x0, static _func_stack = 0x0, static _mutual_recursion_count = 0,<br />
static _max_mutual_recursion_count = 0, static _within_seq_area = 0, static _within_generate_endgenerate = 0,<br />
static _under_default_clock = 0, static _default_disable_defined = 0, static _has_delay_or_event_control = 0,<br />
static _processing_operand = 0, static _potential_always_loop = 0, static _reresolve_idrefs = 0,<br />
static _ignore_ams_in_rtl_elab = 0, static _follow_lrm_for_constant_func = 0, static _evaluated_vals = 0x0,<br />
static _evaluated_constraints = 0x0, static _p_evaluated_vals = 0x0, static _p_evaluated_constraints = 0x0,<br />
static _unnamedscope_vs_decl_ids = 0x0, static _check_linefile_of_import = 1}, _linefile = 8589934594},<br />
_qualifiers = 0}<br />
(gdb) '''p *val'''<br />
$2 = {_vptr.VeriBaseValue = 0x55555654b280 <vtable for Verific::VeriInteger+16>}<br />
(gdb) '''source verific_pp.py'''<br />
(gdb) '''p *module_item'''<br />
$3 = parameter P1 = 8 ;<br />
<br />
(gdb) '''p *val'''<br />
$4 = 8<br />
(gdb)<br />
</nowiki><br />
Notice how before activating the Python pretty-printer, gdb prints out a lot of information when calling 'p *module_item' or 'p *val' . With the pretty-printer, it now prints only the value from GetPrettyPrintedString().</div>Vincehttps://www.verific.com/faq/index.php?title=Main_Page&diff=801Main Page2022-09-13T17:46:17Z<p>Vince: </p>
<hr />
<div>'''General'''<br />
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]<br />
* [[Source code customization & Stable release services | Source code customization & Stable release services]]<br />
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]<br />
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]<br />
* [[Verific data structures | What are the data structures in Verific?]]<br />
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]<br />
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]<br />
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]<br />
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]<br />
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]<br />
* [[Release version | How do I tell the version of a Verific software release? ]]<br />
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]<br />
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]<br />
* [[LineFile data from input files | LineFile data from input files]]<br />
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]<br />
* [[Preserving user nets - preventing nets from being optimized away | Preserving user nets - preventing nets from being optimized away]]<br />
* [[Python pretty-printer for gdb | Python pretty-printer for gdb]]<br />
<br />
'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''<br />
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]<br />
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]<br />
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]<br />
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]<br />
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]<br />
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]<br />
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]<br />
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]<br />
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]<br />
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]<br />
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]<br />
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]<br />
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]<br />
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]<br />
* [[Notes on analysis | SystemVerilog: Notes on analysis]]<br />
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]<br />
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]<br />
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]<br />
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]<br />
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]<br />
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]<br />
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]<br />
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]<br />
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]<br />
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]<br />
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]<br />
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]<br />
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]<br />
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]]<br />
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]<br />
<br />
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]<br />
'''Netlist Database'''<br />
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]<br />
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]<br />
* [[System attributes | Netlist Database: System attributes]]<br />
<br />
'''Output'''<br />
* [[Output file formats | What language formats does Verific support as output?]]<br />
<br />
'''Scripting languages: TCL, Perl, Python'''<br />
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]<br />
<br />
'''Code examples'''<br />
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]<br />
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]<br />
* [[Extract clock enable | Database/C++: Extract clock enable]]<br />
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]<br />
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]<br />
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]<br />
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]<br />
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]<br />
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]<br />
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]<br />
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]<br />
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]<br />
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]<br />
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]<br />
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]<br />
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]<br />
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]<br />
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]<br />
* [[Type Range example | Verilog/C++: Type Range example (simple)]]<br />
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]<br />
* [[How to ignore certain modules while analyzing input RTL files | Verilog/C++: How to ignore certain modules while analyzing input RTL files]]<br />
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]<br />
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]] <br />
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]<br />
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]<br />
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]<br />
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]<br />
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]<br />
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]<br />
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]<br />
* [[Parse select modules only and ignore the rest | Verilog/C++: Parse select modules only and ignore the rest]]<br />
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]<br />
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]<br />
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]<br />
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]<br />
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]<br />
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]<br />
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]<br />
* [[Simple examples of VHDL visitor pattern | VHDL/C++: Simple examples of VHDL visitor pattern]]<br />
* [[Traverse instances in parsetree | VHDL/C++: Traverse instances in parsetree]]<br />
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]</div>Vincehttps://www.verific.com/faq/index.php?title=How_to_get_packed_dimensions_of_enum&diff=785How to get packed dimensions of enum2022-05-12T00:46:26Z<p>Vince: </p>
<hr />
<div>C++:<br />
<nowiki><br />
#include "Array.h"<br />
#include "Map.h"<br />
#include "Set.h"<br />
#include "Message.h"<br />
#include "veri_file.h"<br />
#include "VeriModule.h"<br />
#include "VeriScope.h"<br />
#include "VeriId.h"<br />
#include "VeriExpression.h"<br />
#include "veri_file.h"<br />
#include <iostream><br />
<br />
using namespace std;<br />
#ifdef VERIFIC_NAMESPACE<br />
using namespace Verific ;<br />
#endif<br />
<br />
void GetBaseTypeFromDataType(VeriDataType *);<br />
<br />
int main(int argc, char **argv)<br />
{<br />
veri_file::SetInterfaceModportFieldSeparator("::") ;<br />
<br />
Array file_names;<br />
<br />
if (argc < 2) {<br />
file_names.InsertLast("test.v");<br />
} else {<br />
for (int i = 1; i < argc; i++) {<br />
file_names.InsertLast(argv[i]);<br />
}<br />
}<br />
<br />
Array * file_names_ = new Array( file_names);<br />
<br />
if (!veri_file::AnalyzeMultipleFiles(file_names_, veri_file::SYSTEM_VERILOG, "work", veri_file::MFCU)) {<br />
std::cout << " Unable to analyze multiple files. Aborting\n";<br />
return 1 ;<br />
}<br />
<br />
// Fetching the top module<br />
Array *top_module_array = veri_file::GetTopModules() ;<br />
<br />
if (!top_module_array) {<br />
Message::Error(0, "Cannot find any top module in the design") ;<br />
return 4;<br />
}<br />
<br />
VeriModule *module = (VeriModule *) top_module_array->GetFirst();<br />
<br />
// Creating VPT<br />
module->StaticElaborate( 0);<br />
module->Elaborate( 0, 0, false);<br />
<br />
VeriScope* p_scope = module->GetScope();<br />
Map* scope_map = p_scope->GetThisScope();<br />
MapIter mi ;<br />
VeriIdDef *id;<br />
<br />
FOREACH_MAP_ITEM(scope_map, mi, 0, &id) {<br />
if (!id ) continue;<br />
std::cout << "Handling Declaration: "<< id->Name() << std::endl;<br />
GetBaseTypeFromDataType(id->GetDataType());<br />
}<br />
<br />
return 0;<br />
}<br />
<br />
void GetBaseTypeFromDataType(VeriDataType *p_data_type)<br />
{<br />
if(!p_data_type) {<br />
return;<br />
}<br />
unsigned packed_dim = p_data_type->PackedDimension();<br />
switch( p_data_type->GetClassId() ) {<br />
case ID_VERIDATATYPE: {<br />
std::cout << "===== ID_VERIDATATYPE:: p_data_type->Image() = " << p_data_type->Image() << " =====" << std::endl;<br />
std::cout << "===== ID_VERIDATATYPE:: packed_dim = " << packed_dim << std::endl;<br />
if ( packed_dim != 0 ) {<br />
VeriRange const* range = dynamic_cast<VeriRange const*><br />
(p_data_type->GetDimensions());<br />
VeriRange const* last_dim_range = NULL;<br />
do {<br />
last_dim_range = range;<br />
} while ( range && (range = range->GetNext()) );<br />
if ( last_dim_range && last_dim_range->GetLeft() && last_dim_range->GetRight() ) {<br />
std::cout << "packed_dim->Left = " << last_dim_range->GetLeft()->GetPrettyPrintedString() << std::endl;<br />
std::cout << "packed_dim->Right = " << last_dim_range->GetRight()->GetPrettyPrintedString() << std::endl;<br />
}<br />
}<br />
break;<br />
}<br />
case ID_VERINETDATATYPE:<br />
break;<br />
case ID_VERISTRUCTUNION: {<br />
std::cout << "===== ID_VERISTRUCTUNION:: p_data_type->Image() = " << p_data_type->Image() << " =====" << std::endl;<br />
unsigned i;<br />
Array *decls = p_data_type->GetDecls() ;<br />
VeriDataDecl *decl;<br />
FOREACH_ARRAY_ITEM (decls, i, decl) {<br />
//std::cout << "===== ===== decl " << i << ": " << decl->GetPrettyPrintedString() << std::endl;<br />
VeriDataType *datatype = decl->GetDataType();<br />
(void) GetBaseTypeFromDataType(datatype);<br />
}<br />
break;<br />
}<br />
case ID_VERIENUM : {<br />
std::cout << "===== ID_VERIENUM:: p_data_type->Image() = " << p_data_type->Image() << " =====" << std::endl;<br />
std::cout << "===== ID_VERIENUM:: packed_dim = " << packed_dim << std::endl;<br />
if ( packed_dim != 0 ) {<br />
VeriRange const* range = dynamic_cast<VeriRange const*><br />
(p_data_type->GetDimensions());<br />
VeriRange const* last_dim_range = NULL;<br />
do {<br />
last_dim_range = range;<br />
} while ( range && (range = range->GetNext()) );<br />
<br />
if ( last_dim_range && last_dim_range->GetLeft() && last_dim_range->GetRight() ) {<br />
std::cout << "packed_dim->Left = " << last_dim_range->GetLeft()->GetPrettyPrintedString() << std::endl;<br />
std::cout << "packed_dim->Right = " << last_dim_range->GetRight()->GetPrettyPrintedString() << std::endl;<br />
}<br />
}<br />
VeriEnum* p_enum = dynamic_cast<VeriEnum*>(p_data_type);<br />
VeriDataType* p_base_type = p_enum->GetBaseType();<br />
GetBaseTypeFromDataType (p_base_type);<br />
break;<br />
}<br />
case ID_VERITYPEREF: {<br />
std::cout << "===== ID_VERITYPEREF:: p_data_type->Image() = " << p_data_type->Image() << " =====" << std::endl;<br />
std::cout << "===== ID_VERITYPEREF:: packed_dim = " << packed_dim << std::endl;<br />
GetBaseTypeFromDataType(p_data_type->GetBaseDataType());<br />
break;<br />
}<br />
default:<br />
break;<br />
}<br />
}<br />
</nowiki><br />
<br />
Input Verilog:<br />
<nowiki><br />
typedef enum bit {a, b} [1:0] data_ctrl_t;<br />
<br />
module test (output data_ctrl_t out1 );<br />
struct packed {<br />
logic [7:0] high;<br />
logic [3:0] low;<br />
} word1;<br />
assign out1 = b ;<br />
endmodule<br />
</nowiki><br />
<br />
Run:<br />
<nowiki><br />
-- Analyzing Verilog file 'test.v' (VERI-1482)<br />
test.v(3): INFO: compiling module 'test' (VERI-1018)<br />
test.v(3): INFO: compiling module 'test' (VERI-1018)<br />
Handling Declaration: out1<br />
===== ID_VERITYPEREF:: p_data_type->Image() = data_ctrl_t =====<br />
===== ID_VERITYPEREF:: packed_dim = 1<br />
===== ID_VERIENUM:: p_data_type->Image() = enum(a,b) =====<br />
===== ID_VERIENUM:: packed_dim = 1<br />
packed_dim->Left = 1<br />
packed_dim->Right = 0<br />
===== ID_VERIDATATYPE:: p_data_type->Image() = bit =====<br />
===== ID_VERIDATATYPE:: packed_dim = 0<br />
Handling Declaration: word1<br />
===== ID_VERISTRUCTUNION:: p_data_type->Image() = struct(high,low) =====<br />
===== ID_VERIDATATYPE:: p_data_type->Image() = logic [7:0] =====<br />
===== ID_VERIDATATYPE:: packed_dim = 1<br />
packed_dim->Left = 7<br />
packed_dim->Right = 0<br />
===== ID_VERIDATATYPE:: p_data_type->Image() = logic [3:0] =====<br />
===== ID_VERIDATATYPE:: packed_dim = 1<br />
packed_dim->Left = 3<br />
packed_dim->Right = 0<br />
</nowiki></div>Vincehttps://www.verific.com/faq/index.php?title=Parse_select_modules_only_and_ignore_the_rest&diff=783Parse select modules only and ignore the rest2022-05-02T18:44:53Z<p>Vince: </p>
<hr />
<div>There is no API to parse only a subset of modules of a design that contains many modules. <br />
However, this can be accomplished through Verific's processing of v-files. <br />
<br />
Below is an outline of the steps involved:<br />
<br />
- Register all the input source files as v-files for processing.<br><br />
- Move all of the modules to the 'work' library.<br><br />
- Analyze a 'dummy' file that contains only the modules of interest.<br><br />
- Process the v-files.<br><br />
- Delete the 'dummy' module itself<br />
<br />
C++:<br />
<nowiki><br />
#include <iostream><br />
#include "veri_file.h"<br />
#include "VeriModule.h"<br />
#include "VeriLibrary.h"<br />
#include "Map.h"<br />
<br />
#ifdef VERIFIC_NAMESPACE<br />
using namespace Verific ;<br />
#endif<br />
<br />
int main()<br />
{<br />
// Add the 'real' input file(s) to be analyzed as -v file:<br />
veri_file::AddVFile("testa.v") ;<br />
veri_file::AddVFile("testb.v") ;<br />
// Move -v modules into 'work'<br />
RuntimeFlags::SetVar("veri_move_yv_modules_into_work_library", 1) ;<br />
<br />
// Analyze dummy file<br />
if (!veri_file::Analyze("dummy.v", veri_file::SYSTEM_VERILOG)) return 1 ;<br />
// Need this to process -v file<br />
veri_file::ProcessUserLibraries() ;<br />
<br />
VeriModule *dummy = veri_file::GetModule ("dummy") ;<br />
delete dummy ; // no longer needed<br />
<br />
MapIter mi;<br />
VeriModule *module;<br />
FOREACH_VERILOG_MODULE (mi, module) {<br />
std::cout << "*** Module '" << module->Name() << "' in library '" << module->GetLibrary()->GetName() << "'" << s<br />
td::endl ;<br />
}<br />
veri_file::PrettyPrint("pp_out.v", 0) ;<br />
return 0 ;<br />
}<br />
</nowiki><br />
<br />
Source file testa.v:<br />
<nowiki><br />
module test1 ;<br />
wire ina, inb, inc;<br />
wire outd;<br />
mod1 I0(ina, inb, inc, outd);<br />
endmodule<br />
<br />
module test2 ;<br />
wire ina, inb, inc;<br />
wire outd;<br />
mod2 I0(ina, inb, inc, outd);<br />
endmodule<br />
</nowiki><br />
<br />
Source file testb.v:<br />
<nowiki><br />
module test3 ;<br />
wire ina, inb, inc;<br />
wire outd;<br />
mod3 I0(ina, inb, inc, outd);<br />
endmodule<br />
<br />
module test4 ;<br />
wire ina, inb, inc;<br />
wire outd;<br />
mod4 I0(ina, inb, inc, outd);<br />
endmodule<br />
<br />
module test5 ;<br />
wire ina, inb, inc;<br />
wire outd;<br />
mod5 I0(ina, inb, inc, outd);<br />
endmodule<br />
</nowiki><br />
<br />
Source file dummy.v -- this contains the modules we want to parse:<br />
<nowiki><br />
module dummy ();<br />
test2 i2 ();<br />
test3 i3 ();<br />
endmodule<br />
</nowiki><br />
<br />
Result of running the application:<br />
<nowiki><br />
-- Analyzing Verilog file 'dummy.v' (VERI-1482)<br />
-- Analyzing Verilog file 'testa.v' (VERI-1482)<br />
-- Resolving module 'test2' (VERI-1489)<br />
-- Analyzing Verilog file 'testb.v' (VERI-1482)<br />
-- Resolving module 'test3' (VERI-1489)<br />
-- Analyzing Verilog file 'testa.v' (VERI-1482)<br />
-- Analyzing Verilog file 'testb.v' (VERI-1482)<br />
*** Module 'test2' in library 'work'<br />
*** Module 'test3' in library 'work'<br />
-- Printing all libraries to file 'pp_out.v' (VERI-1492)<br />
</nowiki><br />
<br />
Output file pp_out.v:<br />
<nowiki><br />
module test2 ;<br />
wire ina, inb, inc ; <br />
wire outd ; <br />
mod2 I0 (ina, inb, inc, outd) ; <br />
endmodule<br />
<br />
<br />
<br />
module test3 ;<br />
wire ina, inb, inc ; <br />
wire outd ; <br />
mod3 I0 (ina, inb, inc, outd) ; <br />
endmodule<br />
<br />
</nowiki></div>Vincehttps://www.verific.com/faq/index.php?title=Parse_select_modules_only_and_ignore_the_rest&diff=782Parse select modules only and ignore the rest2022-05-02T18:44:19Z<p>Vince: </p>
<hr />
<div>There is no API to parse only a subset of modules of a design that contains many modules. <br />
However, this can be accomplished through Verific's processing of v-files. <br />
<br />
Below is an outline of the steps involved:<br />
<br />
- Register all the input source files as v-files for processing.<br><br />
- Move all of the modules to the 'work' library.<br><br />
- Analyze a 'dummy' file that contains only the modules of interest.<br><br />
- Process the v-files<br />
- Delete the 'dummy' module itself<br />
<br />
C++:<br />
<nowiki><br />
#include <iostream><br />
#include "veri_file.h"<br />
#include "VeriModule.h"<br />
#include "VeriLibrary.h"<br />
#include "Map.h"<br />
<br />
#ifdef VERIFIC_NAMESPACE<br />
using namespace Verific ;<br />
#endif<br />
<br />
int main()<br />
{<br />
// Add the 'real' input file(s) to be analyzed as -v file:<br />
veri_file::AddVFile("testa.v") ;<br />
veri_file::AddVFile("testb.v") ;<br />
// Move -v modules into 'work'<br />
RuntimeFlags::SetVar("veri_move_yv_modules_into_work_library", 1) ;<br />
<br />
// Analyze dummy file<br />
if (!veri_file::Analyze("dummy.v", veri_file::SYSTEM_VERILOG)) return 1 ;<br />
// Need this to process -v file<br />
veri_file::ProcessUserLibraries() ;<br />
<br />
VeriModule *dummy = veri_file::GetModule ("dummy") ;<br />
delete dummy ; // no longer needed<br />
<br />
MapIter mi;<br />
VeriModule *module;<br />
FOREACH_VERILOG_MODULE (mi, module) {<br />
std::cout << "*** Module '" << module->Name() << "' in library '" << module->GetLibrary()->GetName() << "'" << s<br />
td::endl ;<br />
}<br />
veri_file::PrettyPrint("pp_out.v", 0) ;<br />
return 0 ;<br />
}<br />
</nowiki><br />
<br />
Source file testa.v:<br />
<nowiki><br />
module test1 ;<br />
wire ina, inb, inc;<br />
wire outd;<br />
mod1 I0(ina, inb, inc, outd);<br />
endmodule<br />
<br />
module test2 ;<br />
wire ina, inb, inc;<br />
wire outd;<br />
mod2 I0(ina, inb, inc, outd);<br />
endmodule<br />
</nowiki><br />
<br />
Source file testb.v:<br />
<nowiki><br />
module test3 ;<br />
wire ina, inb, inc;<br />
wire outd;<br />
mod3 I0(ina, inb, inc, outd);<br />
endmodule<br />
<br />
module test4 ;<br />
wire ina, inb, inc;<br />
wire outd;<br />
mod4 I0(ina, inb, inc, outd);<br />
endmodule<br />
<br />
module test5 ;<br />
wire ina, inb, inc;<br />
wire outd;<br />
mod5 I0(ina, inb, inc, outd);<br />
endmodule<br />
</nowiki><br />
<br />
Source file dummy.v -- this contains the modules we want to parse:<br />
<nowiki><br />
module dummy ();<br />
test2 i2 ();<br />
test3 i3 ();<br />
endmodule<br />
</nowiki><br />
<br />
Result of running the application:<br />
<nowiki><br />
-- Analyzing Verilog file 'dummy.v' (VERI-1482)<br />
-- Analyzing Verilog file 'testa.v' (VERI-1482)<br />
-- Resolving module 'test2' (VERI-1489)<br />
-- Analyzing Verilog file 'testb.v' (VERI-1482)<br />
-- Resolving module 'test3' (VERI-1489)<br />
-- Analyzing Verilog file 'testa.v' (VERI-1482)<br />
-- Analyzing Verilog file 'testb.v' (VERI-1482)<br />
*** Module 'test2' in library 'work'<br />
*** Module 'test3' in library 'work'<br />
-- Printing all libraries to file 'pp_out.v' (VERI-1492)<br />
</nowiki><br />
<br />
Output file pp_out.v:<br />
<nowiki><br />
module test2 ;<br />
wire ina, inb, inc ; <br />
wire outd ; <br />
mod2 I0 (ina, inb, inc, outd) ; <br />
endmodule<br />
<br />
<br />
<br />
module test3 ;<br />
wire ina, inb, inc ; <br />
wire outd ; <br />
mod3 I0 (ina, inb, inc, outd) ; <br />
endmodule<br />
<br />
</nowiki></div>Vincehttps://www.verific.com/faq/index.php?title=Parse_select_modules_only_and_ignore_the_rest&diff=781Parse select modules only and ignore the rest2022-05-02T18:39:45Z<p>Vince: </p>
<hr />
<div>There is no API to parse only a subset of modules of a design that contains many modules. <br />
However, this can be accomplished through Verific's processing of v-files. <br />
<br />
Below is an outline of the steps involved:<br />
<br />
- Register all the input source files as v-files for processing.<br><br />
- Move all of the modules to the 'work' library.<br><br />
- Analyze a 'dummy' file that contains only the modules of interest.<br><br />
- Process the v-files<br />
<br />
C++:<br />
<nowiki><br />
#include <iostream><br />
#include "veri_file.h"<br />
#include "VeriModule.h"<br />
#include "VeriLibrary.h"<br />
#include "Map.h"<br />
<br />
#ifdef VERIFIC_NAMESPACE<br />
using namespace Verific ;<br />
#endif<br />
<br />
int main()<br />
{<br />
// Add the 'real' input file(s) to be analyzed as -v file:<br />
veri_file::AddVFile("testa.v") ;<br />
veri_file::AddVFile("testb.v") ;<br />
// Move -v modules into 'work'<br />
RuntimeFlags::SetVar("veri_move_yv_modules_into_work_library", 1) ;<br />
<br />
// Analyze dummy file<br />
if (!veri_file::Analyze("dummy.v", veri_file::SYSTEM_VERILOG)) return 1 ;<br />
// Need this to process -v file<br />
veri_file::ProcessUserLibraries() ;<br />
<br />
VeriModule *dummy = veri_file::GetModule ("dummy") ;<br />
delete dummy ; // no longer needed<br />
<br />
MapIter mi;<br />
VeriModule *module;<br />
FOREACH_VERILOG_MODULE (mi, module) {<br />
std::cout << "*** Module '" << module->Name() << "' in library '" << module->GetLibrary()->GetName() << "'" << s<br />
td::endl ;<br />
}<br />
veri_file::PrettyPrint("pp_out.v", 0) ;<br />
return 0 ;<br />
}<br />
</nowiki><br />
<br />
Source file testa.v:<br />
<nowiki><br />
module test1 ;<br />
wire ina, inb, inc;<br />
wire outd;<br />
mod1 I0(ina, inb, inc, outd);<br />
endmodule<br />
<br />
module test2 ;<br />
wire ina, inb, inc;<br />
wire outd;<br />
mod2 I0(ina, inb, inc, outd);<br />
endmodule<br />
</nowiki><br />
<br />
Source file testb.v:<br />
<nowiki><br />
module test3 ;<br />
wire ina, inb, inc;<br />
wire outd;<br />
mod3 I0(ina, inb, inc, outd);<br />
endmodule<br />
<br />
module test4 ;<br />
wire ina, inb, inc;<br />
wire outd;<br />
mod4 I0(ina, inb, inc, outd);<br />
endmodule<br />
<br />
module test5 ;<br />
wire ina, inb, inc;<br />
wire outd;<br />
mod5 I0(ina, inb, inc, outd);<br />
endmodule<br />
</nowiki><br />
<br />
Source file dummy.v -- this contains the modules we want to parse:<br />
<nowiki><br />
module dummy ();<br />
test2 i2 ();<br />
test3 i3 ();<br />
endmodule<br />
</nowiki><br />
<br />
Result of running the application:<br />
<nowiki><br />
-- Analyzing Verilog file 'dummy.v' (VERI-1482)<br />
-- Analyzing Verilog file 'testa.v' (VERI-1482)<br />
-- Resolving module 'test2' (VERI-1489)<br />
-- Analyzing Verilog file 'testb.v' (VERI-1482)<br />
-- Resolving module 'test3' (VERI-1489)<br />
-- Analyzing Verilog file 'testa.v' (VERI-1482)<br />
-- Analyzing Verilog file 'testb.v' (VERI-1482)<br />
*** Module 'test2' in library 'work'<br />
*** Module 'test3' in library 'work'<br />
-- Printing all libraries to file 'pp_out.v' (VERI-1492)<br />
</nowiki><br />
<br />
Output file pp_out.v:<br />
<nowiki><br />
module test2 ;<br />
wire ina, inb, inc ; <br />
wire outd ; <br />
mod2 I0 (ina, inb, inc, outd) ; <br />
endmodule<br />
<br />
<br />
<br />
module test3 ;<br />
wire ina, inb, inc ; <br />
wire outd ; <br />
mod3 I0 (ina, inb, inc, outd) ; <br />
endmodule<br />
<br />
</nowiki></div>Vincehttps://www.verific.com/faq/index.php?title=Parse_select_modules_only_and_ignore_the_rest&diff=780Parse select modules only and ignore the rest2022-05-02T18:33:33Z<p>Vince: Created page with "There is no API to parse only a subset of modules of a design that contains many modules. However, this can be accomplished through Verific's processing of v-files. Below i..."</p>
<hr />
<div>There is no API to parse only a subset of modules of a design that contains many modules. <br />
However, this can be accomplished through Verific's processing of v-files. <br />
<br />
Below is an outline of the steps involved:<br />
<br />
- Register all the input source files as v-files for processing.<br><br />
- Move all of the modules to the 'work' library.<br><br />
- Analyze a 'dummy' file that contains only the modules of interest.<br><br />
- Process the v-files<br />
<br />
C++:<br />
<nowiki><br />
#include <iostream><br />
#include "veri_file.h"<br />
#include "VeriModule.h"<br />
#include "VeriLibrary.h"<br />
#include "Map.h"<br />
<br />
#ifdef VERIFIC_NAMESPACE<br />
using namespace Verific ;<br />
#endif<br />
<br />
int main()<br />
{<br />
// Add the 'real' input file(s) to be analyzed as -v file:<br />
veri_file::AddVFile("testa.v") ;<br />
veri_file::AddVFile("testb.v") ;<br />
// Move -v modules into 'work'<br />
RuntimeFlags::SetVar("veri_move_yv_modules_into_work_library", 1) ;<br />
<br />
// Analyze dummy file<br />
if (!veri_file::Analyze("dummy.v", veri_file::SYSTEM_VERILOG)) return 1 ;<br />
// Need this to process -v file<br />
veri_file::ProcessUserLibraries() ;<br />
<br />
VeriModule *dummy = veri_file::GetModule ("dummy") ;<br />
delete dummy ; // no longer needed<br />
<br />
MapIter mi;<br />
VeriModule *module;<br />
FOREACH_VERILOG_MODULE (mi, module) {<br />
std::cout << "*** Module '" << module->Name() << "' in library '" << module->GetLibrary()->GetName() << "'" << s<br />
td::endl ;<br />
}<br />
veri_file::PrettyPrint("pp_out.v", 0) ;<br />
return 0 ;<br />
}<br />
</nowiki><br />
<br />
Source file testa.v:<br />
<nowiki><br />
module test1 ;<br />
wire ina, inb, inc;<br />
wire outd;<br />
mod1 I0(ina, inb, inc, outd);<br />
endmodule<br />
<br />
module test2 ;<br />
wire ina, inb, inc;<br />
wire outd;<br />
mod2 I0(ina, inb, inc, outd);<br />
endmodule<br />
</nowiki><br />
<br />
Source file testb.v:<br />
<nowiki><br />
module test3 ;<br />
wire ina, inb, inc;<br />
wire outd;<br />
mod3 I0(ina, inb, inc, outd);<br />
endmodule<br />
<br />
module test4 ;<br />
wire ina, inb, inc;<br />
wire outd;<br />
mod4 I0(ina, inb, inc, outd);<br />
endmodule<br />
<br />
module test5 ;<br />
wire ina, inb, inc;<br />
wire outd;<br />
mod5 I0(ina, inb, inc, outd);<br />
endmodule<br />
</nowiki><br />
<br />
<br />
Result of running the application:<br />
<nowiki><br />
-- Analyzing Verilog file 'dummy.v' (VERI-1482)<br />
-- Analyzing Verilog file 'testa.v' (VERI-1482)<br />
-- Resolving module 'test2' (VERI-1489)<br />
-- Analyzing Verilog file 'testb.v' (VERI-1482)<br />
-- Resolving module 'test3' (VERI-1489)<br />
-- Analyzing Verilog file 'testa.v' (VERI-1482)<br />
-- Analyzing Verilog file 'testb.v' (VERI-1482)<br />
*** Module 'test2' in library 'work'<br />
*** Module 'test3' in library 'work'<br />
-- Printing all libraries to file 'pp_out.v' (VERI-1492)<br />
</nowiki><br />
<br />
Output file pp_out.v:<br />
<nowiki><br />
module test2 ;<br />
wire ina, inb, inc ; <br />
wire outd ; <br />
mod2 I0 (ina, inb, inc, outd) ; <br />
endmodule<br />
<br />
<br />
<br />
module test3 ;<br />
wire ina, inb, inc ; <br />
wire outd ; <br />
mod3 I0 (ina, inb, inc, outd) ; <br />
endmodule<br />
<br />
</nowiki></div>Vincehttps://www.verific.com/faq/index.php?title=Main_Page&diff=779Main Page2022-05-02T18:00:53Z<p>Vince: </p>
<hr />
<div>'''General'''<br />
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]<br />
* [[Source code customization & Stable release services | Source code customization & Stable release services]]<br />
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]<br />
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]<br />
* [[Verific data structures | What are the data structures in Verific?]]<br />
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]<br />
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]<br />
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]<br />
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]<br />
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]<br />
* [[Release version | How do I tell the version of a Verific software release? ]]<br />
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]<br />
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]<br />
* [[LineFile data from input files | LineFile data from input files]]<br />
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]<br />
* [[Preserving user nets - preventing nets from being optimized away | Preserving user nets - preventing nets from being optimized away]]<br />
<br />
'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''<br />
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]<br />
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]<br />
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]<br />
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]<br />
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]<br />
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]<br />
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]<br />
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]<br />
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]<br />
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]<br />
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]<br />
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]<br />
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]<br />
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]<br />
* [[Notes on analysis | SystemVerilog: Notes on analysis]]<br />
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]<br />
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]<br />
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]<br />
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]<br />
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]<br />
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]<br />
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]<br />
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]<br />
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]<br />
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]<br />
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]<br />
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]<br />
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]<br />
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]]<br />
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]<br />
<br />
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]<br />
'''Netlist Database'''<br />
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]<br />
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]<br />
* [[System attributes | Netlist Database: System attributes]]<br />
<br />
'''Output'''<br />
* [[Output file formats | What language formats does Verific support as output?]]<br />
<br />
'''Scripting languages: TCL, Perl, Python'''<br />
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]<br />
<br />
'''Code examples'''<br />
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]<br />
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]<br />
* [[Extract clock enable | Database/C++: Extract clock enable]]<br />
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]<br />
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]<br />
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]<br />
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]<br />
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]<br />
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]<br />
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]<br />
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]<br />
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]<br />
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]<br />
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]<br />
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]<br />
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]<br />
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]<br />
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]<br />
* [[Type Range example | Verilog/C++: Type Range example (simple)]]<br />
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]<br />
* [[How to ignore certain modules while analyzing input RTL files | Verilog/C++: How to ignore certain modules while analyzing input RTL files]]<br />
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]<br />
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]] <br />
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]<br />
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]<br />
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]<br />
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]<br />
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]<br />
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]<br />
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]<br />
* [[Parse select modules only and ignore the rest | Verilog/C++: Parse select modules only and ignore the rest]]<br />
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]<br />
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]<br />
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]<br />
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]<br />
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]<br />
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]<br />
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]<br />
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]<br />
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]</div>Vincehttps://www.verific.com/faq/index.php?title=Main_Page&diff=776Main Page2022-04-01T18:26:20Z<p>Vince: </p>
<hr />
<div>'''General'''<br />
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]<br />
* [[Source code customization & Stable release services | Source code customization & Stable release services]]<br />
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]<br />
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]<br />
* [[Verific data structures | What are the data structures in Verific?]]<br />
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]<br />
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]<br />
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]<br />
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]<br />
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]<br />
* [[Release version | How do I tell the version of a Verific software release? ]]<br />
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]<br />
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]<br />
* [[LineFile data from input files | LineFile data from input files]]<br />
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]<br />
* [[Preserving user nets - preventing nets from being optimized away | Preserving user nets - preventing nets from being optimized away]]<br />
<br />
'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''<br />
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]<br />
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]<br />
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]<br />
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]<br />
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]<br />
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]<br />
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]<br />
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]<br />
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]<br />
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]<br />
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]<br />
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]<br />
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]<br />
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]<br />
* [[Notes on analysis | SystemVerilog: Notes on analysis]]<br />
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]<br />
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]<br />
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]<br />
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]<br />
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]<br />
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]<br />
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]<br />
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]<br />
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]<br />
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]<br />
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]<br />
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]<br />
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]<br />
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]]<br />
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]<br />
<br />
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]<br />
'''Netlist Database'''<br />
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]<br />
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]<br />
* [[System attributes | Netlist Database: System attributes]]<br />
<br />
'''Output'''<br />
* [[Output file formats | What language formats does Verific support as output?]]<br />
<br />
'''Scripting languages: TCL, Perl, Python'''<br />
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]<br />
<br />
'''Code examples'''<br />
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]<br />
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]<br />
* [[Extract clock enable | Database/C++: Extract clock enable]]<br />
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]<br />
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]<br />
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]<br />
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]<br />
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]<br />
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]<br />
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]<br />
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]<br />
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]<br />
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]<br />
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]<br />
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]<br />
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]<br />
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]<br />
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]<br />
* [[Type Range example | Verilog/C++: Type Range example (simple)]]<br />
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]<br />
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]<br />
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]] <br />
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]<br />
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]<br />
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]<br />
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]<br />
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]<br />
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]<br />
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]<br />
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]<br />
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]<br />
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]<br />
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]<br />
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]<br />
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]<br />
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]<br />
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]<br />
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]</div>Vincehttps://www.verific.com/faq/index.php?title=Main_Page&diff=775Main Page2022-04-01T18:25:39Z<p>Vince: </p>
<hr />
<div>'''General'''<br />
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]<br />
* [[Source code customization & Stable release services | Source code customization & Stable release services]]<br />
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]<br />
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]<br />
* [[Verific data structures | What are the data structures in Verific?]]<br />
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]<br />
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]<br />
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]<br />
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]<br />
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]<br />
* [[Release version | How do I tell the version of a Verific software release? ]]<br />
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]<br />
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]<br />
* [[LineFile data from input files | LineFile data from input files]]<br />
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]<br />
* [[Preserving user nets | Preserving user nets - preventing nets from being optimized away]]<br />
<br />
'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''<br />
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]<br />
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]<br />
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]<br />
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]<br />
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]<br />
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]<br />
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]<br />
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]<br />
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]<br />
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]<br />
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]<br />
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]<br />
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]<br />
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]<br />
* [[Notes on analysis | SystemVerilog: Notes on analysis]]<br />
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]<br />
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]<br />
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]<br />
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]<br />
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]<br />
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]<br />
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]<br />
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]<br />
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]<br />
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]<br />
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]<br />
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]<br />
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]<br />
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]]<br />
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]<br />
<br />
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]<br />
'''Netlist Database'''<br />
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]<br />
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]<br />
* [[System attributes | Netlist Database: System attributes]]<br />
<br />
'''Output'''<br />
* [[Output file formats | What language formats does Verific support as output?]]<br />
<br />
'''Scripting languages: TCL, Perl, Python'''<br />
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]<br />
<br />
'''Code examples'''<br />
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]<br />
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]<br />
* [[Extract clock enable | Database/C++: Extract clock enable]]<br />
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]<br />
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]<br />
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]<br />
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]<br />
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]<br />
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]<br />
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]<br />
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]<br />
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]<br />
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]<br />
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]<br />
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]<br />
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]<br />
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]<br />
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]<br />
* [[Type Range example | Verilog/C++: Type Range example (simple)]]<br />
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]<br />
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]<br />
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]] <br />
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]<br />
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]<br />
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]<br />
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]<br />
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]<br />
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]<br />
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]<br />
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]<br />
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]<br />
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]<br />
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]<br />
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]<br />
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]<br />
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]<br />
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]<br />
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]</div>Vincehttps://www.verific.com/faq/index.php?title=Preserving_nets&diff=774Preserving nets2022-04-01T18:24:24Z<p>Vince: Redirected page to Preserving user nets - preventing nets from being optimized away</p>
<hr />
<div>#REDIRECT [[Preserving user nets - preventing nets from being optimized away]]</div>Vincehttps://www.verific.com/faq/index.php?title=Main_Page&diff=773Main Page2022-04-01T18:20:58Z<p>Vince: </p>
<hr />
<div>'''General'''<br />
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]<br />
* [[Source code customization & Stable release services | Source code customization & Stable release services]]<br />
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]<br />
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]<br />
* [[Verific data structures | What are the data structures in Verific?]]<br />
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]<br />
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]<br />
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]<br />
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]<br />
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]<br />
* [[Release version | How do I tell the version of a Verific software release? ]]<br />
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]<br />
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]<br />
* [[LineFile data from input files | LineFile data from input files]]<br />
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]<br />
* [[Preserving nets | Preserving user nets - preventing nets from being optimized away]]<br />
<br />
'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''<br />
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]<br />
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]<br />
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]<br />
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]<br />
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]<br />
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]<br />
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]<br />
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]<br />
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]<br />
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]<br />
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]<br />
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]<br />
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]<br />
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]<br />
* [[Notes on analysis | SystemVerilog: Notes on analysis]]<br />
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]<br />
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]<br />
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]<br />
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]<br />
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]<br />
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]<br />
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]<br />
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]<br />
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]<br />
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]<br />
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]<br />
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]<br />
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]<br />
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]]<br />
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]<br />
<br />
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]<br />
'''Netlist Database'''<br />
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]<br />
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]<br />
* [[System attributes | Netlist Database: System attributes]]<br />
<br />
'''Output'''<br />
* [[Output file formats | What language formats does Verific support as output?]]<br />
<br />
'''Scripting languages: TCL, Perl, Python'''<br />
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]<br />
<br />
'''Code examples'''<br />
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]<br />
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]<br />
* [[Extract clock enable | Database/C++: Extract clock enable]]<br />
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]<br />
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]<br />
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]<br />
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]<br />
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]<br />
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]<br />
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]<br />
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]<br />
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]<br />
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]<br />
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]<br />
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]<br />
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]<br />
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]<br />
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]<br />
* [[Type Range example | Verilog/C++: Type Range example (simple)]]<br />
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]<br />
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]<br />
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]] <br />
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]<br />
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]<br />
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]<br />
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]<br />
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]<br />
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]<br />
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]<br />
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]<br />
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]<br />
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]<br />
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]<br />
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]<br />
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]<br />
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]<br />
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]<br />
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]</div>Vincehttps://www.verific.com/faq/index.php?title=Main_Page&diff=772Main Page2022-04-01T18:20:03Z<p>Vince: </p>
<hr />
<div>'''General'''<br />
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]<br />
* [[Source code customization & Stable release services | Source code customization & Stable release services]]<br />
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]<br />
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]<br />
* [[Verific data structures | What are the data structures in Verific?]]<br />
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]<br />
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]<br />
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]<br />
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]<br />
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]<br />
* [[Release version | How do I tell the version of a Verific software release? ]]<br />
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]<br />
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]<br />
* [[LineFile data from input files | LineFile data from input files]]<br />
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]<br />
* [[Preserving user nets | Preserving user nets - preventing nets from being optimized away]]<br />
<br />
'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''<br />
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]<br />
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]<br />
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]<br />
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]<br />
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]<br />
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]<br />
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]<br />
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]<br />
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]<br />
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]<br />
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]<br />
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]<br />
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]<br />
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]<br />
* [[Notes on analysis | SystemVerilog: Notes on analysis]]<br />
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]<br />
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]<br />
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]<br />
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]<br />
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]<br />
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]<br />
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]<br />
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]<br />
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]<br />
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]<br />
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]<br />
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]<br />
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]<br />
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]]<br />
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]<br />
<br />
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]<br />
'''Netlist Database'''<br />
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]<br />
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]<br />
* [[System attributes | Netlist Database: System attributes]]<br />
<br />
'''Output'''<br />
* [[Output file formats | What language formats does Verific support as output?]]<br />
<br />
'''Scripting languages: TCL, Perl, Python'''<br />
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]<br />
<br />
'''Code examples'''<br />
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]<br />
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]<br />
* [[Extract clock enable | Database/C++: Extract clock enable]]<br />
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]<br />
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]<br />
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]<br />
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]<br />
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]<br />
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]<br />
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]<br />
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]<br />
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]<br />
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]<br />
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]<br />
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]<br />
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]<br />
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]<br />
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]<br />
* [[Type Range example | Verilog/C++: Type Range example (simple)]]<br />
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]<br />
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]<br />
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]] <br />
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]<br />
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]<br />
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]<br />
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]<br />
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]<br />
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]<br />
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]<br />
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]<br />
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]<br />
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]<br />
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]<br />
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]<br />
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]<br />
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]<br />
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]<br />
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]</div>Vincehttps://www.verific.com/faq/index.php?title=Preserving_user_nets_-_preventing_nets_from_being_optimized_away&diff=771Preserving user nets - preventing nets from being optimized away2022-04-01T18:17:38Z<p>Vince: </p>
<hr />
<div>'''Q: How do I preserve user-declared nets so that they don't get optimized away? I would like to see them written out to the netlist file.'''<br />
<br />
There are two approaches :<br />
* globally preserve all user nets<br />
* preserve only selective nets<br />
<br />
<br />
1. Globally preserve all user nets<br />
<br />
The following flags need to be set to have global effect :<br />
<br />
set_runtime_flag db_preserve_user_nets 1<br />
set_runtime_flag veri_preserve_user_nets 1 # if using Verilog/SystemVerilog<br />
set_runtime_flag vhdl_preserve_user_nets 1 # if using VHDL<br />
<br />
<br />
2. Preserve only selective nets<br />
<br />
Setting an attribute on a net will prevent it from being optimized away. The attribute can be any attribute, as seen in the examples below.<br />
<br />
Verilog :<br />
<br />
module test (input i, output o);<br />
(* any *) wire willstay;<br />
wire willgo;<br />
(* another = "any" *) reg willstaytoo;<br />
assign o = ~i;<br />
endmodule<br />
<br />
This is the output Verilog netlist :<br />
//<br />
// Verific Verilog Description of module test<br />
//<br />
module test (i, o); // test2.v(1)<br />
input i; // test2.v(1)<br />
output o; // test2.v(1)<br />
<br />
wire willstay /* verific any=1 */ ; // test2.v(2)<br />
wire willstaytoo /* verific another="any" */ ; // test2.v(4)<br />
<br />
not (o, i) ; // test2.v(5)<br />
<br />
endmodule<br />
<br />
<br />
VHDL :<br />
<br />
library ieee;<br />
use ieee.std_logic_1164.all ;<br />
entity test is <br />
port (i : in bit; o : out bit) ;<br />
end entity test;<br />
architecture arch of test is<br />
signal willstay : bit ;<br />
signal willgo : bit ;<br />
signal willstaytoo : bit ; <br />
attribute any : string ;<br />
attribute any of willstay : signal is "" ;<br />
attribute another : string ;<br />
attribute another of willstaytoo : signal is "any" ;<br />
begin<br />
o <= not i ;<br />
end arch ;<br />
<br />
This is the output VHDL netlist :<br />
--<br />
-- Verific VHDL Description of module test<br />
--<br />
library ieee ;<br />
use ieee.std_logic_1164.all ;<br />
entity test is<br />
port (i: in std_logic; -- test2.vhd(4)<br />
o: out std_logic -- test2.vhd(4)<br />
);<br />
end entity test; -- test2.vhd(3)<br />
architecture arch of test is <br />
signal willstay : std_logic; -- any="" -- test2.vhd(8)<br />
signal willstaytoo : std_logic; -- another="any" -- test2.vhd(10) <br />
begin<br />
o <= not i; -- test2.vhd(16) <br />
end architecture arch; -- test2.vhd(3)</div>Vincehttps://www.verific.com/faq/index.php?title=Preserving_user_nets_-_preventing_nets_from_being_optimized_away&diff=769Preserving user nets - preventing nets from being optimized away2022-04-01T18:16:48Z<p>Vince: Vince moved page Preserving user nets --preventing nets from being optimized away to Preserving user nets - preventing nets from being optimized away</p>
<hr />
<div>'''Q: How do I preserve user-declared nets so that they don't get optimized away? I would like to see them written out to the netlist file.'''<br />
<br />
There are two approaches :<br />
* globally preserve all user nets<br />
* preserve only selective nets<br />
<br />
<br />
1. Globally preserve all user nets<br />
<br />
The following flags need to be set for global effect :<br />
<br />
set_runtime_flag db_preserve_user_nets 1<br />
set_runtime_flag veri_preserve_user_nets 1 # if using Verilog/SystemVerilog<br />
set_runtime_flag vhdl_preserve_user_nets 1 # if using VHDL<br />
<br />
<br />
2. Preserve only selective nets<br />
<br />
Setting an attribute on a net will prevent it from being optimized away. The attribute can be any attribute, as seen in the examples below.<br />
<br />
Verilog :<br />
<br />
module test (input i, output o);<br />
(* any *) wire willstay;<br />
wire willgo;<br />
(* another = "any" *) reg willstaytoo;<br />
assign o = ~i;<br />
endmodule<br />
<br />
This is the output Verilog netlist :<br />
//<br />
// Verific Verilog Description of module test<br />
//<br />
module test (i, o); // test2.v(1)<br />
input i; // test2.v(1)<br />
output o; // test2.v(1)<br />
<br />
wire willstay /* verific any=1 */ ; // test2.v(2)<br />
wire willstaytoo /* verific another="any" */ ; // test2.v(4)<br />
<br />
not (o, i) ; // test2.v(5)<br />
<br />
endmodule<br />
<br />
<br />
VHDL :<br />
<br />
library ieee;<br />
use ieee.std_logic_1164.all ;<br />
entity test is <br />
port (i : in bit; o : out bit) ;<br />
end entity test;<br />
architecture arch of test is<br />
signal willstay : bit ;<br />
signal willgo : bit ;<br />
signal willstaytoo : bit ; <br />
attribute any : string ;<br />
attribute any of willstay : signal is "" ;<br />
attribute another : string ;<br />
attribute another of willstaytoo : signal is "any" ;<br />
begin<br />
o <= not i ;<br />
end arch ;<br />
<br />
This is the output VHDL netlist :<br />
--<br />
-- Verific VHDL Description of module test<br />
--<br />
library ieee ;<br />
use ieee.std_logic_1164.all ;<br />
entity test is<br />
port (i: in std_logic; -- test2.vhd(4)<br />
o: out std_logic -- test2.vhd(4)<br />
);<br />
end entity test; -- test2.vhd(3)<br />
architecture arch of test is <br />
signal willstay : std_logic; -- any="" -- test2.vhd(8)<br />
signal willstaytoo : std_logic; -- another="any" -- test2.vhd(10) <br />
begin<br />
o <= not i; -- test2.vhd(16) <br />
end architecture arch; -- test2.vhd(3)</div>Vincehttps://www.verific.com/faq/index.php?title=Preserving_user_nets_--preventing_nets_from_being_optimized_away&diff=770Preserving user nets --preventing nets from being optimized away2022-04-01T18:16:48Z<p>Vince: Vince moved page Preserving user nets --preventing nets from being optimized away to Preserving user nets - preventing nets from being optimized away</p>
<hr />
<div>#REDIRECT [[Preserving user nets - preventing nets from being optimized away]]</div>Vincehttps://www.verific.com/faq/index.php?title=Main_Page&diff=768Main Page2022-04-01T18:16:06Z<p>Vince: </p>
<hr />
<div>'''General'''<br />
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]<br />
* [[Source code customization & Stable release services | Source code customization & Stable release services]]<br />
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]<br />
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]<br />
* [[Verific data structures | What are the data structures in Verific?]]<br />
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]<br />
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]<br />
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]<br />
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]<br />
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]<br />
* [[Release version | How do I tell the version of a Verific software release? ]]<br />
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]<br />
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]<br />
* [[LineFile data from input files | LineFile data from input files]]<br />
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]<br />
* [[Preserving nets | Preserving user nets - preventing nets from being optimized away]]<br />
<br />
'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''<br />
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]<br />
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]<br />
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]<br />
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]<br />
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]<br />
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]<br />
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]<br />
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]<br />
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]<br />
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]<br />
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]<br />
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]<br />
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]<br />
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]<br />
* [[Notes on analysis | SystemVerilog: Notes on analysis]]<br />
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]<br />
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]<br />
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]<br />
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]<br />
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]<br />
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]<br />
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]<br />
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]<br />
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]<br />
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]<br />
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]<br />
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]<br />
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]<br />
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]]<br />
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]<br />
<br />
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]<br />
'''Netlist Database'''<br />
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]<br />
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]<br />
* [[System attributes | Netlist Database: System attributes]]<br />
<br />
'''Output'''<br />
* [[Output file formats | What language formats does Verific support as output?]]<br />
<br />
'''Scripting languages: TCL, Perl, Python'''<br />
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]<br />
<br />
'''Code examples'''<br />
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]<br />
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]<br />
* [[Extract clock enable | Database/C++: Extract clock enable]]<br />
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]<br />
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]<br />
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]<br />
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]<br />
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]<br />
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]<br />
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]<br />
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]<br />
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]<br />
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]<br />
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]<br />
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]<br />
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]<br />
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]<br />
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]<br />
* [[Type Range example | Verilog/C++: Type Range example (simple)]]<br />
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]<br />
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]<br />
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]] <br />
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]<br />
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]<br />
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]<br />
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]<br />
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]<br />
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]<br />
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]<br />
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]<br />
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]<br />
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]<br />
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]<br />
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]<br />
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]<br />
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]<br />
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]<br />
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]</div>Vincehttps://www.verific.com/faq/index.php?title=Preserving_user_nets_-_preventing_nets_from_being_optimized_away&diff=766Preserving user nets - preventing nets from being optimized away2022-04-01T18:13:33Z<p>Vince: Vince moved page Preserving nets to Preserving user nets --preventing nets from being optimized away: rename for clarify</p>
<hr />
<div>'''Q: How do I preserve user-declared nets so that they don't get optimized away? I would like to see them written out to the netlist file.'''<br />
<br />
There are two approaches :<br />
* globally preserve all user nets<br />
* preserve only selective nets<br />
<br />
<br />
1. Globally preserve all user nets<br />
<br />
The following flags need to be set for global effect :<br />
<br />
set_runtime_flag db_preserve_user_nets 1<br />
set_runtime_flag veri_preserve_user_nets 1 # if using Verilog/SystemVerilog<br />
set_runtime_flag vhdl_preserve_user_nets 1 # if using VHDL<br />
<br />
<br />
2. Preserve only selective nets<br />
<br />
Setting an attribute on a net will prevent it from being optimized away. The attribute can be any attribute, as seen in the examples below.<br />
<br />
Verilog :<br />
<br />
module test (input i, output o);<br />
(* any *) wire willstay;<br />
wire willgo;<br />
(* another = "any" *) reg willstaytoo;<br />
assign o = ~i;<br />
endmodule<br />
<br />
This is the output Verilog netlist :<br />
//<br />
// Verific Verilog Description of module test<br />
//<br />
module test (i, o); // test2.v(1)<br />
input i; // test2.v(1)<br />
output o; // test2.v(1)<br />
<br />
wire willstay /* verific any=1 */ ; // test2.v(2)<br />
wire willstaytoo /* verific another="any" */ ; // test2.v(4)<br />
<br />
not (o, i) ; // test2.v(5)<br />
<br />
endmodule<br />
<br />
<br />
VHDL :<br />
<br />
library ieee;<br />
use ieee.std_logic_1164.all ;<br />
entity test is <br />
port (i : in bit; o : out bit) ;<br />
end entity test;<br />
architecture arch of test is<br />
signal willstay : bit ;<br />
signal willgo : bit ;<br />
signal willstaytoo : bit ; <br />
attribute any : string ;<br />
attribute any of willstay : signal is "" ;<br />
attribute another : string ;<br />
attribute another of willstaytoo : signal is "any" ;<br />
begin<br />
o <= not i ;<br />
end arch ;<br />
<br />
This is the output VHDL netlist :<br />
--<br />
-- Verific VHDL Description of module test<br />
--<br />
library ieee ;<br />
use ieee.std_logic_1164.all ;<br />
entity test is<br />
port (i: in std_logic; -- test2.vhd(4)<br />
o: out std_logic -- test2.vhd(4)<br />
);<br />
end entity test; -- test2.vhd(3)<br />
architecture arch of test is <br />
signal willstay : std_logic; -- any="" -- test2.vhd(8)<br />
signal willstaytoo : std_logic; -- another="any" -- test2.vhd(10) <br />
begin<br />
o <= not i; -- test2.vhd(16) <br />
end architecture arch; -- test2.vhd(3)</div>Vincehttps://www.verific.com/faq/index.php?title=Preserving_nets&diff=767Preserving nets2022-04-01T18:13:33Z<p>Vince: Vince moved page Preserving nets to Preserving user nets --preventing nets from being optimized away: rename for clarify</p>
<hr />
<div>#REDIRECT [[Preserving user nets --preventing nets from being optimized away]]</div>Vincehttps://www.verific.com/faq/index.php?title=Main_Page&diff=765Main Page2022-04-01T18:12:11Z<p>Vince: Undo revision 764 by Vince (talk)</p>
<hr />
<div>'''General'''<br />
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]<br />
* [[Source code customization & Stable release services | Source code customization & Stable release services]]<br />
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]<br />
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]<br />
* [[Verific data structures | What are the data structures in Verific?]]<br />
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]<br />
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]<br />
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]<br />
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]<br />
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]<br />
* [[Release version | How do I tell the version of a Verific software release? ]]<br />
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]<br />
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]<br />
* [[LineFile data from input files | LineFile data from input files]]<br />
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]<br />
* [[Preserving nets | Preserving nets -- preventing nets from being optimized away]]<br />
<br />
'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''<br />
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]<br />
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]<br />
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]<br />
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]<br />
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]<br />
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]<br />
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]<br />
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]<br />
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]<br />
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]<br />
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]<br />
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]<br />
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]<br />
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]<br />
* [[Notes on analysis | SystemVerilog: Notes on analysis]]<br />
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]<br />
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]<br />
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]<br />
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]<br />
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]<br />
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]<br />
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]<br />
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]<br />
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]<br />
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]<br />
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]<br />
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]<br />
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]<br />
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]]<br />
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]<br />
<br />
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]<br />
'''Netlist Database'''<br />
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]<br />
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]<br />
* [[System attributes | Netlist Database: System attributes]]<br />
<br />
'''Output'''<br />
* [[Output file formats | What language formats does Verific support as output?]]<br />
<br />
'''Scripting languages: TCL, Perl, Python'''<br />
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]<br />
<br />
'''Code examples'''<br />
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]<br />
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]<br />
* [[Extract clock enable | Database/C++: Extract clock enable]]<br />
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]<br />
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]<br />
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]<br />
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]<br />
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]<br />
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]<br />
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]<br />
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]<br />
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]<br />
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]<br />
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]<br />
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]<br />
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]<br />
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]<br />
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]<br />
* [[Type Range example | Verilog/C++: Type Range example (simple)]]<br />
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]<br />
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]<br />
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]] <br />
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]<br />
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]<br />
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]<br />
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]<br />
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]<br />
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]<br />
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]<br />
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]<br />
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]<br />
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]<br />
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]<br />
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]<br />
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]<br />
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]<br />
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]<br />
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]</div>Vincehttps://www.verific.com/faq/index.php?title=Main_Page&diff=764Main Page2022-04-01T18:10:47Z<p>Vince: </p>
<hr />
<div>'''General'''<br />
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]<br />
* [[Source code customization & Stable release services | Source code customization & Stable release services]]<br />
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]<br />
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]<br />
* [[Verific data structures | What are the data structures in Verific?]]<br />
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]<br />
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]<br />
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]<br />
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]<br />
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]<br />
* [[Release version | How do I tell the version of a Verific software release? ]]<br />
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]<br />
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]<br />
* [[LineFile data from input files | LineFile data from input files]]<br />
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]<br />
* [[Preserving user nets - preventing nets from being optimized away | Preserving user nets - preventing nets from being optimized away]]<br />
<br />
'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''<br />
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]<br />
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]<br />
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]<br />
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]<br />
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]<br />
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]<br />
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]<br />
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]<br />
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]<br />
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]<br />
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]<br />
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]<br />
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]<br />
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]<br />
* [[Notes on analysis | SystemVerilog: Notes on analysis]]<br />
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]<br />
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]<br />
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]<br />
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]<br />
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]<br />
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]<br />
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]<br />
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]<br />
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]<br />
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]<br />
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]<br />
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]<br />
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]<br />
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]]<br />
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]<br />
<br />
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]<br />
'''Netlist Database'''<br />
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]<br />
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]<br />
* [[System attributes | Netlist Database: System attributes]]<br />
<br />
'''Output'''<br />
* [[Output file formats | What language formats does Verific support as output?]]<br />
<br />
'''Scripting languages: TCL, Perl, Python'''<br />
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]<br />
<br />
'''Code examples'''<br />
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]<br />
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]<br />
* [[Extract clock enable | Database/C++: Extract clock enable]]<br />
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]<br />
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]<br />
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]<br />
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]<br />
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]<br />
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]<br />
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]<br />
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]<br />
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]<br />
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]<br />
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]<br />
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]<br />
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]<br />
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]<br />
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]<br />
* [[Type Range example | Verilog/C++: Type Range example (simple)]]<br />
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]<br />
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]<br />
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]] <br />
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]<br />
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]<br />
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]<br />
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]<br />
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]<br />
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]<br />
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]<br />
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]<br />
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]<br />
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]<br />
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]<br />
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]<br />
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]<br />
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]<br />
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]<br />
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]</div>Vincehttps://www.verific.com/faq/index.php?title=Preserving_user_nets_-_preventing_nets_from_being_optimized_away&diff=763Preserving user nets - preventing nets from being optimized away2022-04-01T18:07:34Z<p>Vince: Created page with "'''Q: How do I preserve user-declared nets so that they don't get optimized away? I would like to see them written out to the netlist file.''' There are two approaches : * gl..."</p>
<hr />
<div>'''Q: How do I preserve user-declared nets so that they don't get optimized away? I would like to see them written out to the netlist file.'''<br />
<br />
There are two approaches :<br />
* globally preserve all user nets<br />
* preserve only selective nets<br />
<br />
<br />
1. Globally preserve all user nets<br />
<br />
The following flags need to be set for global effect :<br />
<br />
set_runtime_flag db_preserve_user_nets 1<br />
set_runtime_flag veri_preserve_user_nets 1 # if using Verilog/SystemVerilog<br />
set_runtime_flag vhdl_preserve_user_nets 1 # if using VHDL<br />
<br />
<br />
2. Preserve only selective nets<br />
<br />
Setting an attribute on a net will prevent it from being optimized away. The attribute can be any attribute, as seen in the examples below.<br />
<br />
Verilog :<br />
<br />
module test (input i, output o);<br />
(* any *) wire willstay;<br />
wire willgo;<br />
(* another = "any" *) reg willstaytoo;<br />
assign o = ~i;<br />
endmodule<br />
<br />
This is the output Verilog netlist :<br />
//<br />
// Verific Verilog Description of module test<br />
//<br />
module test (i, o); // test2.v(1)<br />
input i; // test2.v(1)<br />
output o; // test2.v(1)<br />
<br />
wire willstay /* verific any=1 */ ; // test2.v(2)<br />
wire willstaytoo /* verific another="any" */ ; // test2.v(4)<br />
<br />
not (o, i) ; // test2.v(5)<br />
<br />
endmodule<br />
<br />
<br />
VHDL :<br />
<br />
library ieee;<br />
use ieee.std_logic_1164.all ;<br />
entity test is <br />
port (i : in bit; o : out bit) ;<br />
end entity test;<br />
architecture arch of test is<br />
signal willstay : bit ;<br />
signal willgo : bit ;<br />
signal willstaytoo : bit ; <br />
attribute any : string ;<br />
attribute any of willstay : signal is "" ;<br />
attribute another : string ;<br />
attribute another of willstaytoo : signal is "any" ;<br />
begin<br />
o <= not i ;<br />
end arch ;<br />
<br />
This is the output VHDL netlist :<br />
--<br />
-- Verific VHDL Description of module test<br />
--<br />
library ieee ;<br />
use ieee.std_logic_1164.all ;<br />
entity test is<br />
port (i: in std_logic; -- test2.vhd(4)<br />
o: out std_logic -- test2.vhd(4)<br />
);<br />
end entity test; -- test2.vhd(3)<br />
architecture arch of test is <br />
signal willstay : std_logic; -- any="" -- test2.vhd(8)<br />
signal willstaytoo : std_logic; -- another="any" -- test2.vhd(10) <br />
begin<br />
o <= not i; -- test2.vhd(16) <br />
end architecture arch; -- test2.vhd(3)</div>Vincehttps://www.verific.com/faq/index.php?title=Main_Page&diff=762Main Page2022-04-01T17:38:14Z<p>Vince: </p>
<hr />
<div>'''General'''<br />
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]<br />
* [[Source code customization & Stable release services | Source code customization & Stable release services]]<br />
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]<br />
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]<br />
* [[Verific data structures | What are the data structures in Verific?]]<br />
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]<br />
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]<br />
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]<br />
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]<br />
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]<br />
* [[Release version | How do I tell the version of a Verific software release? ]]<br />
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]<br />
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]<br />
* [[LineFile data from input files | LineFile data from input files]]<br />
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]<br />
* [[Preserving nets | Preserving nets -- preventing nets from being optimized away]]<br />
<br />
'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''<br />
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]<br />
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]<br />
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]<br />
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]<br />
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]<br />
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]<br />
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]<br />
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]<br />
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]<br />
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]<br />
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]<br />
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]<br />
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]<br />
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]<br />
* [[Notes on analysis | SystemVerilog: Notes on analysis]]<br />
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]<br />
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]<br />
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]<br />
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]<br />
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]<br />
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]<br />
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]<br />
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]<br />
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]<br />
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]<br />
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]<br />
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]<br />
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]<br />
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]]<br />
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]<br />
<br />
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]<br />
'''Netlist Database'''<br />
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]<br />
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]<br />
* [[System attributes | Netlist Database: System attributes]]<br />
<br />
'''Output'''<br />
* [[Output file formats | What language formats does Verific support as output?]]<br />
<br />
'''Scripting languages: TCL, Perl, Python'''<br />
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]<br />
<br />
'''Code examples'''<br />
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]<br />
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]<br />
* [[Extract clock enable | Database/C++: Extract clock enable]]<br />
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]<br />
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]<br />
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]<br />
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]<br />
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]<br />
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]<br />
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]<br />
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]<br />
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]<br />
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]<br />
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]<br />
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]<br />
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]<br />
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]<br />
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]<br />
* [[Type Range example | Verilog/C++: Type Range example (simple)]]<br />
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]<br />
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]<br />
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]] <br />
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]<br />
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]<br />
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]<br />
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]<br />
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]<br />
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]<br />
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]<br />
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]<br />
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]<br />
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]<br />
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]<br />
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]<br />
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]<br />
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]<br />
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]<br />
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]</div>Vincehttps://www.verific.com/faq/index.php?title=How_to_save_computer_resources&diff=759How to save computer resources2022-02-11T15:44:36Z<p>Vince: </p>
<hr />
<div>There are compile flags & runtime flags that may help to reduce memory consumption and/or runtime.<br />
Below are some common ones.<br />
<br />
- Compile flag "VERIFIC_MEMORY_MANAGER" in util/VerificSystem.h<br />
Highly recommended.<br />
<br />
Enables the new, zero-overhead, Verific memory manager. Typically reduces memory usage of the Verific software by an additional 20% over the default system memory manager.<br />
- Compile flag "DB_USE_PORT_ORDERED_PORTREF" in database/DBCompileFlags.h<br />
Highly recommended.<br />
<br />
Organizes the PortRef structures in an ordered array rather than a hash table. This saves a significant amount of memory since PortRefs are no longer individually allocated,<br />
and the overhead of a hash table is also saved.<br />
- Compile flag "VERILOG_QUICK_PARSE_V_FILES" in verilog/VeriCompileFlags.h<br />
Normally a -v file may contain multiple module definitions. The Verilog parser is supposed to pick only the required modules from that file.<br />
<br />
However, the file may not contain any of the required modules; instead it is a large file containing many other modules of no interest. In such a case, analyzing and creating a parse tree for the full file will consume much time and memory.<br />
<br />
To prevent this, we provide this compile flag to quickly parse the file and see if it is actually required or not, without creating the parse tree. If it is not required we will ignore the file, otherwise we will fully parse it and pick the required modules.<br />
<br />
- Compile flag "VERIFIC_LINEFILE_INCLUDES_COLUMNS" in util/VerificSystem.h<br />
If you don't need the starting and ending locations including column info, turn this flag off.<br />
<br />
For more details, see [[LineFile data from input files|LineFile data from input files]]<br />
- Runtime flag "veri_improve_include_dir_processing_runtime_for_network_file_system"<br />
Adds directory caching for include directories with simple files (files without a directory specification).<br />
<br />
We read the contents of the directory on first encountering it while checking for an include file. Subsequent searches will find the file in the cache instead of the actual disk.<br />
<br />
The cache is automatically cleared at the end of the veri_file::Analyze() or veri_file::AnalyzeMultipleFiles() calls. Note that we cannot keep it alive after the two analyze calls since there could possibly be a chdir() call which would make the cache invalid.<br />
- Runtime flag "veri_ignore_always_constructs"<br />
<br />
This enables a "light-weighed" RTL elaboration. "always" constructs in the input RTL Verilog file will be skipped over.<br />
<br />
The output netlist is not complete, but is useful if you are interested only in module interfaces and instantiations.<br />
<br />
Note that this flag is active only during RTL elaboration, not analysis. The input files still need to be Verilog-legal.</div>Vincehttps://www.verific.com/faq/index.php?title=Black_box,_empty_box,_and_unknown_box&diff=749Black box, empty box, and unknown box2021-11-03T17:51:39Z<p>Vince: </p>
<hr />
<div>In the Verific Netlist Database, a Netlist can be a black box, an empty box, or an unknown box (and of course, a "normal" box).<br />
# An unknown box is a Netlist that is:<br />
#* from an instantiation of an undefined Verilog module<br />
#* from an instantiation of a VHDL component without binding entity<br />
# A black box is a Netlist that contains no Instances (NumOfInsts() == 0) and no Nets ((NumOfNets() == 0). It can be:<br />
#* an unknown box<br />
#* a Verific Primitive or Operator<br />
#* a Netlist that has errors during RTL elaboration<br />
#* set from VeriModule::SetCompileAsBlackbox()<br />
#* set from VhdlPrimaryUnit::SetCompileAsBlackbox()<br />
# An empty box is a Netlist that contains no Instances and no port-to-port connections. It can be:<br />
#* a black box<br />
#* a user-defined module/entity with ports but no contents<br />
#* a user-defined module/entity that has no assignments to its outputs<br />
<br />
If it is desired to have the user-defined module declarations written out into the output netlist, including those of black boxes and empty boxes, the runtime flag 'db_verilog_writer_write_blackboxes' can be set to different values to control this behavior:<br />
* value > 1: print all Netlists except Primitives<br />
* value = 1: print all Netlists except Primitives and Netlists with ' unknown_design' attribute<br />
* value = 0: print all Netlists except Primitives, Netlists with ' unknown_design' attribute and 'IsBlackBox()' Netlists<br />
* default value = 0<br />
<br />
For more details on how the Verific RTL elaborator handles Instances of unknown boxes, please read [[How Verific elaborator handles blackboxes/unknown boxes]]<br />
<br />
<nowiki><br />
#include "Set.h"<br />
#include "Message.h"<br />
#include "Strings.h"<br />
#include "veri_file.h"<br />
#include "vhdl_file.h"<br />
#include "VeriModule.h"<br />
#include "VeriWrite.h"<br />
#include "DataBase.h"<br />
<br />
#ifdef VERIFIC_NAMESPACE<br />
using namespace Verific ;<br />
#endif<br />
<br />
void Accumulate(Netlist *netlist, Set &done) ;<br />
<br />
int main() {<br />
vhdl_file::SetDefaultLibraryPath("../vdbs");<br />
<br />
if (!vhdl_file::Analyze("fromvhdl.vhd")) return 1 ;<br />
if (!veri_file::Analyze("test.v", veri_file::VERILOG_2K)) return 1 ;<br />
<br />
// blackboxing module "willbeblackboxed"<br />
VeriModule *tobeblackboxed = veri_file::GetModule("willbeblackboxed");<br />
tobeblackboxed->SetCompileAsBlackbox();<br />
<br />
veri_file::Elaborate("top");<br />
<br />
Netlist *top = Netlist::PresentDesign() ;<br />
if (!top) {<br />
Message::PrintLine("cannot find any handle to the top-level netlist") ;<br />
return 1 ;<br />
}<br />
<br />
Message::Msg(VERIFIC_INFO, 0, top->Linefile(), "top level design is '%s(%s)'",<br />
top->Owner()->Name(), top->Name()) ;<br />
<br />
// Lets accumulate all netlist<br />
Set netlists(POINTER_HASH) ;<br />
Accumulate(top, netlists) ;<br />
<br />
// Iterate over all Netlists in the design<br />
Netlist *netlist ;<br />
SetIter si ;<br />
FOREACH_SET_ITEM(&netlists, si, &netlist) {<br />
Message::Msg(VERIFIC_INFO, 0, 0, "*** netlist '%s' of cell '%s'", netlist->Name(), netlist->Owner()->Name()) ;<br />
// What language does it come from?<br />
if (netlist->GetAttValue(" language")) {<br />
Message::Msg(VERIFIC_INFO, 0, 0, " from %s", netlist->GetAttValue(" language"));<br />
} else {<br />
Message::Msg(VERIFIC_INFO, 0, 0, " no language");<br />
}<br />
// Is it a Verific primitive or operator?<br />
if (netlist->IsPrimitive() || netlist->IsOperator()) {<br />
Message::Msg(VERIFIC_INFO, 0, 0, " a primitive/operator");<br />
}<br />
// Check attribute for unknown box<br />
const Att *attr = netlist->GetAtt(" unknown_design"); // note the leading space character<br />
if (attr) {<br />
if (Strings::compare (attr->Value(),"1")) {<br />
// attribute value = "1" : instantiated in a Verilog module<br />
Message::Msg(VERIFIC_INFO, 0, 0, " an unknown box instantiated in a Verilog module");<br />
}<br />
else if (Strings::compare (attr->Value(),"2")) {<br />
// attribute value = "2" : instantiated in a VHDL architecture<br />
Message::Msg(VERIFIC_INFO, 0, 0, " an unknown box instantiated in a VHDL architecture");<br />
}<br />
}<br />
if (netlist->IsBlackBox()) {<br />
Message::Msg(VERIFIC_INFO, 0, 0, " a black box");<br />
}<br />
if (netlist->IsEmptyBox()) {<br />
Message::Msg(VERIFIC_INFO, 0, 0, " an empty box");<br />
}<br />
<br />
}<br />
VeriWrite veriWriter;<br />
veriWriter.WriteFile("netlistout.v", top) ;<br />
<br />
return 0 ;<br />
}<br />
<br />
// This function is recursive in nature, and collects all other<br />
// netlists that the incoming netlist depends on in a container.<br />
<br />
void Accumulate(Netlist *netlist, Set &done)<br />
{<br />
if (!netlist) return ; // Ignore NULL netlists<br />
<br />
SetItem *item = done.GetItem(netlist) ;<br />
if (item) {<br />
return ; // We've already been here<br />
}<br />
<br />
Instance *inst ;<br />
MapIter mi ;<br />
FOREACH_INSTANCE_OF_NETLIST(netlist, mi, inst) {<br />
// Now go into the netlist associated with the instance<br />
Accumulate(inst->View(), done) ;<br />
}<br />
<br />
done.Insert(netlist) ;<br />
}<br />
</nowiki><br />
test.v<br />
<nowiki><br />
module nocontents (input a, output o);<br />
endmodule<br />
<br />
module willbeblackboxed (input a, b, output o);<br />
assign o = a ^ b;<br />
endmodule<br />
<br />
module containserror (input a, b, output o);<br />
assign o = a & b;<br />
assign o = a | b;<br />
endmodule<br />
<br />
module emptybox (input a, output o); // no outputs are driven<br />
wire i = a;<br />
endmodule<br />
<br />
module normal (input a, b, output o);<br />
assign o = a & b;<br />
endmodule<br />
<br />
module top (input i1, i2, i3, i4, i5, i6, i7, i8, i9, ia, ib,<br />
output o1, o2, o3, o4, o5);<br />
nocontents u_nocontents (i1, o1);<br />
willbeblackboxed u_willbeblackboxed (i2, i3, o2);<br />
containserror u_containserror (i4, i5, o3);<br />
emptybox u_emptybox (i9, );<br />
unknownverilog u_unknownverilog (i6, o4);<br />
normal u_normal (i7, i8, o5);<br />
fromvhdl u_fromvhdl (ia, ib, o6);<br />
endmodule<br />
</nowiki><br />
fromvhdl.vhd:<br />
<nowiki><br />
library std;<br />
use std.all;<br />
entity fromvhdl is<br />
port ( a, b: in bit; o: out bit );<br />
end entity;<br />
architecture test of fromvhdl is<br />
component unknownvhdl<br />
port ( a, b : in bit; o : out bit);<br />
end component;<br />
begin<br />
u_unknownvhdl: unknownvhdl port map (a, b, o);<br />
end architecture;<br />
</nowiki><br />
Run:<br />
<nowiki><br />
$ test-linux<br />
INFO: The default VHDL library search path is now "/mnt/Verific/extra_tests/vdbs" (VHDL-1504)<br />
-- Analyzing VHDL file 'fromvhdl.vhd' (VHDL-1481)<br />
-- Restoring VHDL parse-tree 'std.standard' from '/mnt/Verific/extra_tests/vdbs/std/standard.vdb' (VHDL-1493)<br />
fromvhdl.vhd(3): INFO: analyzing entity 'fromvhdl' (VHDL-1012)<br />
fromvhdl.vhd(6): INFO: analyzing architecture 'test' (VHDL-1010)<br />
-- Analyzing Verilog file 'test.v' (VERI-1482)<br />
test.v(21): INFO: compiling module 'top' (VERI-1018)<br />
test.v(1): INFO: compiling module 'nocontents' (VERI-1018)<br />
test.v(4): INFO: compiling module 'willbeblackboxed' (VERI-1018)<br />
test.v(8): INFO: compiling module 'containserror' (VERI-1018)<br />
test.v(9): ERROR: net 'o' is constantly driven from multiple places (VDB-1000)<br />
test.v(10): ERROR: another driver from here (VDB-1001)<br />
test.v(8): INFO: module 'containserror' remains a black box, due to errors in its contents (VERI-1073)<br />
test.v(13): INFO: compiling module 'emptybox' (VERI-1018)<br />
test.v(27): WARNING: instantiating unknown module 'unknownverilog' (VERI-1063)<br />
test.v(17): INFO: compiling module 'normal' (VERI-1018)<br />
test.v(29): INFO: going to VHDL side to elaborate design unit 'fromvhdl' (VERI-1231)<br />
fromvhdl.vhd(3): INFO: executing 'fromvhdl(test)' (VHDL-1067)<br />
fromvhdl.vhd(9): WARNING: 'unknownvhdl' remains a black box since it has no binding entity (VHDL-1250)<br />
test.v(29): INFO: back to Verilog to continue elaboration (VERI-1232)<br />
test.v(21): INFO: top level design is top()<br />
INFO: *** netlist '' of cell 'nocontents'<br />
INFO: from verilog<br />
INFO: an empty box<br />
INFO: *** netlist '' of cell 'willbeblackboxed'<br />
INFO: from verilog<br />
INFO: a black box<br />
INFO: an empty box<br />
INFO: *** netlist '' of cell 'containserror'<br />
INFO: from verilog<br />
INFO: a black box<br />
INFO: an empty box<br />
INFO: *** netlist 'INTERFACE' of cell 'VERIFIC_BUF'<br />
INFO: no language<br />
INFO: a primitive/operator<br />
INFO: a black box<br />
INFO: an empty box<br />
INFO: *** netlist '' of cell 'emptybox'<br />
INFO: from verilog<br />
INFO: *** netlist 'OrderedPorts' of cell 'unknownverilog'<br />
INFO: no language<br />
INFO: an unknown box instantiated in a Verilog module<br />
INFO: a black box<br />
INFO: an empty box<br />
INFO: *** netlist 'INTERFACE' of cell 'VERIFIC_AND'<br />
INFO: no language<br />
INFO: a primitive/operator<br />
INFO: a black box<br />
INFO: an empty box<br />
INFO: *** netlist '' of cell 'normal'<br />
INFO: from verilog<br />
INFO: *** netlist '' of cell 'unknownvhdl'<br />
INFO: from vhdl<br />
INFO: an unknown box instantiated in a VHDL architecture<br />
INFO: a black box<br />
INFO: an empty box<br />
INFO: *** netlist 'test' of cell 'fromvhdl'<br />
INFO: from vhdl<br />
INFO: *** netlist '' of cell 'top'<br />
INFO: from verilog<br />
-- Writing netlist 'top' to Verilog file 'netlistout.v' (VDB-1030)<br />
$<br />
</nowiki></div>Vincehttps://www.verific.com/faq/index.php?title=How_to_get_all_Verilog_files_being_analyzed&diff=744How to get all Verilog files being analyzed2021-10-20T15:57:44Z<p>Vince: </p>
<hr />
<div>'''Q: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?'''<br />
<br />
Use this C++:<br />
<br />
Array *GetAllAbsFileNames() {<br />
Array *files = new Array() ;<br />
unsigned file_id = 2 ; // for Verific releases Sep18 and older, use "unsigned file_id = 1 ;" - See VIPER #14058<br />
const char *file_name ;<br />
while ((file_name=LineFile::GetAbsFileNameFromId(file_id++))!=0) {<br />
// Instead of LineFile::GetAbsFileNameFromId(), the API LineFile::GetFileNameFromId()<br />
// can also be used if relative file name is required.<br />
// This is a file we processed:<br />
files->Insert(file_name) ;<br />
}<br />
// Now "files" array should contain names of all the files analyzed<br />
if (!files->Size()) { delete files ; files = 0 ; }<br />
return files ;<br />
}<br />
<br />
Or this Perl:<br />
<br />
my $topfile = "top.v"; # input filename<br />
my $stubfile = "stubs.v"; # filename for -v option<br />
my $dir = "dir"; # dir name for -y option<br />
# Verific::veri_file::AddYDir($dir); # -y option<br />
Verific::veri_file::AddVFile($stubfile); # -v option<br />
if (!Verific::veri_file::Analyze($topfile)) {<br />
exit (1) ;<br />
}<br />
if (!Verific::veri_file::AnalyzeFull()) { # IMPORTANT: need to call this to process -v, -y, ....<br />
exit (1) ;<br />
}<br />
my $file_id = 2; # for Verific releases Sep18 and older, use "my $file_id = 1;" - See VIPER #14058<br />
# my $file_name=Verific::LineFile::GetAbsFileNameFromId($file_id); # for file with full path<br />
$file_name=Verific::LineFile::GetFileNameFromId($file_id); # for just filename<br />
while ($file_name ne "") {<br />
print "filename analyzed: $file_name\n";<br />
$file_id = $file_id + 1;<br />
# $file_name=Verific::LineFile::GetAbsFileNameFromId($file_id); # for file with full path<br />
$file_name=Verific::LineFile::GetFileNameFromId($file_id); # for just filename<br />
}<br />
<br />
How this works:<br />
<br />
# Verific keeps file_name vs. file_id mapping.<br />
# File_id starts from 1 and increases by 1.<br />
# LineFile::GetAbsFileNameFromId()/GetFileNameFromId() returns 0 for non-existing id.<br />
# The code keeps calling the API with incremented file_id until getting a 0.</div>Vincehttps://www.verific.com/faq/index.php?title=Source_code_customization_%26_Stable_release_services&diff=735Source code customization & Stable release services2021-10-11T20:28:10Z<p>Vince: </p>
<hr />
<div>On Verific's system, each of our licensees has a separate code branch. There are mechanisms in place to prevent cross-contamination among code branches, helping to ensure their privacy and security. With this implementation Verific is able to offer two complimentary services to our licensees : ''Source Code Customization'' and ''Stable Release Maintenance''.<br />
<br />
<br />
'''1. Source Code Customization<br />
'''<br />
<br />
A licensee can send in custom code modifications to be merged into their branch maintained by Verific. The customizations will be included in future source code releases so that the licensee will not need to merge them manually each time. Please note the following :<br />
<br />
* The modified code should be complete and compilable on Verific's system.<br />
<br />
* Zip the modified code with the same password used for the monthly code releases.<br />
<br />
* Mention the Verific release version that the modifications are based upon.<br />
<br />
The licensee can include testcases that exercise the customized code. These testcases will be added to the regression testsuite of the licensee's code branch.<br />
<br />
The best way to initiate this process is for the licensee to file a VIPER issue with Type "Merge Request" and attach the zip file of the code modifications to the VIPER issue. This VIPER issue will be closed (not just "fixed") when the code merge has been completed. The licensee will receive an email notice when the VIPER issue is closed.<br />
<br />
<br />
<br />
'''2. Stable Release Mantenance<br />
'''<br />
<br />
A Stable release is a physically separate branch of a licensee's code on Verific's system. It is treated as a distinct "customer" branch. There are no connections between a Stable branch and the licensee's normal branch. A Stable branch is usually requested by a licensee when a specific monthly normal branch has been extensively tested and integrated into the licensee's tool and there is a need to maintain this branch of code for a longer period of time than the regular monthly Verific releases. Some notes to keep in mind about the Stable branch :<br />
<br />
* After creation, Stable branch code can only be changed to fix Stable branch VIPER issues. VIPER issues filed for a Stable branch are treated as "customer-specific". In other words, VIPER fixes in a Stable branch don't go into the normal branch and, likewise, VIPER fixes in the normal branch don't go into a Stable branch.<br />
<br />
* To avoid having new issues introduced into a Stable branch, only defect (not enhancement) VIPERs are allowed for a Stable branch.<br />
<br />
* If an issue needs to be fixed in both a Stable branch and in the normal branch, two separate VIPER issues will need to be filed : one for the Stable branch and one for the normal branch.<br />
<br />
* Stable branch code can not be merged into normal branch code.<br />
<br />
* When a Stable branch has served its purpose and is ready to be retired, the licensee should inform Verific about this decision as soon as possible. We will then archive the branch and stop its maintenance, helping to free up our time and resources.</div>Vincehttps://www.verific.com/faq/index.php?title=Source_code_customization_%26_Stable_release_services&diff=734Source code customization & Stable release services2021-10-08T23:37:13Z<p>Vince: </p>
<hr />
<div>On Verific's system, each of our licensees has a separate code branch. There are mechanisms in place to prevent cross-contamination among code branches, helping to ensure their privacy and security. With this implementation Verific is able to offer two complimentary services to our licensees : ''Source Code Customization'' and ''Stable Release Maintenance''.<br />
<br />
<br />
'''1. Source Code Customization<br />
'''<br />
<br />
A licensee can send in custom code modifications to be merged into their branch maintained by Verific. The customizations will be included in future source code releases so that the licensee will not need to merge them manually each time. Please note the following :<br />
<br />
* The modified code should be complete and compilable on Verific's system.<br />
<br />
* Zip the modified code with the same password used for the monthly code releases.<br />
<br />
* Mention the Verific release version that the modifications are based upon.<br />
<br />
The licensee can include testcases that exercise the customized code. These testcases will be added to the regression testsuite of the licensee's code branch.<br />
<br />
The best way to initiate this process is for the licensee to file a VIPER issue with Type "Merge Request" and attach the zip file of the code modifications to the VIPER issue. This VIPER issue will be closed (not just "fixed") when the code merge has been completed. The licensee will receive an email notice when the VIPER issue is closed.<br />
<br />
<br />
<br />
'''2. Stable Release Mantenance<br />
'''<br />
<br />
A STABLE release is a physically separate branch of a licensee's code on Verific's system. It is treated as a distinct "customer" branch. There are no connections between a STABLE branch and the licensee's NORMAL branch. A STABLE branch is usually requested by a licensee when a specific monthly NORMAL branch has been extensively tested and integrated into the licensee's tool and there is a need to maintain this branch of code for a longer period of time than the regular monthly Verific releases. Some notes to keep in mind about the STABLE branch :<br />
<br />
* After creation, STABLE branch code can only be changed to fix STABLE branch VIPER issues. VIPER issues filed for a STABLE branch are treated as "customer-specific". In other words, VIPER fixes in a STABLE branch don't go into the NORMAL branch and, likewise, VIPER fixes in the NORMAL branch don't go into a STABLE branch.<br />
<br />
* To avoid having new issues introduced into a STABLE branch, only defect (not enhancement) VIPERs are allowed for a STABLE branch.<br />
<br />
* If an issue needs to be fixed in both a STABLE branch and in the NORMAL branch, two separate VIPER issues will need to be filed : one for the STABLE branch and one for the NORMAL branch.<br />
<br />
* STABLE branch code can not be merged into NORMAL branch code.<br />
<br />
* When a STABLE branch has served its purpose and is ready to be retired, the licensee should inform Verific about this decision as soon as possible. We will then archive the branch and stop its maintenance, helping to free up our time and resources.</div>Vincehttps://www.verific.com/faq/index.php?title=Main_Page&diff=716Main Page2021-08-13T01:53:06Z<p>Vince: </p>
<hr />
<div>'''General'''<br />
* [[How to get best support from Verific | '''''How to get best support from Verific''''']]<br />
* [[How to save computer resources | How to save computer resources (memory consumption & runtime)]]<br />
* [[Original RTL language | How do I know what language a Netlist in the netlist database comes from?]]<br />
* [[Verific data structures | What are the data structures in Verific?]]<br />
* [[Remove Verific data structures | How do I remove all Verific data structures in memory?]]<br />
* [[Does Verific build CDFG? | Does Verific build control and data flow graph (CDFG)?]]<br />
* [[Does Verific support XMR?| Does Verific support cross module references (XMR)?]]<br />
* [[Compile-time/run-time flags | Are there options to control Verific software's behavior? Compile-time & run-time flags.]]<br />
* [[Message handling | How do I downgrade/upgrade messages from Verific? How do I get messages with more details?]]<br />
* [[Release version | How do I tell the version of a Verific software release? ]]<br />
* [[Simulation models for Verific primitives | Where do I find simulation models for Verific primitives (VERIFIC_XOR, VERIFIC_DFFRS, ....)? ]]<br />
* [[Tcl library path| How to correct building (linking) issue "/usr/bin/ld: cannot find -ltcl"]]<br />
* [[LineFile data from input files | LineFile data from input files]]<br />
* [[Difference between RTL and gate-level simulations - Flipflop with async set and async reset | Difference between RTL and gate-level simulations - Flipflop with async set and async reset]]<br />
<br />
'''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''<br />
* [[How to get all Verilog files being analyzed | Verilog: I'm using -v, -y, .... After Verific is done with the analysis, how do I get a list of all the files being analyzed?]]<br />
* [[Included files associated with a Verilog source file | Verilog: How do I get the list of included files associated with a Verilog source file?]]<br />
* [[How to get type/initial value of parameters | Verilog: How to get type/initial value of parameters.]]<br />
* [[Verilog ports being renamed | Verilog: Why are the ports in original Verilog file renamed to p1, p2, ....?]]<br />
* [[Design with System Verilog and Verilog 2001 files | Verilog: For a design consisting of a mixture of Verilog 2001 and SystemVerilog input files, should I parse all the files as SystemVerilog?]]<br />
* [[How to get module ports from Verilog parsetree | Verilog: From the Verilog parsetree, how can I get the ports of a module?]]<br />
* [[How to change name of id in Verilog parsetree | Verilog: How do I change the name of an id (VeriidDef) in Verilog parsetree?]]<br />
* [[How to get library containing nested module | Verilog: How do I get nested modules and get the library that contains the nested module?]]<br />
* [[How to get linefile information of macro definitions | Verilog: How do I get linefile information of macro definitions?]]<br />
* [[How to find port dimensions | Verilog: How do I get port dimensions?]]<br />
* [[Instance - Module binding order | Verilog: What is the order of binding modules to instances?]]<br />
* [[How Verific elaborator handles blackboxes/unknown boxes | Verilog: How Verific elaborator handles blackboxes/unknown boxes]]<br />
* [[Constant expression replacement | Verilog: Does Verific replace constant expressions with their respective values?]]<br />
* [[Defined macros become undefined - MFCU vs SFCU | SystemVerilog: Why does Verific complain about undefined macros for macros defined in a different file (Compilation Unit)?]]<br />
* [[Notes on analysis | SystemVerilog: Notes on analysis]]<br />
* [[How to get enums from Verilog parsetree | SystemVerilog: From the parsetree, how can I get the enums declared in a module?]]<br />
* [[How to identify packages being imported into a module | SystemVerilog: How do I identify packages being imported into a module?]]<br />
* [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]<br />
* [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]<br />
* [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]<br />
* [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures '''(under construction)'''.]]<br />
* [[Prettyprint to a string | Verilog/VHDL: How to prettyprint a parsetree node to a string.]]<br />
* [[Static elaboration | Verilog/VHDL: What does 'static elaboration' do?]]<br />
* [[How to ignore a (not used) parameter/generic in elaboration. | Verilog/VHDL: How to ignore a (not used) parameter/generic in elaboration.]]<br />
* [[What VeriModule* or VhdlPrimaryUnit* the Netlist comes from? | Verilog/VHDL: For a Netlist in the netlist database, is there a clean way to look back at what VeriModule* or VhdlPrimaryUnit* the Netlist was derived from?]]<br />
* [[Cross-reference between the original RTL files and the elaborated netlist | Verilog/VHDL: Is there a way to cross-reference between the original RTL design files and the elaboration netlist?]]<br />
* [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]<br />
* [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]<br />
* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units with "_default" suffix in their names. Why? And what are they?]]<br />
* [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]<br />
<br />
* [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]<br />
'''Netlist Database'''<br />
* [[Logic optimization across hierarchy boundaries | Netlist Database: Does Verific perform logic optimization across hierarchy boundaries?]]<br />
* [[Bit-blasting a multi-port RAM instance | Netlist Database: Bit-blasting a multi-port RAM instance]]<br />
* [[System attributes | Netlist Database: System attributes]]<br />
<br />
'''Output'''<br />
* [[Output file formats | What language formats does Verific support as output?]]<br />
<br />
'''Scripting languages: TCL, Perl, Python'''<br />
* [[What languages can I use with Verific software? | What programming languages can I use with Verific software?]]<br />
<br />
'''Code examples'''<br />
* [[How to use RegisterCallBackMsg() | Util/C++: How to use RegisterCallBackMsg()]]<br />
* [[Write out an encrypted netlist | Database/C++: Write out an encrypted netlist]]<br />
* [[Extract clock enable | Database/C++: Extract clock enable]]<br />
* [[Black box, empty box, and unknown box | Database/C++: Black box, empty box, and unknown box]]<br />
* [[Replacing Verific built-in primitives/operators with user implementations | Database/C++: Replacing Verific built-in primitives/operators with user implementations]]<br />
* [[Hierarchy tree RTL elaboration | Database/Perl: Simple example of hierarchy tree elaboration]]<br />
* [[Create a Netlist Database from scratch (not from RTL elaboration) | Database/Perl/TCL: Create a Netlist Database from scratch (not from RTL elaboration)]]<br />
* [[Buffering signals and ungrouping | Database/Verilog: Buffering signals and ungrouping (flattening) in the Netlist Database]]<br />
* [[Memory elements of a RamNet | Database/Verilog/C++: Memory elements of a RamNet]]<br />
* [[Process -f file and explore the Netlist Database (C++)| Database/Verilog/C++: Process -f file and explore the Netlist Database]]<br />
* [[Process -f file and explore the Netlist Database (py)| Database/Verilog/Python: Process -f file and explore the Netlist Database]]<br />
* [[Fanout cone and grouping | Database/Verilog/Perl: Fanout cone and grouping in the Netlist Database]]<br />
* [[Simple example of visitor pattern | Verilog/C++: Simple examples of visitor pattern]]<br />
* [[Statically elaborate with different values of parameters | Verilog/C++: Statically elaborate with different values of parameters]]<br />
* [[Prettyprint all modules in the design hierarchy | Verilog/C++: Prettyprint all modules in the design hierarchy]]<br />
* [[Getting instances' parameters | Verilog/C++: Getting instances' parameters]]<br />
* [[Accessing and evaluating module's parameters | Verilog/C++: Accessing and evaluating module's parameters]]<br />
* [[Visiting Hierarchical References (VeriSelectedName) | Verilog/C++: Visiting Hierarchical References (VeriSelectedName)]]<br />
* [[Type Range example | Verilog/C++: Type Range example (simple)]]<br />
* [[Using stream input to ignore input file | Verilog/C++: Using stream input to ignore input file]]<br />
* [[How to tell if a module has encrypted contents | Verilog/C++: How to tell if a module has encrypted contents]]<br />
* [[Comment out a line using text based design modification and parsetree modification | Verilog/C++: Comment out a line using text-based design modification and parsetree modification]] <br />
* [[Verilog/C++: How to use IsUserDeclared() : Example for port associations]]<br />
* [[How to create new module in Verilog parsetree | Verilog/C++: How to create new module in Verilog parsetree]]<br />
* [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]<br />
* [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]<br />
* [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]<br />
* [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]<br />
* [[How to get driving net of an instance | Verilog/C++: How to get driving net of an instance]]<br />
* [[Type Range example with multi-dimensional arrays| Verilog/C++/Perl: Type Range example with multi-dimensional arrays]]<br />
* [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]<br />
* [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]<br />
* [[Access attributes of ports in parsetree | Verilog/Perl: Access attributes of ports in parsetree and from netlist]]<br />
* [[Retrieve package name for user-defined variable types | SystemVerilog/C++/Python: Retrieve package name for user-defined variable types]]<br />
* [[Pretty-print a module and the packages imported by the module | SystemVerilog/C++: Pretty-print a module and the packages imported by the module]]<br />
* [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]<br />
* [[Traverse instances in parsetree | Verilog/VHDL/C++: Traverse instances in parsetree]]<br />
* [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]</div>Vincehttps://www.verific.com/faq/index.php?title=How_to_get_driving_net_of_an_instance&diff=715How to get driving net of an instance2021-08-13T01:40:24Z<p>Vince: Created page with "C++: <nowiki> #include "Strings.h" #include "Array.h" #include "Message.h" #include "veri_nl_file.h" #include "DataBase.h" #include "VeriWrite.h" #ifdef VERIFIC_NAMESPACE us..."</p>
<hr />
<div>C++:<br />
<nowiki><br />
#include "Strings.h"<br />
#include "Array.h"<br />
#include "Message.h"<br />
#include "veri_nl_file.h"<br />
#include "DataBase.h"<br />
#include "VeriWrite.h"<br />
<br />
#ifdef VERIFIC_NAMESPACE<br />
using namespace Verific ;<br />
#endif<br />
<br />
int main()<br />
{<br />
if (!veri_nl_file::Read("mid.v","work")) return 1 ;<br />
Netlist *mid = Netlist::PresentDesign() ;<br />
if (!mid) {<br />
Message::PrintLine("cannot find any handle to 'mid' netlist") ;<br />
return 2 ;<br />
}<br />
<br />
if (!veri_nl_file::Read("top.v","work")) return 3 ;<br />
Netlist *top = Netlist::PresentDesign() ;<br />
if (!top) {<br />
Message::PrintLine("cannot find any handle to 'top' netlist") ;<br />
return 4 ;<br />
}<br />
<br />
VeriWrite veriWriter;<br />
// Write out the design before any modifications<br />
if (!veriWriter.WriteFile("before.v", top)) return 4 ;<br />
<br />
// Lets get a handle to instance 'mid_bot'<br />
Instance *bot_inst = mid->GetInst("mid_bot");<br />
if (!bot_inst) {<br />
Message::PrintLine("cannot find instance 'mid_bot' netlist") ;<br />
return 5 ;<br />
}<br />
<br />
Netlist *bot_nl = bot_inst->View();<br />
if (!bot_nl) {<br />
Message::PrintLine("cannot find netlist (view) of instance 'mid_bot'") ;<br />
return 5 ;<br />
}<br />
<br />
Port *bot_port = bot_nl->GetPort ("i");<br />
if (!bot_port) {<br />
Message::PrintLine("cannot find port") ;<br />
return 5 ;<br />
}<br />
<br />
// Get the portref for port 'i' of 'mid_bot'<br />
PortRef *bot_pr = bot_inst->GetPortRef(bot_port);<br />
if (!bot_pr) {<br />
Message::PrintLine("cannot find portref");<br />
return 5 ;<br />
}<br />
<br />
Net *net = bot_pr->GetNet();<br />
if (!net) {<br />
Message::PrintLine("cannot find net") ;<br />
return 5 ;<br />
}<br />
<br />
Netlist *view = bot_inst->Owner();<br />
if (!view) {<br />
Message::PrintLine("cannot find view");<br />
return 5 ;<br />
}<br />
if (view->NumOfRefs() > 1) {<br />
// This netlist is instantiated more than once; need to uniquify it to ensure unique driving nets<br />
SetIter i ;<br />
Instance *inst ;<br />
FOREACH_REFERENCE_OF_NETLIST (view, i, inst) {<br />
if (!Strings::compare (inst->Name(), "top_mid_2")) continue; // Only interested in instance "top_mid_2"<br />
Cell *owner = view->Owner() ;<br />
Netlist *new_netlist = view->Copy() ;<br />
new_netlist->SetName(0) ; // Force a made-up name for the new netlist<br />
if (owner) (void) owner->Add(new_netlist) ;<br />
// Swap the instance to the new netlist<br />
inst->ReplaceView(new_netlist, 0 /* By port order is faster */, 0 /* By port bit is faster */) ;<br />
view = new_netlist ;<br />
}<br />
}<br />
<br />
Message::PrintLine("**** In Netlist '", view->Name(), "' of cell '", view->Owner()->Name(), "'");<br />
Message::PrintLine(" Found net '", net->Name(), "'");<br />
Message::PrintLine(" driving port '", bot_port->Name(), "' of instance '", bot_inst->Name(), "'");<br />
<br />
// Write out the design after uniquification<br />
if (!veriWriter.WriteFile("after.v", top)) return 4 ;<br />
<br />
return 0 ;<br />
}<br />
</nowiki><br />
<br />
top.v<br />
<nowiki><br />
module top (output topo2, topo1, input topi2, topi1);<br />
mid top_mid_1 (topo1, topi1);<br />
mid top_mid_2 (topo2, topi2);<br />
endmodule<br />
</nowiki><br />
<br />
mid.v<br />
<nowiki><br />
module bot (output o, input i);<br />
endmodule<br />
<br />
module mid(output mido, input midi);<br />
bot mid_bot (mido, midi);<br />
endmodule<br />
</nowiki><br />
<br />
Run Output :<br />
<nowiki><br />
-- Reading structural Verilog file 'mid.v' (VNLR-1084)<br />
mid.v(1): INFO: compiling module 'bot' (VNLR-1012)<br />
mid.v(4): INFO: compiling module 'mid' (VNLR-1012)<br />
mid.v(4): INFO: setting 'mid' as the top level module (VNLR-1015)<br />
-- Reading structural Verilog file 'top.v' (VNLR-1084)<br />
top.v(1): INFO: compiling module 'top' (VNLR-1012)<br />
top.v(1): INFO: setting 'top' as the top level module (VNLR-1015)<br />
-- Writing netlist 'top' to Verilog file 'before.v' (VDB-1030)<br />
-- **** In Netlist 'v1' of cell 'mid'<br />
-- Found net 'midi'<br />
-- driving port 'i' of instance 'mid_bot'<br />
-- Writing netlist 'top' to Verilog file 'after.v' (VDB-1030)<br />
</nowiki></div>Vincehttps://www.verific.com/faq/index.php?title=Message_handling&diff=710Message handling2021-07-30T04:20:28Z<p>Vince: </p>
<hr />
<div>'''Q: How do I upgrade/downgrade messages from Verific?'''<br />
<br />
Verific message table, with notation as whether the error can be safely downgraded: [http://www.verific.com/docs/index.php?title=Message_Downgrading_Table Verific Message Table]<br />
<br />
(Access to Verific On-line Documentation requires login. Contact Verific if you don't know/don't have credentials).<br />
<br />
You can set any message to any type below:<br />
<nowiki><br />
VERIFIC_NONE, // print no prefix<br />
VERIFIC_ERROR, // print ERROR:<br />
VERIFIC_WARNING, // print WARNING:<br />
VERIFIC_IGNORE, // ignore message (do not print message):<br />
VERIFIC_INFO, // print INFO:<br />
VERIFIC_COMMENT, // print --<br />
VERIFIC_PROGRAM_ERROR // print PROGRAM_ERROR<br />
</nowiki><br />
For C++, use the following APIs:<br />
<nowiki><br />
Message::SetMessageType() - Force a message type by message id<br />
Message::GetMessageType() - Get the message type by message id<br />
Message::ClearMessageType() - Clear a message type by message id<br />
Message::SetAllMessageType() - Force all messages of type 'orig' to behave as type 'type'.<br />
Message::ClearAllMessageTypes() - Clear all forced message types<br />
</nowiki><br />
For Tcl, use the following commands:<br />
<nowiki><br />
setmsgtype<br />
clearmsgtype<br />
</nowiki><br />
Some Perl command examples:<br />
<nowiki><br />
# ignore message VNLR-1015<br />
Verific::Message::SetMessageType("VNLR-1015", $Verific::VERIFIC_IGNORE);<br />
# ignore all warning messages<br />
Verific::Message::SetAllMessageType($Verific::VERIFIC_WARNING, $Verific::VERIFIC_IGNORE);<br />
</nowiki><br />
Note that downgrading an error may have unpredictable/undesirable results.<br />
<br />
<br />
'''Q: How do I get messages with more details?'''<br />
<br />
For "syntax error" messages, you can get messages with more details by enabling compile flag "VERIFIC_PRODUCE_VERBOSE_SYNTAX_ERROR_MESSAGE" or its runtime equivalent "verific_produce_verbose_syntax_error_message".<br />
<br />
With these flags enabled, for syntax errors, the parsers will print the whole line and point to the exact token where the issue is.<br />
<br />
For example, with:<br />
<nowiki><br />
1. module test (input c, output reg o) ;<br />
2. always@(*)<br />
3. unique priority case (c)<br />
4. 1'b0 : o = 1'b1 ;<br />
5. 1'b1 : o = 1'b0 ;<br />
6. endcase<br />
7. endmodule<br />
</nowiki><br />
By default, the Verilog parser outputs:<br />
<nowiki><br />
-- Analyzing Verilog file 'test.v' (VERI-1482)<br />
test.v(3): ERROR: syntax error near 'priority' (VERI-1137)<br />
test.v(3): ERROR: SystemVerilog keyword priority used in incorrect context (VERI-2344)<br />
test.v(4): ERROR: syntax error near '=' (VERI-1137)<br />
test.v(5): ERROR: syntax error near '=' (VERI-1137)<br />
test.v(3): ERROR: 'c' is not a constant (VERI-1188)<br />
test.v(4): ERROR: 'o' is not a type (VERI-1281)<br />
test.v(5): ERROR: 'o' is not a type (VERI-1281)<br />
test.v(7): ERROR: module 'test' ignored due to previous errors (VERI-1072)<br />
ERROR: analyze: failed (CMD-1014)<br />
</nowiki><br />
<br />
With "verific_produce_verbose_syntax_error_message" enabled, you'll see:<br />
<nowiki><br />
-- Analyzing Verilog file 'test.v' (VERI-1482)<br />
test.v(3): INFO: unique priority case (c) (VERI-2124)<br />
test.v(3): INFO: ^ (VERI-2124)<br />
test.v(3): ERROR: syntax error near 'priority', expecting 'case' or 'casex' or 'casez' or 'if' (VERI-1137)<br />
test.v(3): ERROR: SystemVerilog keyword priority used in incorrect context (VERI-2344)<br />
test.v(4): INFO: 1'b0 : o = 1'b1 ; (VERI-2124)<br />
test.v(4): INFO: ^ (VERI-2124)<br />
test.v(4): ERROR: syntax error near '=' (VERI-1137)<br />
test.v(5): INFO: 1'b1 : o = 1'b0 ; (VERI-2124)<br />
test.v(5): INFO: ^ (VERI-2124)<br />
test.v(5): ERROR: syntax error near '=' (VERI-1137)<br />
test.v(3): ERROR: 'c' is not a constant (VERI-1188)<br />
test.v(4): ERROR: 'o' is not a type (VERI-1281)<br />
test.v(5): ERROR: 'o' is not a type (VERI-1281)<br />
test.v(7): ERROR: module 'test' ignored due to previous errors (VERI-1072)<br />
ERROR: analyze: failed (CMD-1014)<br />
</nowiki><br />
<br />
'''Other useful APIs'''<br />
<nowiki><br />
// Control if messages going to console:<br />
SetConsoleOutput(unsigned console_output)<br />
<br />
// Control if messages going to a logfile:<br />
OpenLogFile(const char *log_file)<br />
CloseLogFile()<br />
</nowiki></div>Vincehttps://www.verific.com/faq/index.php?title=Traverse_instances_in_parsetree&diff=709Traverse instances in parsetree2021-07-28T20:49:36Z<p>Vince: </p>
<hr />
<div>C++:<br />
<nowiki><br />
// Verific utilities<br />
#include "Array.h" // Make class Array available<br />
#include "Set.h" // Make class Set available<br />
#include "Message.h" // Make message handlers available<br />
#include "Strings.h" // Definition of class to manipulate, copy, concatenate, create etc...<br />
// Verific Verilog parser<br />
#include "VeriModule.h"<br />
#include "veri_file.h"<br />
<br />
// Verific VHDL parser<br />
#include "vhdl_file.h" <br />
#include "VhdlIdDef.h" <br />
#include "VhdlScope.h" <br />
#include "VhdlStatement.h" <br />
#include "VhdlName.h" // Definition of VhdlName<br />
#include "VhdlUnits.h" // Definition of VhdlLibrary<br />
<br />
#ifdef VERIFIC_NAMESPACE<br />
using namespace Verific ;<br />
#endif<br />
<br />
// Routines for traversing the entity instances in DFS order and print them.<br />
static void PrintDesignUnit(const VhdlStatement *stmt) ;<br />
static void TraverseVhdl(const VhdlPrimaryUnit *top, const char *arch_name) ;<br />
<br />
int main(int argc, const char **argv)<br />
{<br />
<br />
vhdl_file::SetDefaultLibraryPath("../vdbs") ;<br />
<br />
if (!veri_file::Analyze("test.v")) return 1 ;<br />
if (!vhdl_file::Analyze("test.vhd")) return 1 ;<br />
<br />
<br />
VhdlLibrary *lib = vhdl_file::GetLibrary("work") ;<br />
VhdlPrimaryUnit *top_entity = lib ? lib->GetPrimUnit("comp") : 0 ; // Get the top-level entity<br />
if (!top_entity) {<br />
return 1 ; <br />
}<br />
<br />
Message::PrintLine("\n") ;<br />
top_entity->Info("Start hierarchy traversal here at VHDL top level unit '%s'", top_entity->Name()) ;<br />
Message::PrintLine("\n") ;<br />
TraverseVhdl(top_entity, 0 /*architecture name*/) ; // Traverse top level unit and the hierarchy under it<br />
return 0 ; // all good<br />
}<br />
<br />
// Traverse an entity and the hierarchy under it:<br />
static void<br />
TraverseVhdl(const VhdlPrimaryUnit *unit, const char *arch_name)<br />
{<br />
// Find the architecture of the unit:<br />
VhdlSecondaryUnit *arch = unit? unit->GetSecondaryUnit(arch_name) : 0 ;<br />
// Find the scope:<br />
VhdlScope *scope = arch ? arch->LocalScope() : 0 ;<br />
<br />
// Get the declared ids from that scope:<br />
Map *ids = scope ? scope->DeclArea() : 0 ;<br />
MapIter mi ;<br />
VhdlIdDef *id ;<br />
FOREACH_MAP_ITEM(ids, mi, 0, &id) {<br />
if (!id) continue ;<br />
VhdlStatement *stmt = id->GetStatement() ;<br />
if (!stmt) continue ;<br />
// Routine to print the hierarchy:<br />
PrintDesignUnit(stmt) ;<br />
}<br />
}<br />
<br />
// Print the hierarchy<br />
static void PrintDesignUnit(const VhdlStatement *stmt)<br />
{<br />
if (!stmt) return ;<br />
<br />
// Get the array of statements, for loop/block statements<br />
// we get an array of statements and recursively go to the<br />
// inner most statement and print the hierarchy.<br />
Array *stmts = stmt->GetStatements() ;<br />
unsigned ai ;<br />
VhdlStatement *inner_stmt ;<br />
FOREACH_ARRAY_ITEM(stmts, ai, inner_stmt) {<br />
PrintDesignUnit(inner_stmt) ;<br />
}<br />
<br />
VhdlIdDef *inst_unit = stmt->GetInstantiatedUnit() ; // Get the instantiated unit id for instances only<br />
if (!inst_unit) return ; // Not an instance level<br />
<br />
// Processing instance<br />
VhdlIdDef *id = stmt->GetLabel() ;<br />
Message::PrintLine("Processing instance : ", id ? id->Name() : 0) ;<br />
<br />
if (inst_unit->IsComponent()) { // instance of component<br />
Message::PrintLine("Component instance, name of component is ", inst_unit->Name()) ;<br />
Message::PrintLine("\n") ;<br />
}<br />
<br />
VhdlPrimaryUnit *prim_unit = inst_unit ? inst_unit->GetPrimaryUnit() : 0 ; // Get the primary unit<br />
if (!prim_unit) return ;<br />
<br />
if (prim_unit->IsVerilogModule()) { // instance of Verilog module<br />
// Get instantiated verilog module<br />
VeriModule *veri_module = vhdl_file::GetVerilogModuleFromlib(inst_unit->GetContainingLibraryName(), inst_unit->Name()) ;<br />
if (!veri_module) return ;<br />
Message::PrintLine("instantiated Verilog module : ", veri_module->Name()) ;<br />
Message::PrintLine("\n") ;<br />
} else { // Instance of vhdl unit<br />
VhdlName *instantiated_unit_name = stmt->GetInstantiatedUnitNameNode() ;<br />
// Find the architecture name and traverse the vhdl design<br />
const char *arch_name = instantiated_unit_name ? instantiated_unit_name->ArchitectureNameAspect(): 0 ; <br />
Message::PrintLine("instantiated VHDL unit : ", prim_unit->Name()) ;<br />
Message::PrintLine("architecture name : ", arch_name ? arch_name : 0) ;<br />
Message::PrintLine("\n") ;<br />
TraverseVhdl(prim_unit, arch_name) ; // Traverse the VHDL unit<br />
}<br />
}<br />
</nowiki><br />
<br />
test.vhd:<br />
<nowiki><br />
entity child is -- instantiated in test module in Verilog design<br />
generic (p : integer := 3);<br />
port (S1, S2: out bit_vector (p downto 0);<br />
I1 : in bit_vector (p downto 0));<br />
end ;<br />
<br />
architecture arch of child is<br />
begin<br />
S1 <= I1 ;<br />
S2 <= not I1 ;<br />
end ;<br />
<br />
entity comp is -- top-level unit<br />
<br />
port(X, Y: in BIT_VECTOR(3 DOWNTO 0);<br />
S1, S2: out bit_vector (3 DOWNTO 0);<br />
S3, S4: out bit_vector (3 DOWNTO 0);<br />
Sum, Carry: out BIT);<br />
<br />
end;<br />
<br />
architecture Structure of comp is<br />
<br />
component child is<br />
generic (p : integer) ;<br />
port (S1, S2: out BIT_VECTOR(3 DOWNTO 0);<br />
I1 : in BIT_VECTOR(3 downto 0));<br />
end component;<br />
<br />
begin<br />
<br />
L1: entity work.xor_gate generic map (4)<br />
port map (X, Y, Sum);<br />
<br />
L2 : component child generic map (4) port map(S1, S2, X) ;<br />
blk : block<br />
begin<br />
L3 : entity work.child(arch) generic map (4) port map(S3, S4, X) ;<br />
end block ;<br />
<br />
end;<br />
</nowiki><br />
<br />
test.v:<br />
<nowiki><br />
module xor_gate (CompIn1, CompIn2, CompOut); // Instantiated in 'comp' entity in VHDL file test.vhd<br />
parameter p = 10 ;<br />
input [3:0]CompIn1;<br />
input [3:0]CompIn2;<br />
output CompOut;<br />
endmodule<br />
</nowiki><br />
<br />
Run:<br />
<nowiki><br />
[hoa@awing0 HD]$ test-linux <br />
INFO: The default vhdl library search path is now "/mnt/awing0_customers/Verific/extra_tests/vdbs" (VHDL-1504)<br />
-- Analyzing Verilog file 'test.v' (VERI-1482)<br />
-- Analyzing VHDL file 'test.vhd' (VHDL-1481)<br />
-- Restoring VHDL parse-tree 'std.standard' from '/mnt/awing0_customers/Verific/extra_tests/vdbs/std/standard.vdb' (VHDL-1493)<br />
test.vhd(1): INFO: analyzing entity 'child' (VHDL-1012)<br />
test.vhd(7): INFO: analyzing architecture 'arch' (VHDL-1010)<br />
test.vhd(13): INFO: analyzing entity 'comp' (VHDL-1012)<br />
test.vhd(22): INFO: analyzing architecture 'structure' (VHDL-1010)<br />
-- Restoring VHDL parse-tree 'vl.vl_types' from '/mnt/awing0_customers/Verific/extra_tests/vdbs/vl/vl_types.vdb' (VHDL-1493)<br />
-- <br />
<br />
test.vhd(20): INFO: Start hierarchy traversal here at VHDL top level unit 'comp'<br />
-- <br />
<br />
-- Processing instance : l1<br />
-- instantiated Verilog module : xor_gate<br />
-- <br />
<br />
-- Processing instance : l2<br />
-- Component instance, name of component is child<br />
-- <br />
<br />
-- Processing instance : l3<br />
-- instantiated VHDL unit : child<br />
-- architecture name : arch<br />
-- <br />
<br />
[hoa@awing0 HD]$ <br />
</nowiki></div>Vincehttps://www.verific.com/faq/index.php?title=Tcl_library_path&diff=679Tcl library path2021-04-27T17:46:42Z<p>Vince: </p>
<hr />
<div>'''Q: When trying to build, I get the error message: "/usr/bin/ld: cannot find -ltcl". How do I correct that problem?'''<br />
<br />
First, verify that you have tcl and tcl dev installed on your system. Have them installed if they are not.<br />
<br />
For Ubuntu-like systems:<br />
apt-get install tcl-dev<br />
For Centos/Fedora-like systems:<br />
yum/dnf install tcl-devel<br />
<br />
The "Makefile" provided by Verific has "-ltcl" option. The linker will look for the file /usr/lib/libtcl.so (for 32-bit build) or /usr/lib64/libtcl.so (for 64-bit build).<br />
<br />
You can either:<br />
<br />
1. In /usr/lib (or in /usr/lib64 for 64-bit build), make soft link libtcl.so pointing to your_lib_tcl.so and (for static build) libtcl.a to your_lib_tcl_.a. For example:<br />
<br />
[lib64]$ pwd<br />
/usr/lib64<br />
[lib64]$ ls -l *tcl*<br />
-rw-r----- 1 root root 2107226 Nov 29 2016 libtcl8.5.a<br />
-rwxr-xr-x 1 root root 1194938 Nov 29 2016 libtcl8.5.so<br />
lrwxrwxrwx 1 root root 11 Nov 29 2016 libtcl.a -> libtcl8.5.a<br />
lrwxrwxrwx 1 root root 12 Nov 29 2016 libtcl.so -> libtcl8.5.so<br />
[lib64]$<br />
<br />
or:<br />
<br />
2. In the Makefile, replace "-ltcl" with "-L /path/to/your/tcl/library -ltclX.y" where X is the major version and y is the minor. Depending on your PATH variable you may also need to replace the #include <tcl.h> in commands/*.cpp, tclmain/TclMain.cpp (and tclmain/swig.i if it exists) with #include "/path/to/your/tcl/headers/tcl.h"</div>Vince