View source for Notes on analysis

First, please read this article: [[Defined macros become undefined - MFCU vs SFCU]].

'''Q: Can I use 'veri_file::Analyze()' to read SystemVerilog input files one by one, all of them belonging to one compilation unit?'''
 
Yes. But if you have multiple files, it’s better to use 'veri_file::AnalyzeMultipleFiles()'.
 
'veri_file::AnalyzeMultipleFiles()', besides analyzing each file, also:
 
* opens and ends the compilation unit
* processes –v and –y options
* removes include directories
* processes root module
* undefines user-defined macros, including command-line macros
* resets compile directives (e.g. `default_nettype, `timescale)
 
If you use 'veri_file::Analyze()' to analyze each file one by one, after all the calls to 'veri_file::Analyze()'. you’ll need to call 'veri_file::AnalyzeFull()' to complete the analysis before starting any other operation.

The TCL command 'analyze' uses the API 'veri_file::AnalyzeMultipleFiles()'. In other words, it assumes a complete compilation unit for each execution.