How to evaluate a Verilog expression - Revision history

Mohammad at 04:53, 19 November 2025

2025-11-19T04:53:50Z

2025-11-18T20:08:36Z

2025-11-18T20:05:57Z

2025-09-03T21:44:48Z

2025-09-03T21:39:56Z

2025-09-03T21:38:35Z

2025-09-03T19:18:49Z

2025-09-03T19:17:54Z

2025-09-03T19:15:31Z

2025-09-03T18:46:12Z

@@ Line 12: / Line 12: @@
 #include "VeriModule.h"
 #include "VeriBaseValue_Stat.h"
 #include "Strings.h"
@@ Line 45: / Line 46: @@
      ValueTable df ;
      MapIter mi ;
@@ Line 59: / Line 62: @@
          VeriExpression *expr = veri_file::AnalyzeExpr(val_str, veri_file::SYSTEM_VERILOG) ;
          if (!expr) return 4 ;
          // Evaluate the expression:
@@ Line 82: / Line 92: @@
      VeriBaseValue *val = expr->StaticEvaluate(0 /* self context */, &df /* use this table with the known values */) ;
      delete expr ;
      if (!val) return 8 ; // Failed to evaluate
@@ Line 92: / Line 108: @@
      return 0 ;
+}
   </nowiki>

@@ Line 2: / Line 2: @@
-== Evaluate an expression not in the design ==
+== Static evaluate an expression not in the design ==
 In the example below, a, b, and c are declared in the Verilog module. There is no need to run static elaboration on the whole module. But 'Static Elaboration' feature is still required because the API VeriExpression::StaticEvaluate() is available only with 'Static Elaboration' feature.
@@ Line 115: / Line 115: @@
-== A function call in the design and generate variables (genvar)==
+== Static evaluate a function call in the design and generate variables (genvar)==
 Function calls are similar to other expressions, and you can evaluate them using StaticEvaluate().
@@ Line 278: / Line 278: @@
   </nowiki>
-== An expression that crosses module boundaries ==
+== Static evaluate an expression that crosses module boundaries ==
 If an element in the expression to be evaluated crosses module boundaries, elaboration needs to be run as in the Verilog testcase below ('my_int' is to be evaluated):

@@ Line 110: / Line 110: @@
   </nowiki>
-If an element in the expression crosses module boundaries, elaboration needs to be run as in the example below:
+If an element in the expression to be evaluated crosses module boundaries, elaboration needs to be run as in the Verilog testcase below ('my_int' is to be evaluated):
-−
 Verilog testcase:
   <nowiki>
@@ Line 121: / Line 119: @@
 module test();
      ifc #(.N(13)) I();
-     int my_int = $bits(I.data);
+     int my_int = $bits(I.data); // want to evaluated 'my_int' or '$bits(I.data)'
 endmodule
   </nowiki>
@@ Line 189: / Line 187: @@
 Reference: https://www.verific.com/docs/index.php?title=Hierarchy_Tree
-The C++ example below uses hierarchy-tree elaboration:
+The C++ example below uses hierarchy-tree elaboration instead of static elaboration:
 C++:

@@ Line 125: / Line 125: @@
   </nowiki>
-C++:
+The C++ example below calls static elaboration:
   <nowiki>
 #include "veri_file.h"

@@ Line 107: / Line 107: @@
 -- Analyzing Verilog file 'test.v' (VERI-1482)
 test.v(5): INFO: Evaluated value: 2'b10 (2)
+$
   </nowiki>

@@ Line 1: / Line 1: @@
 Evaluating a Verilog expression requires 'Static Elaboration' or 'Hierarchy Tree' feature.
-In the example below, a, b, and c are declared in the Verilog module. But 'Static Elaboration' feature is still required because the API VeriExpression::StaticEvaluate() is available only with 'Static Elaboration' feature.
+In the example below, a, b, and c are declared in the Verilog module. There is no need to run static elaboration on the whole module. But 'Static Elaboration' feature is still required because the API VeriExpression::StaticEvaluate() is available only with 'Static Elaboration' feature.
 C++:

← Older revision		Revision as of 19:17, 3 September 2025
Line 1:		Line 1:
−	Evaluating a Verilog expression ~~Verific~~ 'Static Elaboration' or 'Hierarchy Tree' feature.	+	Evaluating a Verilog expression requires 'Static Elaboration' or 'Hierarchy Tree' feature.

	In the example below, a, b, and c are declared in the Verilog module. But 'Static Elaboration' feature is still required because the API VeriExpression::StaticEvaluate() is available only with 'Static Elaboration' feature.		In the example below, a, b, and c are declared in the Verilog module. But 'Static Elaboration' feature is still required because the API VeriExpression::StaticEvaluate() is available only with 'Static Elaboration' feature.

@@ Line 1: / Line 1: @@
-This application example shows how to evaluate a Verilog expression. It requires Verific 'Static Elaboration' feature (the API VeriExpression::StaticEvaluate() available only with Verilog Static Elaboration feature).
+Evaluating a Verilog expression Verific 'Static Elaboration' or 'Hierarchy Tree' feature.
-Note that a, b, and c are declared in the Verilog module. The application evaluates an expression of these variables.
+In the example below, a, b, and c are declared in the Verilog module. But 'Static Elaboration' feature is still required because the API VeriExpression::StaticEvaluate() is available only with 'Static Elaboration' feature.
 C++:

← Older revision		Revision as of 18:46, 3 September 2025
Line 1:		Line 1:
−	This application example shows how to evaluate a Verilog expression. It requires Verific 'Static Elaboration' feature.	+	This application example shows how to evaluate a Verilog expression. It requires Verific 'Static Elaboration' feature (the API VeriExpression::StaticEvaluate() available only with Verilog Static Elaboration feature).

	Note that a, b, and c are declared in the Verilog module. The application evaluates an expression of these variables.		Note that a, b, and c are declared in the Verilog module. The application evaluates an expression of these variables.