How to get packed dimensions of enum - Revision history

Vince at 00:46, 12 May 2022

2022-05-12T00:46:26Z

Hoa at 18:39, 9 August 2021

2021-08-09T18:39:29Z

Hoa at 18:39, 9 August 2021

2021-08-09T18:39:00Z

Hoa at 23:21, 4 July 2019

2019-07-04T23:21:35Z

Hoa: Created page with "C++: #include "Map.h" // Make associated hash table class Map available #include "Set.h" // Make associated hash table class Set available #include "..."

2019-07-04T23:20:24Z

Created page with "C++: <nowiki> #include "Map.h" // Make associated hash table class Map available #include "Set.h" // Make associated hash table class Set available #include "..."

New page

C++:
<nowiki>
#include "Map.h" // Make associated hash table class Map available
#include "Set.h" // Make associated hash table class Set available
#include "Message.h" // Make message handlers available
#include "veri_file.h" // Make verilog reader available
#include "VeriModule.h"
#include "VeriScope.h"
#include "VeriId.h"
#include "VeriExpression.h"
#include "veri_file.h"
#include <iostream>
#include <string>
#include <string.h>
#include <sstream>
#include <stdio.h>
#include <set>
#include <vector>
#include <map>

using namespace std;
#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

void GetBaseTypeFromDataType(VeriDataType *);

int main(int argc, char **argv)
{
veri_file::SetInterfaceModportFieldSeparator("::") ;

Array file_names;

if (argc < 2) {
file_names.InsertLast("test.v");
} else {
for (int i = 1; i < argc; i++) {
file_names.InsertLast(argv[i]);
}
}

Array * file_names_ = new Array( file_names);

if (!veri_file::AnalyzeMultipleFiles(file_names_, veri_file::SYSTEM_VERILOG, "work", veri_file::MFCU)) {
std::cout << " Unable to analyze multiple files. Aborting\n";
return 1 ;
}

// Fetching the top module
Array *top_module_array = veri_file::GetTopModules() ;

if (!top_module_array) {
Message::Error(0, "Cannot find any top module in the design") ;
return 4;
}

VeriModule *module = (VeriModule *) top_module_array->GetFirst();

// Creating VPT
module->StaticElaborate( 0);
module->Elaborate( 0, 0, false);

VeriScope* p_scope = module->GetScope();
Map* scope_map = p_scope->GetThisScope();
MapIter mi ;
VeriIdDef *id;

FOREACH_MAP_ITEM(scope_map, mi, 0, &id) {
if (!id ) continue;
std::cout << "Handling Declaration: "<< id->Name() << std::endl;
GetBaseTypeFromDataType(id->GetDataType());
}
// module->PrettyPrint(std::cout, 1) ;

return 0;
}

void GetBaseTypeFromDataType(VeriDataType *p_data_type)
{
if(!p_data_type) {
return;
}
unsigned packed_dim = p_data_type->PackedDimension();
switch( p_data_type->GetClassId() ) {
case ID_VERIDATATYPE: {
std::cout << "===== ID_VERIDATATYPE:: p_data_type->Image() = " << p_data_type->Image() << " =====" << std::endl;
std::cout << "===== ID_VERIDATATYPE:: packed_dim = " << packed_dim << std::endl;
if ( packed_dim != 0 ) {
VeriRange const* range = dynamic_cast<VeriRange const*>
(p_data_type->GetDimensions());
VeriRange const* last_dim_range = NULL;
do {
last_dim_range = range;
} while ( range && (range = range->GetNext()) );
if ( last_dim_range && last_dim_range->GetLeft() && last_dim_range->GetRight() ) {
std::cout << "packed_dim->Left = " << last_dim_range->GetLeft()->Image() << std::endl;
std::cout << "packed_dim->Right = " << last_dim_range->GetRight()->Image() << std::endl;
}
}
break;
}
case ID_VERINETDATATYPE:
case ID_VERISTRUCTUNION:
case ID_VERIENUM : {
std::cout << "===== ID_VERIENUM:: p_data_type->Image() = " << p_data_type->Image() << " =====" << std::endl;
std::cout << "===== ID_VERIENUM:: packed_dim = " << packed_dim << std::endl;
if ( packed_dim != 0 ) {
VeriRange const* range = dynamic_cast<VeriRange const*>
(p_data_type->GetDimensions());
VeriRange const* last_dim_range = NULL;
do {
last_dim_range = range;
} while ( range && (range = range->GetNext()) );

if ( last_dim_range && last_dim_range->GetLeft() && last_dim_range->GetRight() ) {
std::cout << "packed_dim->Left = " << last_dim_range->GetLeft()->Image() << std::endl;
std::cout << "packed_dim->Right = " << last_dim_range->GetRight()->Image() << std::endl;
}
}
VeriEnum* p_enum = dynamic_cast<VeriEnum*>(p_data_type);
VeriDataType* p_base_type = p_enum->GetBaseType();
GetBaseTypeFromDataType (p_base_type);
break;
}
case ID_VERITYPEREF: {
std::cout << "===== ID_VERITYPEREF:: p_data_type->Image() = " << p_data_type->Image() << " =====" << std::endl;
std::cout << "===== ID_VERITYPEREF:: packed_dim = " << packed_dim << std::endl;
GetBaseTypeFromDataType(p_data_type->GetBaseDataType());
break;
}
default:
break;
}
}
</nowiki>

Input Verilog:
<nowiki>
typedef enum bit { a, b } [1:0] data_ctrl_t;

module test(
output data_ctrl_t out1 );

assign out1 = b ;

endmodule
</nowiki>

Run:
<nowiki>
-- Analyzing Verilog file 'test.v' (VERI-1482)
test.v(3): INFO: compiling module 'test' (VERI-1018)
test.v(3): INFO: compiling module 'test' (VERI-1018)
Handling Declaration: out1
===== ID_VERITYPEREF:: p_data_type->Image() = data_ctrl_t =====
===== ID_VERITYPEREF:: packed_dim = 1
===== ID_VERIENUM:: p_data_type->Image() = enum(a,b) =====
===== ID_VERIENUM:: packed_dim = 1
packed_dim->Left = 1
packed_dim->Right = 0
===== ID_VERIDATATYPE:: p_data_type->Image() = bit =====
===== ID_VERIDATATYPE:: packed_dim = 0
</nowiki>

@@ Line 87: / Line 87: @@
                  } while ( range && (range = range->GetNext()) );
                      if ( last_dim_range &&  last_dim_range->GetLeft() && last_dim_range->GetRight() ) {
-                         std::cout << "packed_dim->Left = " << last_dim_range->GetLeft()->Image() << std::endl;
+                         std::cout << "packed_dim->Left = " << last_dim_range->GetLeft()->GetPrettyPrintedString() << std::endl;
-                         std::cout << "packed_dim->Right = " << last_dim_range->GetRight()->Image() << std::endl;
+                         std::cout << "packed_dim->Right = " << last_dim_range->GetRight()->GetPrettyPrintedString() << std::endl;
+                     }
+                 }
@@ Line 119: / Line 119: @@
                  if ( last_dim_range &&  last_dim_range->GetLeft() && last_dim_range->GetRight() ) {
-                     std::cout << "packed_dim->Left = " << last_dim_range->GetLeft()->Image() << std::endl;
+                     std::cout << "packed_dim->Left = " << last_dim_range->GetLeft()->GetPrettyPrintedString() << std::endl;
-                     std::cout << "packed_dim->Right = " << last_dim_range->GetRight()->Image() << std::endl;
+                     std::cout << "packed_dim->Right = " << last_dim_range->GetRight()->GetPrettyPrintedString() << std::endl;
+                 }
+             }

@@ Line 68: / Line 68: @@
      return 0;
+}
 void GetBaseTypeFromDataType(VeriDataType *p_data_type)

@@ Line 1: / Line 1: @@
 C++:
   <nowiki>
-#include "Map.h"         // Make associated hash table class Map available
+#include "Array.h"
-#include "Set.h"         // Make associated hash table class Set available
+#include "Map.h"
-#include "Message.h"     // Make message handlers available
+#include "Set.h"
-#include "veri_file.h"   // Make verilog reader available
+#include "Message.h"
 #include "VeriModule.h"
 #include "VeriScope.h"
@@ Line 11: / Line 12: @@
 #include "veri_file.h"
 #include <iostream>
 using namespace std;
@@ Line 71: / Line 65: @@
          GetBaseTypeFromDataType(id->GetDataType());
+     }
      return 0;
@@ Line 102: / Line 95: @@
+             }
          case ID_VERINETDATATYPE:
-         case ID_VERISTRUCTUNION:
+            break;
          case ID_VERIENUM : {
              std::cout << "===== ID_VERIENUM:: p_data_type->Image() = " << p_data_type->Image() << " =====" << std::endl;
@@ Line 141: / Line 146: @@
 module test (output data_ctrl_t out1 );
-     assign out1 = b ;
+  struct packed {
 endmodule
   </nowiki>
@@ Line 159: / Line 168: @@
 ===== ID_VERIDATATYPE:: p_data_type->Image() = bit =====
 ===== ID_VERIDATATYPE:: packed_dim = 0
   </nowiki>