How to parse a string - Revision history

Hoa at 17:10, 18 June 2024

2024-06-18T17:10:19Z

Hoa at 04:09, 27 January 2022

2022-01-27T04:09:35Z

Hoa at 04:08, 27 January 2022

2022-01-27T04:08:56Z

Hoa at 23:12, 20 October 2021

2021-10-20T23:12:00Z

Hoa at 20:02, 17 June 2021

2021-06-17T20:02:27Z

Hoa at 19:45, 17 June 2021

2021-06-17T19:45:17Z

Hoa at 19:44, 17 June 2021

2021-06-17T19:44:22Z

Vince at 01:33, 1 December 2020

2020-12-01T01:33:34Z

Vince at 23:37, 20 July 2020

2020-07-20T23:37:04Z

Hoa: Created page with "Let's say you want to add a node to the parsetree. One of the simple ways to do so is to start with a text string; then "parse" that string to get a VHDL or Verilog construct..."

2020-07-20T21:49:01Z

Created page with "Let's say you want to add a node to the parsetree. One of the simple ways to do so is to start with a text string; then "parse" that string to get a VHDL or Verilog construct..."

New page

Let's say you want to add a node to the parsetree.

One of the simple ways to do so is to start with a text string; then "parse" that string to get a VHDL or Verilog construct. The construct then can be added to the parsetree.

Below are the APIs to parse a string:

'''Verilog:'''
* VeriExpression *veri_file::AnalyzeExpr(const char *expr, unsigned verilog_mode=VERILOG_2K, const linefile_type line_file = 0)
* VeriModuleItem *veri_file::AnalyzeModuleItem(const char *module_item, unsigned verilog_mode=VERILOG_2K, const linefile_type line_file = 0, VeriScope *container_scope = 0)
* VeriStatement *veri_file::AnalyzeStatement(const char *statement, unsigned verilog_mode=VERILOG_2K, const linefile_type line_file = 0, VeriScope *container_scope = 0)
Appropriate scope information where the given string is valid should be passed to the APIs to have them work properly.
Need to call Resolve() on the returned parse tree nodes with proper scope where these items will be used.
VeriTreeNode::VERI_UPWARD_SCOPE_NAME can be passed as the resolve environment.
If required, they can be added to the existing parse tree using the appropriate APIs.

'''VHDL:'''
* VhdlExpression *vhdl_file::AnalyzeExpr(const char *expr, unsigned vhdl_mode=VHDL_93, const linefile_type line_file=0)
* VhdlStatement *vhdl_file::AnalyzeSequentialStatement(const char *statement, unsigned vhdl_mode = VHDL_93, const char *lib_name = "work", const linefile_type line_file = 0, * VhdlScope *container_scope = 0)
* VhdlStatement *vhdl_file::AnalyzeConcurrentStatement(const char *statement, unsigned vhdl_mode = VHDL_93, const char *lib_name = "work", const linefile_type line_file = 0, VhdlScope *container_scope = 0)
* VhdlDesignUnit *vhdl_file::AnalyzeUnit(const char *unit, unsigned vhdl_mode = VHDL_93, const char *lib_name = "work", const linefile_type line_file = 0)
Appropriate scope information where the given string is valid should be passed to the APIs to have them work properly.
We need vhdl_file::AnalyzeSequentialStatement() as well as vhdl_file::AnalyzeConcurrentStatement() to differentiate the starting point between the two.
Verilog AnalyzeModuleItem() = VHDL AnalyzeConcurrentStatement() and AnalyzeUnit() both
Verilog AnalyzeStatement() = VHDL AnalyzeSequentialStatement()

Off-course full designs can be analyzed from strings. Please use streams for that.
See [https://www.verific.com/docs/index.php?title=Analyzing_Stream_Inputs Analyzing Stream Inputs]

@@ Line 47: / Line 47: @@
 #include "VeriScope.h"
 #include "VeriLibrary.h"
 #include "Array.h"
@@ Line 58: / Line 60: @@
      // Analyze the file:
      Array files(1) ;
-     files.InsertLast("test.sv") ;
+     files.InsertLast("test.v") ;
      if (!veri_file::AnalyzeMultipleFiles(&files, veri_file::SYSTEM_VERILOG, "work")) return 1 ;
      // Get the 'top' module:
-     VeriModule *top = veri_file::GetModule("top") ;
+     VeriModule *top = veri_file::GetModule("test") ;
      if (!top) return 2 ;
      // Get the library of the 'top' module:
@@ Line 77: / Line 76: @@
      // Analyze a new module under the scope of the compilation unit:
-     VeriModuleItem *mi = veri_file::AnalyzeModuleItem("module test_A;\n    A tests[1];\nendmodule", veri_file::SYSTEM_VERILOG, 0UL, scope) ;
+    linefile_type dummy_lf = LineFile::EncodeLineFile("read-from-string", 1) ;
      if (!mi) return 5 ;
@@ Line 89: / Line 89: @@
      if (!mod) return 7 ;
-     // Add the module to the same library as the 'top' module:
+     // Add to user defined library:
-     if (!work_lib->AddModule(mod)) return 8 ;
+    VeriLibrary *user_define_lib = veri_file::GetLibrary("new_lib", 1 /* create if needed */) ;
-     // Finally, elaborate the new module:
+     Netlist *top_nl = Netlist::PresentDesign() ;
-     if (!veri_file::ElaborateStatic(mod->Name())) return 9 ;
+     if (!top_nl) return 10 ;
-     veri_file::PrettyPrint("test_se.v.golden.new", 0) ;
+     VeriWrite vw ;
      return 0 ;
+}
   </nowiki>

@@ Line 30: / Line 30: @@
      VeriScope *current_scope = module->GetScope() ;
      if (expr) {
-         expr->Resolve(current_scope, VeriTreeNode:: VERI_UNDEF_ENV);
+         expr->Resolve(current_scope, VeriTreeNode::VERI_UNDEF_ENV);
          // plus anything else user may want to add
+     }

@@ Line 12: / Line 12: @@
 :- appropriate scope information where the given string is valid should be passed to the APIs for them to work properly
 :- need to call Resolve() on the returned parse tree nodes with proper scope where these items will be used
-:- VeriTreeNode::VERI_UPWARD_SCOPE_NAME can be passed as the Resolve() environment
+:- VeriTreeNode::VERI_UNDEF_ENV can be passed as the Resolve() environment
 :- if required the nodes can be added to the existing parse tree using the appropriate APIs
@@ Line 30: / Line 30: @@
      VeriScope *current_scope = module->GetScope() ;
      if (expr) {
-         expr->Resolve(current_scope, VeriTreeNode::VERI_UPWARD_SCOPE_NAME);
+         expr->Resolve(current_scope, VeriTreeNode:: VERI_UNDEF_ENV);
          // plus anything else user may want to add
+     }

@@ Line 30: / Line 30: @@
      VeriScope *current_scope = module->GetScope() ;
      if (expr) {
-         myexp->Resolve(current_scope, VeriTreeNode::VERI_UPWARD_SCOPE_NAME);
+         expr->Resolve(current_scope, VeriTreeNode::VERI_UPWARD_SCOPE_NAME);
          // plus anything else user may want to add
+     }

@@ Line 37: / Line 37: @@
 See [https://www.verific.com/docs/index.php?title=Analyzing_Stream_Inputs Analyzing Stream Inputs]
-Below is an example using of string parsing (veri_file::AnalyzeModuleItem()) to add a module to the parsetree.
+Below is a C++ code example of using string parsing (veri_file::AnalyzeModuleItem()) to add a module to the parsetree.
   <nowiki>

← Older revision		Revision as of 19:44, 17 June 2021
Line 36:		Line 36:
	Full designs can be analyzed from strings as well. Please use streams for that.		Full designs can be analyzed from strings as well. Please use streams for that.
	See [https://www.verific.com/docs/index.php?title=Analyzing_Stream_Inputs Analyzing Stream Inputs]		See [https://www.verific.com/docs/index.php?title=Analyzing_Stream_Inputs Analyzing Stream Inputs]
		+
		+	Below is an example using string parsing (veri_file::AnalyzeModuleItem()) to add a module to the parsetree.
		+
		+	<nowiki>
		+	#include <iostream>
		+
		+	#include "veri_file.h"
		+	#include "VeriModule.h"
		+	#include "VeriId.h"
		+	#include "VeriScope.h"
		+	#include "VeriLibrary.h"
		+
		+	#include "Array.h"
		+
		+	#ifdef VERIFIC_NAMESPACE
		+	using namespace Verific ;
		+	#endif
		+
		+	int main(void)
		+	{
		+	// Analyze the file:
		+	Array files(1) ;
		+	files.InsertLast("test.sv") ;
		+	if (!veri_file::AnalyzeMultipleFiles(&files, veri_file::SYSTEM_VERILOG, "work")) return 1 ;
		+
		+	// Get the 'top' module:
		+	VeriModule *top = veri_file::GetModule("top") ;
		+	if (!top) return 2 ;
		+
		+	// Elaborate the 'top' module:
		+	if (!veri_file::ElaborateStatic(top->Name())) return 3 ;
		+
		+	// Get the library of the 'top' module:
		+	VeriLibrary *work_lib = top->GetLibrary() ;
		+	if (!work_lib) return 4 ;
		+
		+	// Get the compilation unit of the 'top' module and then the compilation unit scope where the class is declared:
		+	VeriModule *root = top->GetCompilationUnit() ;
		+	VeriScope *scope = (root) ? root->GetScope() : 0 ;
		+
		+	// Analyze a new module under the scope of the compilation unit:
		+	VeriModuleItem *mi = veri_file::AnalyzeModuleItem("module test_A;\n A tests[1];\nendmodule", veri_file::SYSTEM_VERILOG, 0UL, scope) ;
		+	if (!mi) return 5 ;
		+
		+	// Get the identifier of the module item:
		+	VeriIdDef *id = mi->GetId() ;
		+	if (!id) return 6 ;
		+
		+	// Get the VeriModule * from the identifier of the module:
		+	// This will return NULL if it is not actually a module.
		+	VeriModule *mod = id->GetModule() ;
		+	if (!mod) return 7 ;
		+
		+	// Add the module to the same library as the 'top' module:
		+	if (!work_lib->AddModule(mod)) return 8 ;
		+
		+	// Finally, elaborate the new module:
		+	if (!veri_file::ElaborateStatic(mod->Name())) return 9 ;
		+
		+	veri_file::PrettyPrint("test_se.v.golden.new", 0) ;
		+
		+	return 0 ;
		+	}
		+	</nowiki>

@@ Line 1: / Line 1: @@
 Let's say you want to add a node to the parse tree.
-One simple way to do so is to start with a text string, then "parse" that string to get a VHDL or Verilog construct. The construct then can be added to the parse tree.
+One simple way to do so is to start with a text string, then "parse" that string to get a VHDL or Verilog construct. The construct can then be added to the parse tree.
 Below are the APIs to parse a string:

@@ Line 1: / Line 1: @@
-Let's say you want to add a node to the parsetree.
+Let's say you want to add a node to the parse tree.
-One of the simple ways to do so is to start with a text string; then "parse" that string to get a VHDL or Verilog construct. The construct then can be added to the parsetree.
+One simple way to do so is to start with a text string, then "parse" that string to get a VHDL or Verilog construct. The construct then can be added to the parse tree.
 Below are the APIs to parse a string:
@@ Line 9: / Line 9: @@
 * VeriModuleItem *veri_file::AnalyzeModuleItem(const char *module_item, unsigned verilog_mode=VERILOG_2K, const linefile_type line_file = 0, VeriScope *container_scope = 0)
 * VeriStatement *veri_file::AnalyzeStatement(const char *statement, unsigned verilog_mode=VERILOG_2K, const linefile_type line_file = 0, VeriScope *container_scope = 0)
-Appropriate scope information where the given string is valid should be passed to the APIs to have them work properly.
+Notes for Verilog :
-Need to call Resolve() on the returned parse tree nodes with proper scope where these items will be used.
+:- appropriate scope information where the given string is valid should be passed to the APIs for them to work properly
-VeriTreeNode::VERI_UPWARD_SCOPE_NAME can be passed as the resolve environment.
+:- need to call Resolve() on the returned parse tree nodes with proper scope where these items will be used
-If required, they can be added to the existing parse tree using the appropriate APIs.
+:- VeriTreeNode::VERI_UPWARD_SCOPE_NAME can be passed as the Resolve() environment
 '''VHDL:'''
@@ Line 19: / Line 20: @@
 * VhdlStatement *vhdl_file::AnalyzeConcurrentStatement(const char *statement, unsigned vhdl_mode = VHDL_93, const char *lib_name = "work", const linefile_type line_file = 0, VhdlScope *container_scope = 0)
 * VhdlDesignUnit *vhdl_file::AnalyzeUnit(const char *unit, unsigned vhdl_mode = VHDL_93, const char *lib_name = "work", const linefile_type line_file = 0)
-Appropriate scope information where the given string is valid should be passed to the APIs to have them work properly.
+Notes for VHDL :
-We need vhdl_file::AnalyzeSequentialStatement() as well as vhdl_file::AnalyzeConcurrentStatement() to differentiate the starting point between the two.
+:- appropriate scope information where the given string is valid should be passed to the APIs for them to work properly
-Verilog AnalyzeModuleItem() = VHDL AnalyzeConcurrentStatement() and AnalyzeUnit() both
+:- need vhdl_file::AnalyzeSequentialStatement() as well as vhdl_file::AnalyzeConcurrentStatement() to differentiate between the starting points of the two
-Verilog AnalyzeStatement() = VHDL AnalyzeSequentialStatement()
+:- Verilog AnalyzeModuleItem() = both VHDL AnalyzeConcurrentStatement() and VHDL AnalyzeUnit()
-Off-course full designs can be analyzed from strings. Please use streams for that.
+Full designs can be analyzed from strings as well. Please use streams for that.
 See [https://www.verific.com/docs/index.php?title=Analyzing_Stream_Inputs Analyzing Stream Inputs]