How to save computer resources - Revision history

Hoa at 17:54, 12 January 2026

2026-01-12T17:54:21Z

Vince at 17:40, 10 October 2025

2025-10-10T17:40:54Z

Vince at 17:36, 10 October 2025

2025-10-10T17:36:45Z

Vince at 16:51, 10 October 2025

2025-10-10T16:51:32Z

Hoa at 22:12, 28 October 2022

2022-10-28T22:12:15Z

Hoa at 23:45, 9 September 2022

2022-09-09T23:45:47Z

Hoa at 23:43, 9 September 2022

2022-09-09T23:43:07Z

Vince at 15:44, 11 February 2022

2022-02-11T15:44:36Z

Hoa at 03:05, 11 February 2022

2022-02-11T03:05:23Z

Hoa at 22:55, 12 October 2021

2021-10-12T22:55:53Z

@@ Line 28: / Line 28: @@
 We read the contents of the directory on first encountering it while checking for an include file. Subsequent searches will find the file in the cache instead of the actual disk.
-The cache is automatically cleared at the end of the veri_file::Analyze() or veri_file::AnalyzeMultipleFiles() calls. Note that we cannot keep it alive after the two analyze calls since there could possibly be a chdir() call which would make the cache invalid.
+The cache is automatically cleared at the end of the veri_file::Analyze() or veri_file::AnalyzeMultipleFiles() calls. Note that we cannot keep it alive after these two analyze calls since there could possibly be a chdir() call which would make the cache invalid.
   - Runtime flag "veri_share_nodes_in_static_elab"

@@ Line 31: / Line 31: @@
   - Runtime flag "veri_share_nodes_in_static_elab"
-Reduces memory and runtime for large designs. This flag will ensure that only one node will be created in static elaboration for each unique signature of a module, regardless of whether it is a top module or instantiated. The number of nodes that can be reduced depends on the nature of the design. For more details on this flag check [https://www.verific.com/faq/index.php?title=Source_code_customization_%26_Stable_release_services here]
+Reduces memory and runtime for large designs. This flag will ensure that only one node will be created in static elaboration for each unique signature of a module, regardless of whether it is a top module or instantiated. The number of nodes that can be reduced depends on the nature of the design. For more details on this flag check [https://www.verific.com/faq/index.php?title=Parse_tree_node_sharing_in_Static_Elaboration here]
   - Runtime flag "veri_ignore_always_constructs"

@@ Line 33: / Line 33: @@
 Reduces memory and runtime for large designs. This flag will ensure that only one node will be created in static elaboration for each unique signature of a module, regardless of whether it is a top module or instantiated. The number of nodes that can be reduced depends on the nature of the design. For more details on this flag check [https://www.verific.com/faq/index.php?title=Source_code_customization_%26_Stable_release_services here]
 The output netlist is not complete, but is useful if you are interested only in module interfaces and instantiations.
 Note that this flag is active only during RTL elaboration, not analysis. The input files still need to be Verilog-legal.
   - Runtime flag "edif_delete_view_contents_after_processing"

@@ Line 29: / Line 29: @@
 The cache is automatically cleared at the end of the veri_file::Analyze() or veri_file::AnalyzeMultipleFiles() calls. Note that we cannot keep it alive after the two analyze calls since there could possibly be a chdir() call which would make the cache invalid.
-  - Runtime flag "veri_ignore_always_constructs"
+  - Runtime flag "veri_share_nodes_in_static_elab"
 The output netlist is not complete, but is useful if you are interested only in module interfaces and instantiations.
 Note that this flag is active only during RTL elaboration, not analysis. The input files still need to be Verilog-legal.
   - Runtime flag "edif_delete_view_contents_after_processing"

@@ Line 11: / Line 11: @@
 Organizes the PortRef structures in an ordered array rather than a hash table. This saves a significant amount of memory since PortRefs are no longer individually allocated,
 and the overhead of a hash table is also saved.
   - Compile flag "VERILOG_QUICK_PARSE_V_FILES"     in verilog/VeriCompileFlags.h
 Normally a -v file may contain multiple module definitions. The Verilog parser is supposed to pick only the required modules from that file.
@@ Line 35: / Line 36: @@
 Note that this flag is active only during RTL elaboration, not analysis. The input files still need to be Verilog-legal.
   - Runtime flag "edif_link_case_insensitive"

@@ Line 46: / Line 46: @@
 For EDIF input.
-When stitching designs from multiple files, a view may be defined in more than one file. By default ("edif_keep_existing_view" disabled), the view being currently read survives, replacing the existing view. This may slow down the process because the existing view and it references in the Netlist Database has to be updated.
+When stitching designs from multiple files, a view may be defined in more than one file. By default ("edif_keep_existing_view" disabled), the view being currently read survives, replacing the existing view. This may slow down the process because the existing view and all of its references in the Netlist Database has to be updated.
-Enabling "edif_keep_existing_view" allows the reader to ignore the (duplicated) view being currently read. All references to the view being ignored will be updated to point to the existing view in the Netlist Database.
+Enabling "edif_keep_existing_view" allows the reader to ignore the (duplicated) view being currently read. All references to the view being ignored will be updated to point to the existing view in the Netlist Database. Only the references to the current view (in the current read operation) need to be updated to point to the existing view.

← Older revision		Revision as of 23:43, 9 September 2022
Line 35:		Line 35:

	Note that this flag is active only during RTL elaboration, not analysis. The input files still need to be Verilog-legal.		Note that this flag is active only during RTL elaboration, not analysis. The input files still need to be Verilog-legal.
		+
		+	- Runtime flag "edif_link_case_insensitive"
		+
		+	For EDIF input.
		+
		+	EDIF LRM does not define how existing external cells (maybe parsed from another language) should be linked to EDIF cells. We implemented case-insensitive (linear) search for these, which causes an N^2 complexity problem that slows down the reader for very large designs. Switching to case-sensitive search significantly speeds up the process, but there may be incidental cases where the EDIF reader does not link to an existing cell parsed from a different file.
		+
		+	- Runtime flag "edif_keep_existing_view"
		+
		+	For EDIF input.
		+
		+	When stitching designs from multiple files, a view may be defined in more than one file. By default ("edif_keep_existing_view" disabled), the view being currently read survives, replacing the existing view. This may slow down the process because the existing view and it references in the Netlist Database has to be updated.
		+
		+	Enabling "edif_keep_existing_view" allows the reader to ignore the (duplicated) view being currently read. All references to the view being ignored will be updated to point to the existing view in the Netlist Database.

@@ Line 2: / Line 2: @@
 Below are some common ones.
-  - Compile flag "VERIFIC_MEMORY_MANAGER"
+  - Compile flag "VERIFIC_MEMORY_MANAGER"    in util/VerificSystem.h
 Highly recommended.
 Enables the new, zero-overhead, Verific memory manager. Typically reduces memory usage of the Verific software by an additional 20% over the default system memory manager.
-  - Compile flag "DB_USE_PORT_ORDERED_PORTREF"
+  - Compile flag "DB_USE_PORT_ORDERED_PORTREF"     in database/DBCompileFlags.h
 Highly recommended.
 Organizes the PortRef structures in an ordered array rather than a hash table. This saves a significant amount of memory since PortRefs are no longer individually allocated,
 and the overhead of a hash table is also saved.
-  - Compile flag "VERILOG_QUICK_PARSE_V_FILES"
+  - Compile flag "VERILOG_QUICK_PARSE_V_FILES"     in verilog/VeriCompileFlags.h
 Normally a -v file may contain multiple module definitions. The Verilog parser is supposed to pick only the required modules from that file.
@@ Line 18: / Line 18: @@
 To prevent this, we provide this compile flag to quickly parse the file and see if it is actually required or not, without creating the parse tree. If it is not required we will ignore the file, otherwise we will fully parse it and pick the required modules.
-  - Compile flag "VERIFIC_LINEFILE_INCLUDES_COLUMNS"
+  - Compile flag "VERIFIC_LINEFILE_INCLUDES_COLUMNS"     in util/VerificSystem.h
 If you don't need the starting and ending locations including column info, turn this flag off.

← Older revision		Revision as of 03:05, 11 February 2022
Line 3:		Line 3:

	- Compile flag "VERIFIC_MEMORY_MANAGER"		- Compile flag "VERIFIC_MEMORY_MANAGER"
−	~~- Compile flag "VERIFIC_MEMORY_MANAGER_DEFINE_GLOBAL_NEW_DELETE"~~
	Highly recommended.		Highly recommended.

← Older revision		Revision as of 22:55, 12 October 2021
Line 3:		Line 3:

	- Compile flag "VERIFIC_MEMORY_MANAGER"		- Compile flag "VERIFIC_MEMORY_MANAGER"
		+	- Compile flag "VERIFIC_MEMORY_MANAGER_DEFINE_GLOBAL_NEW_DELETE"
	Highly recommended.		Highly recommended.