Instance - Module binding order - Revision history

Hoa at 00:41, 26 January 2024

2024-01-26T00:41:36Z

Vince at 18:04, 19 April 2023

2023-04-19T18:04:10Z

Hoa at 18:26, 21 February 2023

2023-02-21T18:26:05Z

Hoa at 23:27, 7 October 2022

2022-10-07T23:27:19Z

Hoa: Created page with "'''Q: Verilog has many ways to find modules not in the file being directly read: -L, -v, -y, .... There may be more than one module of the same name. What is the order of bind..."

2017-04-06T22:22:45Z

Created page with "'''Q: Verilog has many ways to find modules not in the file being directly read: -L, -v, -y, .... There may be more than one module of the same name. What is the order of bind..."

New page

'''Q: Verilog has many ways to find modules not in the file being directly read: -L, -v, -y, .... There may be more than one module of the same name. What is the order of binding?'''

The order of searching for modules is:

# While parsing:
## `uselib
## -work
## -L
## -y/-v
# While elaborating:
## configurations
## already resolved module from analysis, ie, order of parsing (above)

@@ Line 5: / Line 5: @@
 # While parsing:
 ## `uselib
 ## -L
 ## -y/-v (their order in an f-file is considered)
 # While elaborating:
 ## configurations
 ## already resolved module from analysis, ie, order of parsing (above)