Main Page - Revision history

Vince at 17:10, 10 October 2025

2025-10-10T17:10:57Z

2025-09-02T22:00:10Z

2025-07-14T18:52:55Z

2025-02-20T17:15:46Z

2025-02-19T20:38:57Z

2024-12-09T21:37:14Z

2024-10-19T01:08:38Z

2024-10-11T22:54:16Z

2024-09-06T19:02:01Z

2024-09-06T18:59:53Z

@@ Line 41: / Line 41: @@
 * [[SystemVerilog "std" package | SystemVerilog: Support for SystemVerilog semaphore/process/mailbox constructs.]]
 * [[Top level module with interface ports | SystemVerilog: Support for SystemVerilog top level module with interface ports.]]
 * [[Design with VHDL-1993 and VHDL-2008 files | VHDL: VHDL-1993 and VHDL-2008 each has its own IEEE library set. How do I analyze/elaborate a design with a mixture of files of different VHDL dialects (1993 and 2008)?]]
 * [[Escaped identifiers in RTL files and in Verific data structures | Verilog/VHDL: Escaped identifiers in RTL files and in Verific data structures]]

@@ Line 118: / Line 118: @@
 * [[Simple examples of VHDL visitor pattern | VHDL/C++: Simple examples of VHDL visitor pattern]]
 * [[Traverse instances in parsetree | VHDL/C++: Traverse instances in parsetree]]
 * [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]
 '''INVIO Code examples'''
 * [[Simple port modification | SystemVerilog/Python: Simple port modification]]

@@ Line 99: / Line 99: @@
 * [[How to get full hierarchy ID path | Verilog/C++: How to get full hierarchy ID path]]
 * [[How to traverse scope hierarchy | Verilog/C++: How to traverse scope hierarchy]]
 * [[Access attributes in parsetree | Verilog/C++: How to access attributes in parsetree]]
 * [[How to detect multiple-clock-edge condition in Verilog parsetree | Verilog/C++: How to detect multiple-clock-edge condition in Verilog parsetree]]

@@ Line 104: / Line 104: @@
 * [[Parse select modules only and ignore the rest | Verilog/C++: Parse select modules only and ignore the rest]]
 * [[Create DOT diagram of parse tree | Verilog/C++: Create DOT diagram of a parse tree]]
 * [[How to get parameters creation-time initial expression/value after Static Elaboration | Verilog/C++: How to get parameters creation-time initial expression/value after Static Elaboration]]
 * [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]

@@ Line 104: / Line 104: @@
 * [[Parse select modules only and ignore the rest | Verilog/C++: Parse select modules only and ignore the rest]]
 * [[Create DOT diagram of parse tree | Verilog/C++: Create DOT diagram of a parse tree]]
 * [[How to get linefile data of macros - Macro callback function | Verilog/C++/Perl/Python: How to get linefile data of macros - Macro callback function]]
 * [[Where in RTL does it get assigned? | Verilog/C++/Perl/Python: Where in RTL does it get assigned?]]

@@ Line 18: / Line 18: @@
 * [[Python pretty-printer for gdb | Python pretty-printer for gdb]]
 * [[Yosys-Verific Integration | Yosys-Verific integration]]
 '''Input: VHDL, Verilog (and SystemVerilog), Liberty, EDIF'''

@@ Line 49: / Line 49: @@
 * [[How to ignore parameters/generics in elaboration | Verilog/VHDL: Is there a way to tell the elaborator to ignore certain parameters/generics so that the unit/module is not uniquified?]]
 * [[How to check for errors in analysis/elaboration | Verilog/VHDL: Is there a way to tell if the analysis/elaboration process has errors?]]
-* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units/interfaces with "_default" suffix in their names. Why? And what are they?]]
+* [[Modules/design units with "_default" suffix in their names | Verilog/VHDL: After static elaboration, there are modules/design units/interfaces with "_default" or "or "_1, _2" suffix in their names. What are they?]]
 * [[How to parse a string | Verilog/VHDL: How to parse a string - Example of adding a module to the parsetree]]
 * [[Support IEEE 1735 encryption standard | Verilog/VHDL: Does Verific support IEEE 1735 encryption standard?]]

← Older revision		Revision as of 22:54, 11 October 2024
Line 115:		Line 115:
	* [[Traverse instances in parsetree \| VHDL/C++: Traverse instances in parsetree]]		* [[Traverse instances in parsetree \| VHDL/C++: Traverse instances in parsetree]]
	* [[Parsing from data in memory \| Verilog/VHDL/C++: Parsing from data in memory]]		* [[Parsing from data in memory \| Verilog/VHDL/C++: Parsing from data in memory]]
		+
		+	'''INVIO Code examples'''
		+	* [[Simple port modification \| SystemVerilog/Python: Simple port modification]]

@@ Line 111: / Line 111: @@
 * [[How to get packed dimensions of enum | SystemVerilog/C++: How to get packed dimensions of enum]]
 * [[How to replace a statement that has a label | SystemVerilog/C++: How to replace a statement that has a label]]
-* [[How to insert a statement, module item, into a sequential block or a generate block | SystemVerilog/C++: How to insert a statement, module item, into a sequential block or a generate block]]
+* [[How to insert/add a statement, or a module item, into a sequential block and a generate block | SystemVerilog/C++: How to insert/add a statement, or a module item, into a sequential block and a generate block]]
 * [[Simple examples of VHDL visitor pattern | VHDL/C++: Simple examples of VHDL visitor pattern]]
 * [[Traverse instances in parsetree | VHDL/C++: Traverse instances in parsetree]]
 * [[Parsing from data in memory | Verilog/VHDL/C++: Parsing from data in memory]]