Hoa: Created page with "'''Q: What language formats does Verific software support as output?''' Verific software can write out: * RTL Verilog/SystemVerilog (from parsetree) * RTL VHDL (from parsetr..."

2016-07-23T01:34:32Z

Created page with "'''Q: What language formats does Verific software support as output?''' Verific software can write out: * RTL Verilog/SystemVerilog (from parsetree) * RTL VHDL (from parsetr..."

New page

'''Q: What language formats does Verific software support as output?'''

Verific software can write out:

* RTL Verilog/SystemVerilog (from parsetree)
* RTL VHDL (from parsetree)
* Structural Verilog (from netlist database)
* Structural VHDL (from netlist database)
* BLIF (from netlist database)
* EDIF (from netlist database)

Output file formats - Revision history

Hoa: Created page with "'''Q: What language formats does Verific software support as output?''' Verific software can write out: * RTL Verilog/SystemVerilog (from parsetree) * RTL VHDL (from parsetr..."