Hoa: Created page with "It is possible to use "stream input" to parse data in memory. The example below is For Verilog input, but it can be adapted to use for VHLD input as well. If you run this ap..."

2020-06-01T21:12:59Z

Created page with "It is possible to use "stream input" to parse data in memory. The example below is For Verilog input, but it can be adapted to use for VHLD input as well. If you run this ap..."

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It is possible to use "stream input" to parse data in memory.

The example below is For Verilog input, but it can be adapted to use for VHLD input as well.

If you run this application with arguments pointing to a physical/existing file, it will parse that file.
If you do not pass any argument, it will produce error if "non-existing-file" does not exist.
And if you use "non-existing-file-1" or " non-existing-file-2" arguments, it will parse from memory/string.

<nowiki>
verific_stream *my_stream(const char *file_name)
{
// Handle normal physical files using Verific, by default:
if (!file_name || FileSystem::IsFile(file_name)) return 0 ;

std::string design_str ;
// Handle known mnemonics here:
if (Strings::compare(file_name, "non-existing-file-1")) {
// Use your own string in memory:
design_str = "module test (input in, output out) ; assign out = ~in ; endmodule" ;
} else if (Strings::compare(file_name, "non-existing-file-2")) {
// Use your own string in memory for some other condition:
design_str = "module test (input in, output out) ; buf (out, in) ; endmodule" ;
} else {
// Let Verific produce error:
return 0 ;
}

// Create a stream for this one:
std::istringstream *design_ist = new std::istringstream(design_str) ;
return new verific_istream(design_ist) ;
}

int main(int argc, const char **argv)
{
veri_file::RegisterFlexStreamCallBack(my_stream) ;

const char *file = (argc > 1) ? argv[1] : "non-existing-file" ;
if (!veri_file::Analyze(file)) return 1 ;

veri_file::PrettyPrint("out.v", 0) ;

return 0 ;
}
</nowiki>

Parsing from data in memory - Revision history

Hoa: Created page with "It is possible to use "stream input" to parse data in memory. The example below is For Verilog input, but it can be adapted to use for VHLD input as well. If you run this ap..."