Simple example of visitor pattern - Revision history

Mohammad at 02:13, 4 April 2026

2026-04-04T02:13:34Z

Hoa at 23:04, 6 September 2024

2024-09-06T23:04:57Z

Hoa at 18:08, 26 August 2022

2022-08-26T18:08:07Z

Hoa at 19:38, 27 October 2021

2021-10-27T19:38:22Z

Hoa at 18:01, 21 April 2021

2021-04-21T18:01:31Z

Hoa: Created page with " $ cat test.cpp #include #include "veri_file.h" #include "VeriModule.h" #include "VeriVisitor.h" #include "VeriConstVal.h" #include "Strings.h" #ifdef V..."

2020-12-08T00:32:34Z

Created page with " <nowiki> $ cat test.cpp #include <iostream> #include "veri_file.h" #include "VeriModule.h" #include "VeriVisitor.h" #include "VeriConstVal.h" #include "Strings.h" #ifdef V..."

New page

<nowiki>
$ cat test.cpp
#include <iostream>

#include "veri_file.h"
#include "VeriModule.h"
#include "VeriVisitor.h"
#include "VeriConstVal.h"

#include "Strings.h"

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

class MyVisitor : public VeriVisitor
{
public:
MyVisitor() : VeriVisitor() { }
virtual ~MyVisitor() { }

virtual void VERI_VISIT(VeriConst, node)
{
char *str = node.GetPrettyPrintedString() ;
node.Info("Got expression: %s", str) ;
Strings::free(str) ;
}
} ;

int main(int argc, char **argv)
{
if (!veri_file::Analyze("test.v")) return 1 ;

MyVisitor mv ;

MapIter mi ;
VeriModule *mod ;
FOREACH_VERILOG_MODULE(mi, mod) if (mod) mod->Accept(mv) ;

return 0 ;
}

$ cat test.v
module test ;
(* a = 1, b = 2.6 *) wire w ;
assign w = 2'b00 ;
endmodule

$ test-linux
-- Analyzing Verilog file 'test.v' (VERI-1482)
test.v(2): INFO: Got expression: 1
test.v(2): INFO: Got expression: 2.6
test.v(3): INFO: Got expression: 2'b0

$
</nowiki>

@@ Line 30: / Line 30: @@
 int main (int argc, char **argv)
+{
-     const char *file_name = "test.sv" ; // defaulf input filename
+     const char *file_name = "test.sv" ;
-     if (argc > 1) file_name = argv[1] ; // Set the file name as specified by the user
+     if (argc > 1) file_name = argv[1] ;
-    // veri_file::Analyze(const char *file_name, unsigned verilog_mode=VERILOG_2K, const char *lib_name="work", unsigned cu_mode=NO_MODE) ;
      if (!veri_file::Analyze(file_name, veri_file::SYSTEM_VERILOG)) return 1 ;
+#if 0
-     // if (!veri_file::ElaborateAllStatic()) return 1 ;
+     if (!veri_file::ElaborateAllStatic()) return 1 ;
+#endif
      MyVisitor mv ;

@@ Line 28: / Line 28: @@
 } ;
-int main()
+int main (int argc, char **argv)
+{
-     if (!veri_file::Analyze("test.v")) return 1 ;
+    const char *file_name = "test.sv" ; // defaulf input filename
      MyVisitor mv ;
@@ Line 41: / Line 46: @@
+}
-$ cat test.v
+$ cat test.sv
 module test ;
      (* a = 1, b = 2.6 *) wire w ;
@@ Line 48: / Line 53: @@
 $ test-linux
--- Analyzing Verilog file 'test.v' (VERI-1482)
+-- Analyzing Verilog file 'test.sv' (VERI-1482)
-test.v(2): INFO: Got expression: 1
+test.sv(2): INFO: Got expression: 1
-test.v(2): INFO: Got expression: 2.6
+test.sv(2): INFO: Got expression: 2.6
-test.v(3): INFO: Got expression: 2'b0
+test.sv(3): INFO: Got expression: 2'b0
-−
+$
   </nowiki>

@@ Line 7: / Line 7: @@
 #include "VeriVisitor.h"
 #include "VeriConstVal.h"
 #include "Strings.h"

@@ Line 1: / Line 1: @@
   <nowiki>
 $ cat test.cpp
 #include <iostream>
 #include "veri_file.h"
 #include "VeriModule.h"
 #include "VeriVisitor.h"
 #include "VeriConstVal.h"
 #include "Strings.h"
@@ Line 52: / Line 51: @@
 test.v(2): INFO: Got expression: 2.6
 test.v(3): INFO: Got expression: 2'b0
+$
   </nowiki>