System attributes - Revision history

Hoa at 07:12, 11 September 2022

2022-09-11T07:12:38Z

2022-09-11T07:08:38Z

2021-12-04T04:30:00Z

2021-12-04T04:26:48Z

2021-10-08T18:13:29Z

2021-10-08T18:12:13Z

2021-04-12T20:17:13Z

2021-04-12T20:01:22Z

2020-06-15T08:36:35Z

2020-05-09T03:05:32Z

@@ Line 21: / Line 21: @@
      (" wired", "1")
      (" is_up_dir", "1")
-     (" Init Val", value) // initial value, if compile flag DB_PRESERVE_INITIAL_VALUE is enabled
+     (" init_val", value) // initial value, if compile flag DB_PRESERVE_INITIAL_VALUE is enabled
      (" original_name", name) // original name in the input file, for nets being renamed to avoid to name conflict
      (" supply0", "1") // from Verilog "supply0" construct
@@ Line 34: / Line 34: @@
 Port
      (" orig_port_name", name)
-     (" Init Val", value) // initial value, if compile flag DB_PRESERVE_INITIAL_VALUE is enabled
+     (" init_val", value) // initial value, if compile flag DB_PRESERVE_INITIAL_VALUE is enabled
      (" created_from_test_cell", "1") // created from test cell in SynLib
      (" open_port", "1")

@@ Line 21: / Line 21: @@
      (" wired", "1")
      (" is_up_dir", "1")
      (" original_name", name) // original name in the input file, for nets being renamed to avoid to name conflict
      (" supply0", "1") // from Verilog "supply0" construct
@@ Line 33: / Line 34: @@
 Port
      (" orig_port_name", name)
      (" created_from_test_cell", "1") // created from test cell in SynLib
      (" open_port", "1")

@@ Line 3: / Line 3: @@
 To distinguish with user-declared attributes, the key (name) of a system attribute has a space as the first character.
-Below is the list of system attributes in the Netlist database. Note that depending on the flow, a DesignObj may or may not have a particular attribute. Some attributes depend on run-time flag settings.
+System attributes are not written out in the Verilog netlist output, unless when the runtime flag "db_verilog_writer_write_internal_data" is enabled.
   <nowiki>
 Instance

@@ Line 3: / Line 3: @@
 To distinguish with user-declared attributes, the key (name) of a system attribute has a space as the first character.
-Below is the list of system attributes in the Netlist database. Note that depending on the flow, a DesignObj may or may not have a particular attribute.
+Below is the list of system attributes in the Netlist database. Note that depending on the flow, a DesignObj may or may not have a particular attribute. Some attributes depend on run-time flag settings.
   <nowiki>
 Instance
@@ Line 14: / Line 14: @@
      (" BLOCKING", "1") // ReadPort/WritePort only
      (" from_array_inst", (full_name)?full_name:inst_name)
 Net
      (" basic_constant", const_val) // is driven by a constant and also connected to a blackbox

@@ Line 68: / Line 68: @@
   <nowiki>
- if (netlist->GetAttValue(" language")) {
+if (netlist->GetAttValue(" language")) {
-            Message::Msg(VERIFIC_INFO, 0, 0, "       from %s", netlist->GetAttValue(" language"));
+    Message::Msg(VERIFIC_INFO, 0, 0, "       from %s", netlist->GetAttValue(" language"));
-        } else {
+} else {
-            Message::Msg(VERIFIC_INFO, 0, 0, "       no language");
+    Message::Msg(VERIFIC_INFO, 0, 0, "       no language");
   </nowiki>

@@ Line 35: / Line 35: @@
      (" orig_port_name", name)
 Netlist
-     (" language", "edif") // the language it comes from - "edif", "verilog", "vhdl", "upf", "synlib", "upf"
+     (" language", language_name) // the language it comes from - "edif", "verilog", "vhdl", "upf", "synlib", "upf"
      (" cell_name", module_name) // original module/unit name in input file
      (" from_netlist_reader", "1") // from structural netlist reader (not synthesized from RTL)
@@ Line 64: / Line 64: @@
+}
   </nowiki>

@@ Line 38: / Line 38: @@
      (" cell_name", module_name) // original module/unit name in input file
      (" from_netlist_reader", "1") // from structural netlist reader (not synthesized from RTL)
-     (" primitive", "1")
+     (" primitive", "1") // netlist is a Verific primitive
      (" unknown_design", "2")) // "1" for Verilog instance, "2" for VHDL instance
      (" changed_by_interface_overwrite", "1")
      (" changed_by_hier_ref", "1")
-     (" celldefine","1")
+     (" celldefine","1") // netlist has "`celldefine" directive
-     (" package", "1")
+     (" package", "1") // netlist comes from a VHDL package
-     (" upf_uniquified", "1"))
+     (" upf_uniquified", "1")) // from ups reader
-     (" is_sequential", 0)
+     (" is_sequential", 0) // from synlib reader
-     (" is_latch", 0)
+     (" is_latch", 0) // from synlib reader
   </nowiki>

@@ Line 60: / Line 60: @@
      Message::Msg(VERIFIC_INFO, 0, 0, "   -- attribute name: %s, value: %s", attr->Key(), attr->Value());
+}
   </nowiki>