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		<id>https://www.verific.com/faq/index.php?title=Verific_data_structure&amp;diff=186&amp;oldid=prev</id>
		<title>Hoa: Created page with &quot;'''Q: What are the data structures in Verific?'''  There are 2 data structures in Verific: parsetree and netlist database.  1. The parsetree is just another representation of...&quot;</title>
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				<updated>2016-07-22T22:35:51Z</updated>
		
		<summary type="html">&lt;p&gt;Created page with &amp;quot;&amp;#039;&amp;#039;&amp;#039;Q: What are the data structures in Verific?&amp;#039;&amp;#039;&amp;#039;  There are 2 data structures in Verific: parsetree and netlist database.  1. The parsetree is just another representation of...&amp;quot;&lt;/p&gt;
&lt;p&gt;&lt;b&gt;New page&lt;/b&gt;&lt;/p&gt;&lt;div&gt;'''Q: What are the data structures in Verific?'''&lt;br /&gt;
&lt;br /&gt;
There are 2 data structures in Verific: parsetree and netlist database.&lt;br /&gt;
&lt;br /&gt;
1. The parsetree is just another representation of the design.  It contains the exact information as in the RTL files, only in a machine-readable format.  Because each language (Verilog or VHDL) has its own constructs, each language has its own parsetree.&lt;br /&gt;
&lt;br /&gt;
The parsetree is the result of veri_file::Analyze()/vhdl_file::Ananlyze().&lt;br /&gt;
&lt;br /&gt;
The design parsetree can be &amp;quot;statically elaborated.&amp;quot;  These are some of the&lt;br /&gt;
operations during static elaboration process:&lt;br /&gt;
&lt;br /&gt;
- Unrolling &amp;quot;generate&amp;quot; loops.&lt;br /&gt;
- Evaluating constant expressions.&lt;br /&gt;
- Uniquifying instances of parameterized modules/entities.&lt;br /&gt;
&lt;br /&gt;
The result of static elaboration is a modified parsetree.&lt;br /&gt;
&lt;br /&gt;
The parsetree supports all constructs of the language.&lt;br /&gt;
&lt;br /&gt;
2. The synthesizable subset of the parsetree can go through &amp;quot;RTL elaboration&amp;quot; (or &amp;quot;synthesis&amp;quot;).  The result is the &amp;quot;netlist database,&amp;quot; consisting of &amp;quot;hardware&amp;quot; components: libraries, cells, netlists, nets, ports, instances, operators (adders, muxes, ...), and primitives (ands, ors, xors, ...).  The netlist database is language-independent.  The contents of the netlist database can be written out in various structural languages: Verilog, VHDL, EDIF, BLIF.  In general, the output netlist from the netlist database does not look anything like the RTL input files.&lt;br /&gt;
&lt;br /&gt;
The netlist database is the result of veri_file::Elaborate()/vhdl_file::Elaborate() API (after veri_file::Analyze()/vhdl_file::Analyze()).&lt;br /&gt;
&lt;br /&gt;
RTL elaboration supports the synthesizable subset of the language.&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
Note that during RTL elaboration, Verific software creates a netlist directly from the parse tree. It does not build a control and data flow graph (CDFG). If an application needs a CDFG, it will have to define the graph structure and use Verific parse tree traversal routines to build the graph.&lt;/div&gt;</summary>
		<author><name>Hoa</name></author>	</entry>

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