Verific data structures - Revision history

Vince at 23:13, 27 April 2020

2020-04-27T23:13:59Z

Hoa at 23:56, 4 March 2019

2019-03-04T23:56:11Z

Hoa at 23:55, 4 March 2019

2019-03-04T23:55:49Z

Hoa at 00:10, 23 July 2016

2016-07-23T00:10:11Z

Hoa at 23:43, 22 July 2016

2016-07-22T23:43:14Z

Hoa: Created page with "'''Q: What are the data structures in Verific?''' There are 2 data structures in Verific: parsetree and netlist database. 1. The parsetree is just another representation of..."

2016-07-22T22:37:18Z

Created page with "'''Q: What are the data structures in Verific?''' There are 2 data structures in Verific: parsetree and netlist database. 1. The parsetree is just another representation of..."

New page

'''Q: What are the data structures in Verific?'''

There are 2 data structures in Verific: parsetree and netlist database.

1. The parsetree is just another representation of the design. It contains the exact information as in the RTL files, only in a machine-readable format. Because each language (Verilog or VHDL) has its own constructs, each language has its own parsetree.

The parsetree is the result of veri_file::Analyze()/vhdl_file::Ananlyze().

The design parsetree can be "statically elaborated." These are some of the
operations during static elaboration process:

- Unrolling "generate" loops.
- Evaluating constant expressions.
- Uniquifying instances of parameterized modules/entities.

The result of static elaboration is a modified parsetree.

The parsetree supports all constructs of the language.

2. The synthesizable subset of the parsetree can go through "RTL elaboration" (or "synthesis"). The result is the "netlist database," consisting of "hardware" components: libraries, cells, netlists, nets, ports, instances, operators (adders, muxes, ...), and primitives (ands, ors, xors, ...). The netlist database is language-independent. The contents of the netlist database can be written out in various structural languages: Verilog, VHDL, EDIF, BLIF. In general, the output netlist from the netlist database does not look anything like the RTL input files.

The netlist database is the result of veri_file::Elaborate()/vhdl_file::Elaborate() API (after veri_file::Analyze()/vhdl_file::Analyze()).

RTL elaboration supports the synthesizable subset of the language.

Note that during RTL elaboration, Verific software creates a netlist directly from the parse tree. It does not build a control and data flow graph (CDFG). If an application needs a CDFG, it will have to define the graph structure and use Verific parse tree traversal routines to build the graph.

@@ Line 7: / Line 7: @@
 The parsetree is just another representation of the design.  It contains the exact information as in the RTL files, only in a machine-readable format.  Because each language (Verilog or VHDL) has its own constructs, each language has its own parsetree.
-:The parsetree is the result of veri_file::Analyze()/vhdl_file::Ananlyze().
+:The parsetree is the result of veri_file::Analyze()/vhdl_file::Analyze().
 :The design parsetree can be "statically elaborated."  These are some of the operations during static elaboration process:

← Older revision		Revision as of 23:56, 4 March 2019
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−	Note that during RTL elaboration, Verific software creates a netlist directly from the parse tree. It does not build a control and data flow graph (CDFG). If an application needs a CDFG, it will have to define the graph structure and use Verific parse tree traversal routines (or Verific Netlist database traversal routines) to build the graph.	+	Note that during RTL elaboration, Verific software creates a netlist directly from the parse tree. It does not build a control and data flow graph (CDFG). If an application needs a CDFG, it will have to define the graph structure and use Verific parse tree traversal routines or Verific Netlist database traversal routines to build the graph.

← Older revision		Revision as of 23:55, 4 March 2019
Line 28:		Line 28:


−	Note that during RTL elaboration, Verific software creates a netlist directly from the parse tree. It does not build a control and data flow graph (CDFG). If an application needs a CDFG, it will have to define the graph structure and use Verific parse tree traversal routines to build the graph.	+	Note that during RTL elaboration, Verific software creates a netlist directly from the parse tree. It does not build a control and data flow graph (CDFG). If an application needs a CDFG, it will have to define the graph structure and use Verific parse tree traversal routines (or Verific Netlist database traversal routines) to build the graph.

@@ Line 3: / Line 3: @@
 There are 2 data structures in Verific: parsetree and netlist database.
-. The parsetree is just another representation of the design.  It contains the exact information as in the RTL files, only in a machine-readable format.  Because each language (Verilog or VHDL) has its own constructs, each language has its own parsetree.
+;Parsetree
-The parsetree is the result of veri_file::Analyze()/vhdl_file::Ananlyze().
+The parsetree is just another representation of the design.  It contains the exact information as in the RTL files, only in a machine-readable format.  Because each language (Verilog or VHDL) has its own constructs, each language has its own parsetree.
-The design parsetree can be "statically elaborated."  These are some of the
+:The parsetree is the result of veri_file::Analyze()/vhdl_file::Ananlyze().
-operations during static elaboration process:
-* Unrolling "generate" loops.
+:The design parsetree can be "statically elaborated."  These are some of the operations during static elaboration process:
-* Evaluating constant expressions.
-* Uniquifying instances of parameterized modules/entities.
-The result of static elaboration is a modified parsetree.
+:* Unrolling "generate" loops.
-The parsetree supports all constructs of the language.
+:The result of static elaboration is a modified parsetree.
-. The synthesizable subset of the parsetree can go through "RTL elaboration" (or "synthesis").  The result is the "netlist database," consisting of "hardware" components: libraries, cells, netlists, nets, ports, instances, operators (adders, muxes, ...), and primitives (ands, ors, xors, ...).  The netlist database is language-independent.  The contents of the netlist database can be written out in various structural languages: Verilog, VHDL, EDIF, BLIF.  In general, the output netlist from the netlist database does not look anything like the RTL input files.
+:The parsetree supports all constructs of the language.
 The netlist database is the result of veri_file::Elaborate()/vhdl_file::Elaborate() API (after veri_file::Analyze()/vhdl_file::Analyze()).