Verilog Port Expressions - Revision history

Hoa at 21:40, 13 February 2023

2023-02-13T21:40:15Z

Hoa at 17:59, 10 February 2023

2023-02-10T17:59:12Z

Hoa: Hoa moved page Verilog ports being renamed to Verilog Port Expressions

2023-02-10T17:27:30Z

Hoa moved page Verilog ports being renamed to Verilog Port Expressions

Hoa at 20:34, 23 December 2020

2020-12-23T20:34:53Z

Hoa at 20:33, 23 December 2020

2020-12-23T20:33:10Z

Hoa: Created page with "'''Q: Why are the ports in original Verilog file renamed to p1, p2, ....?''' Input file: module foo ( datain[0], datain[0] /* same net into multiple port expression */,..."

2016-07-22T22:58:51Z

Created page with "'''Q: Why are the ports in original Verilog file renamed to p1, p2, ....?''' Input file: module foo ( datain[0], datain[0] ‎same net into multiple port expression: ,..."

New page

'''Q: Why are the ports in original Verilog file renamed to p1, p2, ....?'''

Input file:
module foo ( datain[0], datain[0] /* same net into multiple port expression */,
datain[2:1] /* part-select port expression */,
/* empty port expression */,
{datain[2],datain[1], datain[1]} /* concatenation in port expression */
) ;
input [2:0] datain ;
...
endmodule

Output netlist:
module foo (p1, p2, p3, , p7); // test.v(1[8:11])
input p1; // test.v(6[17:23])
input p2; // test.v(6[17:23])
input [1:0]p3;
input [2:0]p7;
...
endmodule

The items in the () after the module name are not "port names," rather, they are "port expressions." Verilog defines that the port expressions on this module CANNOT be accessed by name (only by order). This means you cannot rely on the port names to be one thing or another.

Verific chose to not adjust to any particular naming scheme for complex port expressions, which also allows us to error out if named port instantiation occurs where the language disallows it.

The original port expression of the renamed port is saved as attributes " orig_port_name" attached to the port.

key: " orig_port_name", value: port expression

For the testcase above:

input p1 /* verific orig_port_name=datain[0] */ ;
input p2 /* verific orig_port_name=datain[0] */ ;
input [1:0]p3 /* verific orig_port_name=datain[2] datain[1] */ ;
input [2:0]p7 /* verific orig_port_name=datain[2] datain[1] datain[1] */ ;

@@ Line 4: / Line 4: @@
   <nowiki>
 // Example of port expressions
-module test (datain[0], datain[0] /* same net into multiple port expression */,
+module bot (datain[0], datain[0] /* same net into multiple port expression */,
               datain[2:1]  /* part-select port expression */,
               /* empty port expression - nothing between the two commas */,
@@ Line 12: / Line 12: @@
      input [2:0] datain;
      output [3:0] dataout;
 endmodule
   </nowiki>
@@ Line 45: / Line 61: @@
 :''The port expression is optional because ports can be defined that do not connect to anything internal to the module.''
-For the example above, the netlist output from Verific is (note the leading space character of the attribute " orig_port_name"):
+Note that Verific created ports with name for empty ports. By default, the empty ports are not written out in the Verilog netlist output (similar to the module in the input RTL file).
   <nowiki>
 //
-// Verific Verilog Description of module test
+// Verific Verilog Description of module top
 //
-module test (p1, p2, p3, , p7, p11, p12, ) /* verific  language=verilog,  cell_name=test */ ;   // test.sv(2)
+module bot (p1, p2, p3, p6, p7, p11, p12, p16) /* verific  language=verilog,  cell_name=bot, language="verilog", cell_name="bot" */ ;   // test.v.golden.new(35)
-     input p1 /* verific  orig_port_name=datain[0] */ ;
+     input p1 /* verific orig_port_name="datain" */ ;   // test.v.golden.new(36)
-     input p2 /* verific  orig_port_name=datain[0] */ ;
+     input p2 /* verific orig_port_name="datain" */ ;   // test.v.golden.new(37)
-     input [1:0]p3 /* verific  orig_port_name=datain[2] datain[1] */ ;
+     input [1:0]p3;   // test.v.golden.new(38)
-     input [2:0]p7 /* verific  orig_port_name=datain[2] datain[1] datain[1] */ ;
+    input p6 /* verific empty_port=1 */ ;   // test.v.golden.new(39)
-     output p11 /* verific  orig_port_name=dataout[3] */ ;
+     input [2:0]p7;   // test.v.golden.new(40)
-     output [2:0]p12 /* verific  orig_port_name=dataout[2] dataout[1] dataout[0] */ ;
+     output p11 /* verific orig_port_name="dataout" */ ;   // test.v.golden.new(41)
      // Printing the identifier types
-     // datain   :   input [2:0] reg : nets: datain(bus)
+     // p1   :   input  wire : nets: p1(net)
-     // dataout   :   output [3:0] reg : nets: dataout(bus)
+    // p2   :   input  wire
-     assign p1 = p2 /* verific  orig_port_name=datain[0] */ ;
+     assign p1 = p2 /* verific orig_port_name="datain" */ ;   // test.v.golden.new(36)
-     assign p3[1] = p7[2] /* verific  orig_port_name=datain[2] */ ;
+     assign p3[1] = p7[2] /* verific orig_port_name="datain" */ ;   // test.v.golden.new(38)
-     assign p3[0] = p7[0] /* verific  orig_port_name=datain[1] */ ;
+     assign p3[0] = p7[1] /* verific orig_port_name="datain" */ ;   // test.v.golden.new(38)
-     assign p7[1] = p7[0] /* verific  orig_port_name=datain[1] */ ;
+     assign p7[0] = p7[1] /* verific orig_port_name="datain" */ ;   // test.v.golden.new(40)
 endmodule
   </nowiki>

@@ Line 1: / Line 1: @@
-'''Q: Why are the ports in original Verilog file renamed to p1, p2, ....?'''
+'''Q1: Why are the ports in original Verilog RTL file renamed to p1, p2, ... in the output netlist?'''
-Input file:
+Verilog RTL file:
-    module foo ( datain[0],  datain[0] /* same net into multiple port expression */,
+ <nowiki>
-                 datain[2:1]  /* part-select  port expression */,
+// Example of port expressions
-                 /* empty port expression */,
+module test (datain[0], datain[0] /* same net into multiple port expression */,
-                 {datain[2],datain[1], datain[1]} /* concatenation in port expression */
+             datain[2:1]  /* part-select port expression */,
-                ) ;
+             /* empty port expression - nothing between the two commas */,
-        input [2:0] datain ;
+             {datain[2], datain[1], datain[1]} /* concatenation in port expression */,
-        ...
+             dataout[3], {dataout[2:0]}, /* another empty port expression due to the extra comma */
-    endmodule
+            );
-Output netlist:
+Verific chooses to not adjust any particular naming scheme for complex port expressions, which also allows us to error out if named port instantiation occurs where the language disallows it.
-    module foo (p1, p2, p3, , p7);   // test.v(1[8:11])
-        input p1;   // test.v(6[17:23])
-        input p2;   // test.v(6[17:23])
-        input [1:0]p3;
-        input [2:0]p7;
-        ...
-    endmodule
-The items in the () after the module name are not "port names," rather, they are "port expressions." Verilog defines that the port expressions on this module CANNOT be accessed by name (only by order). This means you cannot rely on the port names to be one thing or another.
+'''Q2: Are "empty" ports Verilog-legal?'''
-Verific chose to not adjust to any particular naming scheme for complex port expressions, which also allows us to error out if named port instantiation occurs where the language disallows it.
+The Verilog example at the top of the page contains two "empty" port expressions (nothing between two commas or an extra comma at the end of the port expression list). This is legal as shown below:
-The original port expression of the renamed port is saved as attributes " orig_port_name" attached to the port.
+In BNF section A.1.2 of IEEE 1800-2017 LRM:
-    key: " orig_port_name", value: port expression
+In section 23.2.2.1 of the same LRM on "Non-ANSI style port declarations":
-For the testcase above:
+ <nowiki>
      input p1 /* verific  orig_port_name=datain[0] */ ;
      input p2 /* verific  orig_port_name=datain[0] */ ;
      input [1:0]p3 /* verific  orig_port_name=datain[2] datain[1] */ ;
      input [2:0]p7 /* verific  orig_port_name=datain[2] datain[1] datain[1] */ ;

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