Revision history of "Why are the ports"

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  • (cur | prev) 17:15, 8 July 2016‎ 74.95.193.145 (Talk)‎ . . (1,602 bytes) (+1,602)‎ . . (Created page with "'''Q: Why are the ports in original Verilog file renamed to p1, p2, ....?''' Input file: module foo ( datain[0], datain[0] →‎same net into multiple port expression: ,...")