Difference between revisions of "Output file formats"
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(Created page with "'''Q: What language formats does Verific software support as output?''' Verific software can write out: * RTL Verilog/SystemVerilog (from parsetree) * RTL VHDL (from parsetr...") |
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Latest revision as of 17:34, 22 July 2016
Q: What language formats does Verific software support as output?
Verific software can write out:
- RTL Verilog/SystemVerilog (from parsetree)
- RTL VHDL (from parsetree)
- Structural Verilog (from netlist database)
- Structural VHDL (from netlist database)
- BLIF (from netlist database)
- EDIF (from netlist database)
