Difference between revisions of "Remove Verific data structures"

Latest revision as of 17:15, 18 October 2024

Q: How do I remove all Verific data structures in memory?

To remove hdl file sorting data:

   hdl_file_sort::Reset();

To reset file system cache:

   FileSystem::ResetDirectoryCache();

To remove Verilog parsetree:

   veri_file::Reset();

To remove VHDL parsetree:

   vhdl_file::Reset();

To remove synlib parsetree:

   synlib_file::Reset();

To remove hierarchy tree:

   hier_tree::DeleteHierarchicalTree() ;

To remove UPF data structures:

   upf_file::DeleteAll();

To remove the netlist database:

   Libset::Reset();

To remove linefile data (make sure that you've removed all parsetrees and the netlist database):

   LineFile::DeleteAllLineFiles();
   LineFile::ResetFileIdMaps();

To remove message type settings:

   Message::Reset();

To reset run-time flags:

   RuntimeFlags::DeleteAllFlags();

@@ Line 1: / Line 1: @@
 '''Q: How do I remove all Verific data structures in memory?'''
+To remove hdl file sorting data:
+    hdl_file_sort::Reset();
+To reset file system cache:
+    FileSystem::ResetDirectoryCache();
 To remove Verilog parsetree:
@@ Line 9: / Line 17: @@
      vhdl_file::Reset();
-To remove synlib structures:
+To remove synlib parsetree:
      synlib_file::Reset();