Difference between revisions of "System attributes"

Latest revision as of 09:54, 29 June 2026

Verific system attributes are attributes added and attached to DesignObjs (Design Objects) during the process of building the Netlist Database.

To distinguish with user-declared attributes, the key (name) of a system attribute has a space as the first character.

System attributes are not written out in the Verilog netlist output, unless when the runtime flag "db_verilog_writer_write_internal_data" is enabled.

Below is the list of system attributes in the Netlist database. Note that depending on the flow, a DesignObj may or may not have a particular attribute. Some attributes depend on runtime flag settings.

Instance
    (" named_group", named_group)
    (" GATE_TYPE", "gated_clock")
    (" creating_port_refs", "1")
    (" enum_encoding", user_encoding)      // DFF
    (" PROCESS_ID", buffer)                // ReadPort/WritePort only
    (" is_concurrent", "1")                // ReadPort/WritePort only
    (" BLOCKING", "1")                     // ReadPort/WritePort only
    (" instantiated_primitive", "1")       // for directly-instantiated Verilog primitives
    (" instantiated_vfc_primitive", "1")   // for directly-instantiated Verific primitives
    (" from_array_inst", (full_name)?full_name:inst_name)
Net
    (" wired", "1")
    (" is_up_dir", "1")
    (" basic_constant", const_val)         // is driven by a constant and also connected to a blackbox
    (" init_val", value)                   // initial value if compile flag DB_PRESERVE_INITIAL_VALUE enabled
    (" original_name", name)               // original name per input file for renamed nets to avoid to name conflict
    (" supply0", "1")                      // from Verilog "supply0" construct
    (" supply1", "1")                      // from Verilog "supply1" construct
    (" specify_cond", cond_pp)             // SDF only
    (" global_clocking_ref", "1")          // SVA
    (" sva_clock_ref", "1")                // SVA
    (" enum_encoding", user_encoding)
    (" package_net", "1")
NetBus
    (" original_name", name)
Port
    (" orig_port_name", name)
    (" init_val", value) // initial value, if compile flag DB_PRESERVE_INITIAL_VALUE is enabled
    (" created_from_test_cell", "1")       // created from test cell in SynLib
    (" open_port", "1")
PortBus
    (" orig_port_name", name)
Netlist
    (" language", language_name)           // the language of origin: "edif", "verilog", "vhdl", "upf", "synlib", "upf"
    (" cell_name", module_name)            // original module/unit name in input file
    (" from_netlist_reader", "1")          // from structural netlist reader (not synthesized from RTL)
    (" primitive", "1")                    // netlist is a UDP primitive
    (" unknown_design", "2"))              // "1" for Verilog instance, "2" for VHDL instance
    (" celldefine","1")                    // netlist has "`celldefine" directive
    (" package", "1")                      // netlist comes from a VHDL package
    (" upf_uniquified", "1"))              // from ups reader
    (" is_sequential", 0)                  // from synlib reader
    (" is_latch", 0)                       // from synlib reader
    (" changed_by_interface_overwrite", "1")
    (" changed_by_hier_ref", "1")
 

To access the attributes of a DesignObj, use macro FOREACH_ATTRIBUTE. For example:

C++:

Netlist *netlist = ....; // or any other derived class from DesignObj
Att *attr;
MapIter mi;
FOREACH_ATTRIBUTE(netlist, mi, attr) {           
    const char *key = (attr) ? attr->Key() : 0 ;
    if (!key) continue ;
    if (key[0] == ' ') continue ; // if you want to skip system attributes
    // Do whatever you want here, e.g.            
    Message::Msg(VERIFIC_INFO, 0, 0, "   -- attribute name: %s, value: %s", attr->Key(), attr->Value());
}
 

You can get a particular attribute. For example:

if (netlist->GetAttValue(" language")) {
    Message::Msg(VERIFIC_INFO, 0, 0, "       from %s", netlist->GetAttValue(" language"));
} else {
    Message::Msg(VERIFIC_INFO, 0, 0, "       no language");
}