Difference between revisions of "Accessing and evaluating module's parameters"
From Verific Design Automation FAQ
(Created page with " <nowiki> #include "Map.h" #include "Array.h" #include "Strings.h" #include "veri_file.h" #include "VeriBaseValue_Stat.h" #include "VeriModule.h" #include "VeriExpression.h" #...") |
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| (2 intermediate revisions by the same user not shown) | |||
| Line 33: | Line 33: | ||
unsigned i ; | unsigned i ; | ||
FOREACH_ARRAY_ITEM (module_items, i, module_item) { | FOREACH_ARRAY_ITEM (module_items, i, module_item) { | ||
| + | if (!module_item) continue ; | ||
if (!(module_item->IsParamDecl()) && !(module_item->IsLocalParamDecl())) continue ; | if (!(module_item->IsParamDecl()) && !(module_item->IsLocalParamDecl())) continue ; | ||
VeriDataDecl * param_decl = static_cast<VeriDataDecl *>(module_item) ; | VeriDataDecl * param_decl = static_cast<VeriDataDecl *>(module_item) ; | ||
| Line 52: | Line 53: | ||
Message::PrintLine(" local param: ", param->Name()) ; | Message::PrintLine(" local param: ", param->Name()) ; | ||
} | } | ||
| − | VeriExpression * | + | VeriExpression *initial_expr = param->GetInitialValue() ; |
| − | if ( | + | if (initial_expr) { |
| − | Message::PrintLine(" initial expression: ", | + | Message::PrintLine(" initial expression: ", initial_expr->GetPrettyPrintedString()) ; |
| − | VeriBaseValue *val = | + | VeriBaseValue *val = initial_expr->StaticEvaluate(0, 0) ; |
int int_val = val ? val->GetIntegerValue() : 0 ; | int int_val = val ? val->GetIntegerValue() : 0 ; | ||
Message::PrintLine(" initial value: ", Strings::itoa(int_val)) ; | Message::PrintLine(" initial value: ", Strings::itoa(int_val)) ; | ||
| Line 65: | Line 66: | ||
} | } | ||
</nowiki> | </nowiki> | ||
| + | <nowiki> | ||
$ cat test.v | $ cat test.v | ||
module leaf(bus); | module leaf(bus); | ||
| Line 133: | Line 135: | ||
$ | $ | ||
| − | <nowiki> | + | </nowiki> |
Latest revision as of 12:14, 27 July 2021
#include "Map.h"
#include "Array.h"
#include "Strings.h"
#include "veri_file.h"
#include "VeriBaseValue_Stat.h"
#include "VeriModule.h"
#include "VeriExpression.h"
#include "VeriId.h"
#include "RuntimeFlags.h"
#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif
int main(int argc, char **argv)
{
const char *file = (argc > 1) ? argv[1] : "test.v" ;
if (!veri_file::Analyze(file, veri_file::SYSTEM_VERILOG)) return 1 ;
// If you want to replace constant expressions during static elaboration
// RuntimeFlags::SetVar("veri_replace_const_exprs", 1) ;
// If you want to run static elaboration
veri_file::ElaborateAllStatic() ;
MapIter mi ;
VeriModule *mod ;
FOREACH_VERILOG_MODULE(mi, mod) {
Message::PrintLine("module: ", mod->Name()) ;
Array *module_items = mod->GetModuleItems() ;
VeriModuleItem *module_item ;
unsigned i ;
FOREACH_ARRAY_ITEM (module_items, i, module_item) {
if (!module_item) continue ;
if (!(module_item->IsParamDecl()) && !(module_item->IsLocalParamDecl())) continue ;
VeriDataDecl * param_decl = static_cast<VeriDataDecl *>(module_item) ;
/*
VeriDataType *data_type = param_decl->GetDataType() ;
if (data_type) {
Message::PrintLine(" data type: ", data_type->GetPrettyPrintedString()) ;
}
*/
Array *param_array = param_decl->GetIds() ;
VeriIdDef *param ;
unsigned i ;
FOREACH_ARRAY_ITEM (param_array, i, param) {
if (!param) continue ;
if (module_item->IsParamDecl()) {
Message::PrintLine(" param: ", param->Name()) ;
}
if (module_item->IsLocalParamDecl()) {
Message::PrintLine(" local param: ", param->Name()) ;
}
VeriExpression *initial_expr = param->GetInitialValue() ;
if (initial_expr) {
Message::PrintLine(" initial expression: ", initial_expr->GetPrettyPrintedString()) ;
VeriBaseValue *val = initial_expr->StaticEvaluate(0, 0) ;
int int_val = val ? val->GetIntegerValue() : 0 ;
Message::PrintLine(" initial value: ", Strings::itoa(int_val)) ;
}
}
}
}
return 0 ;
}
$ cat test.v
module leaf(bus);
parameter PARAMLEAF = 1;
localparam PARAMLEAFLOCAL = PARAMLEAF+PARAMLEAF-1+2;
input [PARAMLEAF-1:0] bus;
endmodule
module top();
parameter TOPP = 3;
localparam TOPL = 4;
leaf leaf1();
leaf #(.PARAMLEAF(2)) leaf2();
leaf #(.PARAMLEAF(TOPP)) leaf3();
leaf #(.PARAMLEAF(TOPL+2)) leaf6();
endmodule
$ test-linux
-- Analyzing Verilog file 'test.v' (VERI-1482)
test.v(7): INFO: compiling module 'top' (VERI-1018)
test.v(11): WARNING: port 'bus' is not connected on this instance (VERI-2435)
test.v(12): WARNING: port 'bus' is not connected on this instance (VERI-2435)
test.v(13): WARNING: port 'bus' is not connected on this instance (VERI-2435)
test.v(14): WARNING: port 'bus' is not connected on this instance (VERI-2435)
-- module: leaf
-- param: PARAMLEAF
-- initial expression: 1
-- initial value: 1
-- local param: PARAMLEAFLOCAL
-- initial expression: (((PARAMLEAF + PARAMLEAF) - 1) + 2)
-- initial value: 3
-- module: top
-- param: TOPP
-- initial expression: 3
-- initial value: 3
-- local param: TOPL
-- initial expression: 4
-- initial value: 4
-- module: leaf_default
-- param: PARAMLEAF
-- initial expression: 1
-- initial value: 1
-- local param: PARAMLEAFLOCAL
-- initial expression: (((PARAMLEAF + PARAMLEAF) - 1) + 2)
-- initial value: 3
-- module: leaf(PARAMLEAF=2)
-- param: PARAMLEAF
-- initial expression: 2
-- initial value: 2
-- local param: PARAMLEAFLOCAL
-- initial expression: (((PARAMLEAF + PARAMLEAF) - 1) + 2)
-- initial value: 5
-- module: leaf(PARAMLEAF=3)
-- param: PARAMLEAF
-- initial expression: 3
-- initial value: 3
-- local param: PARAMLEAFLOCAL
-- initial expression: (((PARAMLEAF + PARAMLEAF) - 1) + 2)
-- initial value: 7
-- module: leaf(PARAMLEAF=6)
-- param: PARAMLEAF
-- initial expression: 6
-- initial value: 6
-- local param: PARAMLEAFLOCAL
-- initial expression: (((PARAMLEAF + PARAMLEAF) - 1) + 2)
-- initial value: 13
$