Difference between revisions of "Remove Verific data structures"
From Verific Design Automation FAQ
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vhdl_file::ResetParser(); | vhdl_file::ResetParser(); | ||
− | To remove synlib | + | To remove synlib structures: |
− | synlib_file:: | + | synlib_file::Reset(); |
To remove hierarchy tree: | To remove hierarchy tree: |
Revision as of 11:43, 28 July 2016
Q: How do I remove all Verific data structures in memory?
To remove Verilog parsetree:
veri_file::ResetParser();
To remove VHDL parsetree:
vhdl_file::ResetParser();
To remove synlib structures:
synlib_file::Reset();
To remove hierarchy tree:
hier_tree::DeleteHierarchicalTree() ;
To remove UPF data structures, use:
upf_file::DeleteAll();
To remove the netlist database:
Libset::Reset();
To remove linefile data (make sure that you've removed all parsetrees and the netlist database):
LineFile::DeleteAllLineFiles(); LineFile::ResetFileIdMaps();