Static elaboration

Q: What does 'static elaboration' do?

Static elaboration runs after analysis. It modifies the parsetree. During static elaboration:

• Identify top-level modules and tree of instantiations under this.
• Defparam statements and module instantiations are processed to calculate the parameter values of the modules for every instantiation.
• Hierarchical names are checked for their validity and usage. These hierarchical names remain in designs.
• Generate statements are processed. For generate unrolled, if/case generate selects the correct concurrent statements to be present in the module.
• Instance arrays are flattened.
• Depending on hierarchical name usage and defparam values the same module gets different signatures. They are replicated and proper values are passed within them hierarchically before attaching them to the corresponding instantiations.
• In each module, parameter values are replaced with constant values by evaluating the constant expression assigned to them. Constant expressions include constant function calls, some system function calls AMS function calls and all operators.
• Function and task calls are checked for their validity (if they are defined in higher level of hierarchy and used in lower level).

Sequential code, blocking assignments, tasks and functions are left as is because they are not part of any static context. Only exception are constant function calls - they are replaced with their return values.

If the purpose of the application is to synthesize the design (RTL elaboration), static elaboration is not needed.

Runtime flag 'veri_replace_const_exprs' when set to 1 is to replace following constant expressions with literals. This takes some extra time for an extra pass on elaborated parsetree.

• Bounds of packed and unpacked ranges in all data declarations.
• Default values of all declared objects if those are constant.
• Delay values
• Reject and error limits of VeriPathPulse values.
• Indexed expressions only if the indexed expression is a bit-select on the LHS of a continuous assignment or output/inout port of module or gate instantiation.

There are other runtime flags controlling static elaboration process, e.g.

veri_cleanup_base_modules
veri_copy_top_before_static_elab
veri_do_not_uniquify_interface_instances
veri_preserve_array_instances
veri_preserve_interface_array_instances

vhdl_uniquify_all_instances
vhdl_copy_top_before_static_elab
vhdl_replace_const_exprs
...

Please see vhdl/VhdlRuntimeFlags.h and verilog/VeriRuntimeFlags.h for a complete list and for more details.