Access attributes of ports in parsetree

#!/usr/bin/perl

use strict ;

push(@INC, "../pm") ;
require "Verific.pm" ;

if (!Verific::veri_file::Read("test.v")) { exit 1 ; }

my $mod = Verific::veri_file::GetModule("test") ;
if (!$mod) { exit 2 ; }

# Attributes from parse tree port ids:
my $iter = new Verific::VeriIdDefArrayIter($mod->GetPorts()) ;
for (my $port = $iter->First(); $iter->GetIndex() < $iter->Size(); $port = $iter->Next()) {
    if (!$port) { next ; }

    print "Port: " . $port->Name() . "\n" ;
    my $map_iter = Verific::Map::Iterator($port->GetAttributes(), "char", "Verific::VeriExpression") ;
    my $map_key ;
    my $map_value ;
    while (($map_key, $map_value) = $map_iter->Next()) {
        print "\tAttribute: $map_key -> " . $map_value->GetPrettyPrintedString() . "\n" ;
    }
}

# Attributes from parse tree port declarations:
my $iter = new Verific::VeriModuleItemArrayIter($mod->GetModuleItems()) ;
for (my $mod_item = $iter->First(); $iter->GetIndex() < $iter->Size(); $mod_item = $iter->Next()) {
    if (!$mod_item || !$mod_item->IsDataDecl()) { next ; }

    print "Module item: " . $mod_item->GetPrettyPrintedString() ;
    my $map_iter = Verific::Map::Iterator($mod_item->GetAttributes(), "char", "Verific::VeriExpression") ;
    my $map_key ;
    my $map_value ;
    while (($map_key, $map_value) = $map_iter->Next()) {
        print "\tAttribute: $map_key -> " . $map_value->GetPrettyPrintedString() . "\n" ;
    }
}

# Attributes from netlist ports:
my @ports = Verific::FOREACH_PORT_OF_NETLIST(Verific::Netlist::PresentDesign()) ;
foreach my $port ( @ports ) {
    if (!$port) { next ; }

    print "Port: " . $port->Name() . "\n" ;
    my @atts = Verific::FOREACH_ATTRIBUTE($port) ;
    foreach my $att ( @atts ) {
        if (!$att) { next ; }
        print "\tAttribute: " . $att->Key() . " -> " . $att->Value() . "\n" ;
    }
}

exit 0;