Parse tree node sharing in Static Elaboration
The static elaboration process internally creates a fully instantiated hierarchy tree where each node represents a top level or instantiations of design units.
Consider the following design :
module top () ;
parameter LOOP_LIMIT = 200 ;
genvar i ;
for ( i=0; i<LOOP_LIMIT; i++) begin : in_top
mid m() ;
end
endmodule
module mid () ;
genvar i ;
for ( i=0; i<100; i++) begin : in_mid
bot #(i/10) b() ;
end
endmodule
module bot () ;
parameter P = 0 ;
reg [P:0] w1 ;
endmodule
By default static elaboration will create a hierarchy tree with 20201 nodes (1 for module 'top', 200 for 'mid', and 20000 for 'bot') for this design.
Note that if the runtime flag 'veri_alternative_generate_elab' is set, additional nodes will be created for each generate block (200 block nodes for block 'in_top' and 20000 for 'in_mid') resulting in a total of 40401 nodes created.
Static elaboration, being an iterative process, traverses this hierarchy tree multiple times to resolve hierarchical names, defparams, and bind statements. It evaluates parameters and elaborates generate constructs. This may lead to long runtimes for big designs with many modules and instantiations. Moreover a large amount of memory may be required to create this many nodes.
The runtime flag "veri_share_nodes_in_static_elab" was introduced to reduce runtime and memory for large designs. It will ensure that only one node will be created in static elaboration for each unique signature of a module (top or instantiated). So for the above design, elaboration will use only 1 node for module 'mid' as it has no parameter overwrite. However, module 'bot' will have multiple signatures like 'bot(P=1)', 'bot(P=2)' etc and so multiple nodes will be created for module 'bot'. If a design contains hierarchical names, more nodes can be created to resolve such names.
The number of nodes that can be reduced largely depends on the nature of the design, which in turn reflects on the runtime and memory improvements.
Limitation: For VHDL or mixed language designs, nodes are created for VHDL instances and top levels. However, such VHDL nodes are not shared yet under this runtime flag. It applies only to the Verilog/SystemVerilog nodes.
