How to use RegisterPragmaRefCallBack()

Here is a small example showing how to use RegisterPragmaRefCallBack():

#include <iostream>
#include "veri_file.h"
#include "vhdl_file.h"
#include "Message.h"

using namespace std ;

#ifdef VERIFIC_NAMESPACE
using namespace Verific ;
#endif

static void
pragma_ref_fn(const char *pragma_trigger, const char *pragma_name, const char *pragma_target, const char *pragma_value, const linefile_type lf)
{
    const char *eq = "= " ;
    if (!pragma_value) {
        pragma_value = "" ;
        eq = "" ;
    }
    const char *of = " of " ;
    if (!pragma_target) {
        pragma_target = "" ;
        of = "" ;
    } else {
        eq = "is " ;
    }
    Message::Msg(VERIFIC_INFO, 0, lf, "Got a pragma: %s %s%s%s %s%s", pragma_trigger, pragma_name, of, pragma_target, eq, pragma_value) ;
}

int main(int argc, char **argv)
{
    veri_file::RegisterPragmaRefCallBack(pragma_ref_fn) ;
    vhdl_file::RegisterPragmaRefCallBack(pragma_ref_fn) ;
    veri_file::Analyze("test.v") ;
    vhdl_file::Analyze("test.vhd", "work", vhdl_file::VHDL_2008) ;
    return 0 ;
}
 

test.v:

     1	module test (input a, b, output c);
     2	    assign c = a & b;
     3	// synthesis translate_off
     4	    $display ("This is not synthsizable");
     5	// synthesis translate_on
     6	endmodule
 

test.vhd:

     1	-- pragma label_applies_to
 

Run:

$ test-linux
-- Analyzing Verilog file 'test.v' (VERI-1482)
test.v(3): INFO: Got a pragma: synthesis translate_off
test.v(5): INFO: Got a pragma: synthesis translate_on
-- Analyzing VHDL file 'test.vhd' (VHDL-1481)
test.vhd(1): INFO: Got a pragma: pragma label_applies_to
$