Difference between revisions of "Access attributes of ports in parsetree"

Latest revision as of 14:10, 9 July 2020

Perl script:

#!/usr/bin/perl -w
 
use warnings ;
use strict ;
 
push(@INC, "../pm") ;
require "Verific.pm" ;
 
if (!Verific::veri_file::Analyze("test.v")) { exit 1 ; }
 
ShowAttributes(Verific::veri_file::GetModule("test1")) ;
ShowAttributes(Verific::veri_file::GetModule("test2")) ;
 
exit 0;
 
sub ShowAttributes {
    my ($mod) = @_ ;
    if (!$mod) { return ; }
 
    $mod->Info("Checking module " . $mod->Name()) ;
 
    # Attributes from parse tree port ids:
    my $iter = new Verific::VeriIdDefArrayIter($mod->GetPorts()) ;
    for (my $port = $iter->First(); $iter->GetIndex() < $iter->Size(); $port = $iter->Next()) {
        if (!$port) { next ; }
 
        print "Port: " . $port->Name() . "\n" ;
        my $map_iter = Verific::Map::Iterator($port->GetAttributes(), "char", "Verific::VeriExpression") ;
        my $map_key ;
        my $map_value ;
        while (($map_key, $map_value) = $map_iter->Next()) {
            print "\tAttribute: $map_key -> " . $map_value->GetPrettyPrintedString() . "\n" ;
        }
    }
 
    # Attributes from port declarations/expression:
    $iter = new Verific::VeriExpressionArrayIter($mod->GetPortConnects()) ;
    for (my $port_expr = $iter->First(); $iter->GetIndex() < $iter->Size(); $port_expr = $iter->Next()) {
        if (!$port_expr) { next ; }
  
        print "Port declaration: " . $port_expr->GetPrettyPrintedString() . "\n" ;
        my $map_iter = Verific::Map::Iterator($port_expr->GetAttributes(), "char", "Verific::VeriExpression") ;
        my $map_key ;
        my $map_value ;
        while (($map_key, $map_value) = $map_iter->Next()) {
            print "\tAttribute: $map_key -> " . $map_value->GetPrettyPrintedString() . "\n" ;
        }
    }
 
    # Attributes from parse tree port declarations:
    $iter = new Verific::VeriModuleItemArrayIter($mod->GetModuleItems()) ;
    for (my $mod_item = $iter->First(); $iter->GetIndex() < $iter->Size(); $mod_item = $iter->Next()) {
        if (!$mod_item || !$mod_item->IsDataDecl()) { next ; }
  
        print "Module item: " . $mod_item->GetPrettyPrintedString() ;
        my $map_iter = Verific::Map::Iterator($mod_item->GetAttributes(), "char", "Verific::VeriExpression") ;
        my $map_key ;
        my $map_value ;
        while (($map_key, $map_value) = $map_iter->Next()) {
            print "\tAttribute: $map_key -> " . $map_value->GetPrettyPrintedString() . "\n" ;
        }
    }
}
 

Verilog testcase:

module test1 (
        (* attr1 = 0, attr2 = 1 *) input in ,
        (* attr3 = 2, attr4 = 3 *) output out
    );
 
    assign out = in ;
endmodule
 
module test2 (in, out) ;
    (* attr1 = 0, attr2 = 1 *) input in ;
    (* attr3 = 2, attr4 = 3 *) output out ;
 
    assign out = in ;
endmodule
 

Run:

-- Analyzing Verilog file 'test.v' (VERI-1482)
test.v(7): INFO: Checking module test1
Port: in
Port: out
Port declaration:
(* attr1=0, attr2=1 *) input in
        Attribute: attr1 -> 0
        Attribute: attr2 -> 1
Port declaration:
(* attr3=2, attr4=3 *) output out
        Attribute: attr3 -> 2
        Attribute: attr4 -> 3
test.v(14): INFO: Checking module test2
Port: in
Port: out
Port declaration: in
Port declaration: out
Module item: (* attr1=0, attr2=1 *) input in ;
        Attribute: attr1 -> 0
        Attribute: attr2 -> 1
Module item: (* attr3=2, attr4=3 *) output out ;
        Attribute: attr3 -> 2
        Attribute: attr4 -> 3