Difference between revisions of "Black box, empty box, and unknown box"
From Verific Design Automation FAQ
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| − | In Verific Netlist Database, a Netlist can be a black box, an empty box, or an unknown box. | + | In Verific Netlist Database, a Netlist can be a black box, an empty box, or an unknown box (and of course, a "normal" box). |
# An unknown box is a Netlist that is: | # An unknown box is a Netlist that is: | ||
#* from an instantiation of an undefined Verilog module | #* from an instantiation of an undefined Verilog module | ||
Revision as of 17:44, 4 June 2020
In Verific Netlist Database, a Netlist can be a black box, an empty box, or an unknown box (and of course, a "normal" box).
- An unknown box is a Netlist that is:
- from an instantiation of an undefined Verilog module
- from an instantiation of a VHDL component without binding entity
- An black box is a Netlist that has no Instances (NumOfInsts() == 0) and no Nets ((NumOfNets() == 0). It can be:
- an unknown box
- a Verific Primitive or Operator
- a Netlist that has errors during RTL elaboration
- from VeriModule::SetCompileAsBlackbox()
- from VhdlPrimaryUnit::SetCompileAsBlackbox()
- An empty box is a Netlist that has no Instances and no port-port connections. It can be:
- a black box
- a user-defined module/entity with ports but no contents
- a user-defined module/entity that has no assignments to its outputs
See example below:
1 #include "Set.h"
2 #include "Message.h"
3 #include "Strings.h"
4 #include "veri_file.h"
5 #include "vhdl_file.h"
6 #include "VeriModule.h"
7 #include "VeriWrite.h"
8 #include "DataBase.h"
9
10 #ifdef VERIFIC_NAMESPACE
11 using namespace Verific ;
12 #endif
13
14 void Accumulate(Netlist *netlist, Set &done) ;
15
16 int main()
17 {
18 vhdl_file::SetDefaultLibraryPath("../vdbs");
19
20 if (!vhdl_file::Analyze("fromvhdl.vhd")) return 1 ;
21 if (!veri_file::Analyze("test.v", veri_file::VERILOG_2K)) return 1 ;
22
23 // blackboxing module "willbebackboxed"
24 VeriModule *tobeblackboxed = veri_file::GetModule("willbebackboxed");
25 tobeblackboxed->SetCompileAsBlackbox();
26
27 veri_file::Elaborate("top");
28
29 Netlist *top = Netlist::PresentDesign() ;
30 if (!top) {
31 Message::PrintLine("cannot find any handle to the top-level netlist") ;
32 return 1 ;
33 }
34
35 Message::Msg(VERIFIC_INFO, 0, top->Linefile(), "top level design is %s(%s)",
36 top->Owner()->Name(), top->Name()) ;
37
38 // Lets accumulate all netlist
39 Set netlists(POINTER_HASH) ;
40 Accumulate(top, netlists) ;
41
42 // For each netlist, print out its data
43 Netlist *netlist ;
44 SetIter si ;
45 FOREACH_SET_ITEM(&netlists, si, &netlist) {
46 Message::Msg(VERIFIC_INFO, 0, 0, "*** netlist of cell %s", netlist->Owner()->Name()) ;
47 if (netlist->IsPrimitive() || netlist->IsOperator()) {
48 Message::Msg(VERIFIC_INFO, 0, 0, " a primitive/operator");
49 }
50 const Att *attr = netlist->GetAtt(" unknown_design"); // note the leading space character
51 if (attr) {
52 if (Strings::compare (attr->Value(),"1")) {
53 Message::Msg(VERIFIC_INFO, 0, 0, " an unknown box instantiated in a Verilog module");
54 }
55 else if (Strings::compare (attr->Value(),"2")) {
56 Message::Msg(VERIFIC_INFO, 0, 0, " an unknown box instantiated in a VHDL architecture");
57 }
58 }
59 if (netlist->IsBlackBox()) {
60 Message::Msg(VERIFIC_INFO, 0, 0, " a black box");
61 }
62 if (netlist->IsEmptyBox()) {
63 Message::Msg(VERIFIC_INFO, 0, 0, " an empty box");
64 }
65
66 }
67 VeriWrite veriWriter;
68 veriWriter.WriteFile("netlistout.v", top) ;
69
70 return 0 ;
71 }
72
73 // This function is recursive in nature, and collects all other
74 // netlists that the incoming netlist depends on in a container.
75
76 void Accumulate(Netlist *netlist, Set &done)
77 {
78 if (!netlist) return ; // Ignore NULL netlists
79
80 SetItem *item = done.GetItem(netlist) ;
81 if (item) {
82 return ; // We've already been here
83 }
84
85 Instance *inst ;
86 MapIter mi ;
87 FOREACH_INSTANCE_OF_NETLIST(netlist, mi, inst) {
88 // Now go into the netlist associated with the instance
89 Accumulate(inst->View(), done) ;
90 }
91
92 done.Insert(netlist) ;
93 }
test.v
module nocontents (input a, output o);
endmodule
module willbebackboxed (input a, b, output o);
assign o = a ^ b;
endmodule
module containserror (input a, b, output o);
assign o = a & b;
assign o = a | b;
endmodule
module emptybox (input a, output o); // no outputs are driven
wire i = a;
endmodule
module normal (input a, b, output o);
assign o = a & b;
endmodule
module top (input i1, i2, i3, i4, i5, i6, i7, i8, i9, ia, ib,
output o1, o2, o3, o4, o5);
nocontents u_nocontents (i1, o1);
willbebackboxed u_willbebackboxed (i2, i3, o2);
containserror u_containserror (i4, i5, o3);
emptybox u_emptybox (i9, );
unknownverilog u_unknownverilog (i6, o4);
normal u_normal (i7, i8, o5);
fromvhdl u_fromvhdl (ia, ib, o6);
endmodule
fromvhdl.vhd:
library std;
use std.all;
entity fromvhdl is
port ( a, b: in bit; o: out bit );
end entity;
architecture test of fromvhdl is
component unknownvhdl
port ( a, b : in bit; o : out bit);
end component;
begin
u_unknownvhdl: unknownvhdl port map (a, b, o);
end architecture;
Run:
$ test-linux INFO: The default VHDL library search path is now "/mnt/Verific/extra_tests/vdbs" (VHDL-1504) -- Analyzing VHDL file 'fromvhdl.vhd' (VHDL-1481) -- Restoring VHDL parse-tree 'std.standard' from '/mnt/Verific/extra_tests/vdbs/std/standard.vdb' (VHDL-1493) fromvhdl.vhd(3): INFO: analyzing entity 'fromvhdl' (VHDL-1012) fromvhdl.vhd(6): INFO: analyzing architecture 'test' (VHDL-1010) -- Analyzing Verilog file 'test.v' (VERI-1482) test.v(21): INFO: compiling module 'top' (VERI-1018) test.v(1): INFO: compiling module 'nocontents' (VERI-1018) test.v(4): INFO: compiling module 'willbebackboxed' (VERI-1018) test.v(8): INFO: compiling module 'containserror' (VERI-1018) test.v(9): ERROR: net 'o' is constantly driven from multiple places (VDB-1000) test.v(10): ERROR: another driver from here (VDB-1001) test.v(8): INFO: module 'containserror' remains a black box, due to errors in its contents (VERI-1073) test.v(13): INFO: compiling module 'emptybox' (VERI-1018) test.v(27): WARNING: instantiating unknown module 'unknownverilog' (VERI-1063) test.v(17): INFO: compiling module 'normal' (VERI-1018) test.v(29): INFO: going to VHDL side to elaborate design unit 'fromvhdl' (VERI-1231) fromvhdl.vhd(3): INFO: executing 'fromvhdl(test)' (VHDL-1067) fromvhdl.vhd(9): WARNING: 'unknownvhdl' remains a black box since it has no binding entity (VHDL-1250) test.v(29): INFO: back to Verilog to continue elaboration (VERI-1232) test.v(21): INFO: top level design is top() INFO: *** netlist of cell nocontents INFO: an empty box INFO: *** netlist of cell willbebackboxed INFO: a black box INFO: an empty box INFO: *** netlist of cell containserror INFO: a black box INFO: an empty box INFO: *** netlist of cell emptybox INFO: an empty box INFO: *** netlist of cell unknownverilog INFO: an unknown box instantiated in a Verilog module INFO: a black box INFO: an empty box INFO: *** netlist of cell VERIFIC_AND INFO: a primitive/operator INFO: a black box INFO: an empty box INFO: *** netlist of cell normal INFO: *** netlist of cell unknownvhdl INFO: an unknown box instantiated in a VHDL architecture INFO: a black box INFO: an empty box INFO: *** netlist of cell fromvhdl INFO: *** netlist of cell top -- Writing netlist 'top' to Verilog file 'netlistout.v' (VDB-1030) $
