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Comment out a line using text based design modification and parsetree modification - Revision history
2024-03-28T21:32:08Z
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Hoa: Created page with "C++: <nowiki> #include <iostream> #include "veri_file.h" #include "VeriModule.h" #include "VeriStatement.h" #include "Array.h" #include "Strings.h" #include "TextBasedDes..."
2021-04-08T21:17:06Z
<p>Created page with "C++: <nowiki> #include <iostream> #include "veri_file.h" #include "VeriModule.h" #include "VeriStatement.h" #include "Array.h" #include "Strings.h" #include "TextBasedDes..."</p>
<p><b>New page</b></p><div>C++:<br />
<nowiki><br />
#include <iostream><br />
<br />
#include "veri_file.h"<br />
<br />
#include "VeriModule.h"<br />
#include "VeriStatement.h"<br />
<br />
#include "Array.h"<br />
<br />
#include "Strings.h"<br />
#include "TextBasedDesignMod.h"<br />
<br />
#ifdef VERIFIC_NAMESPACE<br />
using namespace Verific ;<br />
#endif<br />
<br />
void CommentStmtInParseTree(VeriModule *mod)<br />
{<br />
if (!mod) return ;<br />
<br />
Array *mod_items = mod->GetModuleItems() ;<br />
unsigned i ;<br />
VeriModuleItem *item ;<br />
FOREACH_ARRAY_ITEM(mod_items, i, item) {<br />
if (!item) continue ;<br />
// Get statement from the module item (initial block)<br />
VeriStatement *stmt = item->GetStmt() ;<br />
if (!stmt) continue ;<br />
// Get all statements from the statement (squential block in initial block)<br />
Array *stmts = stmt->GetStatements() ;<br />
if (stmts) {<br />
unsigned j ;<br />
VeriStatement *child ;<br />
// Iterate over the child statement:<br />
FOREACH_ARRAY_ITEM(stmts, j, child) {<br />
if (!child) continue ;<br />
// Get the string of the statement:<br />
char *tmp = child->GetPrettyPrintedString() ;<br />
// Remove the last new-line:<br />
unsigned len = Strings::len(tmp) ;<br />
if (!tmp || !len) continue ;<br />
if (tmp[len-1] == '\n') tmp[len-1] = '\0' ;<br />
// Comment out the string:<br />
char *str = Strings::save("/* ", tmp, " */") ;<br />
Strings::free(tmp) ;<br />
// Create a null statement:<br />
VeriStatement *new_stmt = new VeriNullStatement() ;<br />
new_stmt->SetLinefile(child->Linefile()) ;<br />
// Create a comment node with the comment string:<br />
VeriCommentNode *comment = new VeriCommentNode(child->Linefile()) ;<br />
comment->AppendComment(str) ;<br />
Strings::free(str) ;<br />
// Add the comment on the null-statement:<br />
Array *comments = new Array(1) ;<br />
comments->InsertLast(comment) ;<br />
new_stmt->AddComments(comments) ;<br />
// Finally replace the original statement with the created null-statement:<br />
if (!stmt->ReplaceChildStmt(child, new_stmt, 1 /* delete old stmt */)) delete new_stmt ;<br />
}<br />
} else {<br />
// Get the string of the statement:<br />
char *tmp = stmt->GetPrettyPrintedString() ;<br />
// Remove the last new-line:<br />
unsigned len = Strings::len(tmp) ;<br />
if (!tmp || !len) continue ;<br />
if (tmp[len-1] == '\n') tmp[len-1] = '\0' ;<br />
// Comment out the string:<br />
char *str = Strings::save("/* ", tmp, " */") ;<br />
Strings::free(tmp) ;<br />
// Create a null statement:<br />
VeriStatement *new_stmt = new VeriNullStatement() ;<br />
new_stmt->SetLinefile(stmt->Linefile()) ;<br />
// Create a comment node with the comment string:<br />
VeriCommentNode *comment = new VeriCommentNode(stmt->Linefile()) ;<br />
comment->AppendComment(str) ;<br />
Strings::free(str) ;<br />
// Add the comment on the null-statement:<br />
Array *comments = new Array(1) ;<br />
comments->InsertLast(comment) ;<br />
new_stmt->AddComments(comments) ;<br />
// Finally replace the original statement with the created null-statement:<br />
if (!item->ReplaceChildStmt(stmt, new_stmt, 1 /* delete old stmt */)) delete new_stmt ;<br />
}<br />
}<br />
<br />
veri_file::PrettyPrint("test_pp.v.golden.new", 0) ;<br />
}<br />
<br />
void CommentStmtViaTBDM(VeriModule *mod, TextBasedDesignMod &tbdm)<br />
{<br />
if (!mod) return ;<br />
<br />
Array *mod_items = mod->GetModuleItems() ;<br />
unsigned i ;<br />
VeriModuleItem *item ;<br />
FOREACH_ARRAY_ITEM(mod_items, i, item) {<br />
if (!item) continue ;<br />
// Get statement from the module item (initial block)<br />
VeriStatement *stmt = item->GetStmt() ;<br />
if (!stmt) continue ;<br />
// Get all statements from the statement (squential block in initial block)<br />
Array *stmts = stmt->GetStatements() ;<br />
if (stmts) {<br />
unsigned j ;<br />
VeriStatement *child ;<br />
// Iterate over the child statement:<br />
FOREACH_ARRAY_ITEM(stmts, j, child) {<br />
if (!child) continue ;<br />
// Comment the whole statement:<br />
tbdm.InsertBefore(child->Linefile(), "; /* ") ;<br />
tbdm.InsertAfter(child->Linefile(), " */") ;<br />
}<br />
} else {<br />
// Comment the whole statement:<br />
tbdm.InsertBefore(stmt->Linefile(), "; /* ") ;<br />
tbdm.InsertAfter(stmt->Linefile(), " */") ;<br />
}<br />
}<br />
}<br />
<br />
int main()<br />
{<br />
if (!veri_file::Analyze("test.v")) return 1 ;<br />
<br />
VeriModule *mod = veri_file::GetModule("test") ;<br />
if (!mod) return 2 ;<br />
<br />
CommentStmtInParseTree(mod) ;<br />
<br />
TextBasedDesignMod tbdm(0) ;<br />
CommentStmtViaTBDM(mod, tbdm) ;<br />
tbdm.WriteFile("test.v", "test_out.v.golden.new") ;<br />
<br />
return 0 ;<br />
}<br />
</nowiki><br />
<br />
Input Verilog:<br />
<nowiki><br />
module test ;<br />
reg A, b ;<br />
initial<br />
A = b ;<br />
initial<br />
begin<br />
A = b ;<br />
end<br />
endmodule<br />
</nowiki><br />
<br />
Output Verilog:<br />
<br />
<nowiki><br />
module test ;<br />
reg A, b ;<br />
initial<br />
; /* A = b ; */<br />
initial<br />
begin<br />
; /* A = b ; */<br />
end<br />
endmodule<br />
</nowiki></div>
Hoa