View source for Create a Netlist Database from scratch (not from RTL elaboration)

Perl script:
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#!/usr/bin/perl
use strict;

push (@INC,"../../../extra_tests/pm");
require "Verific.pm";

# The global Libset is already at the top of the netlist database.
# No need to create, just get a handle to it.
my $libset = Verific::Libset::Global();

# Add new library.  If RTL elaboration has been run, a library has been created
# already.  The default library is "work".
my $lib = Verific::Library->new("mylib");
$libset->Add($lib);

# Add cell to the library.  In the Verilog netlist output, the cell name is the
# same as the module name.
my $cell = Verific::Cell->new("mycell");
$lib->Add($cell);

# Add netlist to cell.  In the Verilog netlist output, the netlist name doesn't matter.
my $netlist = Verific::Netlist->new("mynetlist");
$cell->Add($netlist);

# Add ports to netlist
my $inport = Verific::Port->new("in", $Verific::DIR_IN);
$netlist->Add($inport);
my $outport = Verific::Port->new("out", $Verific::DIR_OUT);
$netlist->Add($outport);

# Add nets (Verilog: wire) to netlist
my $net1 = Verific::Net->new("in");
$netlist->Add($net1);
$net1->Connect($inport);

my $net2 = Verific::Net->new("out");
$netlist->Add($net2);
$net2->Connect($outport);

my $net3 = Verific::Net->new("n1");
$netlist->Add($net3);

# Add new library
my $primlib = Verific::Library->new("myprimitives");
$libset->Add($primlib);
# Create primitive inv
my $invcell = Verific::Cell->new("inv");
$primlib->Add($invcell);
my $invnetlist = Verific::Netlist->new("primitive");
$invcell->Add($invnetlist);
my $Ainport = Verific::Port->new("A", $Verific::DIR_IN);
$invnetlist->Add($Ainport);
my $Zoutport = Verific::Port->new("Z", $Verific::DIR_OUT);
$invnetlist->Add($Zoutport);
# Create primitive buff
my $buffcell = Verific::Cell->new("buff");
$primlib->Add($buffcell);
my $buffnetlist = Verific::Netlist->new("primitive");
$buffcell->Add($buffnetlist);
$Ainport = Verific::Port->new("A", $Verific::DIR_IN);
$buffnetlist->Add($Ainport);
$Zoutport = Verific::Port->new("Z", $Verific::DIR_OUT);
$buffnetlist->Add($Zoutport);

# Instantiate inv in mynetlist
my $inst = $netlist->Add(Verific::Instance->new("inv1", $invnetlist));
if ($inst) {
    my $port = $invnetlist->GetPort("A");
    if ($port) {$net1->Connect($inst, $port);}
    $port = $invnetlist->GetPort("Z");
    if ($port) {$net3->Connect($inst, $port);}
}

# Instantiate buff in mynetlist
$inst = $netlist->Add(Verific::Instance->new("buff2", $buffnetlist));
if ($inst) {
    my $port = $buffnetlist->GetPort("A");
    if ($port) {$net3->Connect($inst, $port);}
    $port = $buffnetlist->GetPort("Z");
    if ($port) {$net2->Connect($inst, $port);}
}

# write netlist
my $veriWriter = Verific::VeriWrite->new();
$veriWriter->WriteFile(sprintf("%s.v",$netlist->Owner->Name()), $netlist);

exit(1);

# moved this to a subroutine to keep above code clean,
# this subroutine shows how to resolve linefile information
sub vfcprintf {
   my ($format) = (@_[0]);
   my ($lf) = (@_[1]);
   my @PARAMS;
   for (my $i = 2; $i < scalar(@_); $i++) {
       push(@PARAMS,"@_[$i]");
   }   
   my $lf_format = ""; 
   if (Verific::LineFile::GetFileName($lf) && Verific::LineFile::GetLineNo($lf)) {
       my $lf_format = sprintf("%s(%s)",Verific::LineFile::GetFileName($lf), Verific::LineFile::GetLineNo($lf));
       printf "%s: $format\n",$lf_format,@PARAMS;
   } else {
       printf "$format\n",@PARAMS;
   }   

   return 0;
}
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Equivalent TCL script:
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# The global Libset is already at the top of the netlist database.
# No need to create, just get a handle to it.
set libset [Libset_Global];

# Add new library.  If RTL elaboration has been run, a library has been created
# already.  The default library is "work".
set lib [new_Library "mylib"];
Libset_Add $libset $lib;

# Add cell to the library.  In the Verilog netlist output, the cell name is the
# same as the module name.
set cell [new_Cell "newcell"];
Library_Add $lib $cell;

# Add netlist to cell.  In the Verilog netlist output, the netlist name doesn't matter.
set netlist [new_Netlist "mynetlist"];
Cell_Add $cell $netlist;

# Set the new netlist as present design
Netlist_SetPresentDesign $netlist;

# Add ports to netlist
set inport [new_Port "in" $DIR_IN];
Netlist_Add $netlist $inport;
set outport [new_Port "out" $DIR_OUT];
Netlist_Add $netlist $outport;

# Add nets (Verilog: wire) to netlist
set net1 [new_Net "in"];
Netlist_Add $netlist $net1;
Net_Connect $net1 $inport;

set net2 [new_Net "out"];
Netlist_Add $netlist $net2;
Net_Connect $net2 $outport;

set net3 [new_Net "n1"];
Netlist_Add $netlist $net3;

# Add new library
set primlib [new_Library "myprimitives"];
Libset_Add $libset $primlib;

# Create primitive inv
set invcell [new_Cell "inv"];
Library_Add $primlib $invcell;
set invnetlist [new_Netlist "primitive"]
Cell_Add $invcell $invnetlist;
set Ainport [new_Port "A" $DIR_IN];
Netlist_Add $invnetlist $Ainport
set Zinport [new_Port "Z" $DIR_OUT];
Netlist_Add $invnetlist $Zinport

# Create primitive buff
set buffcell [new_Cell "buff"];
Library_Add $primlib $buffcell;
set buffnetlist [new_Netlist "primitive"];
Cell_Add $buffcell $buffnetlist
set Ainport [new_Port "A" $DIR_IN];
Netlist_Add $buffnetlist $Ainport
set Zinport [new_Port "Z" $DIR_OUT];
Netlist_Add $buffnetlist $Zinport

# Instantiate inv in mynetlist
set inst [Netlist_Add $netlist [new_Instance "inv1" $invnetlist]];
if {$inst!=0} {
    set port [Netlist_GetPort $invnetlist "A"];
    if {$port!=0} {Net_Connect $net1 $inst $port};
    set port [Netlist_GetPort $invnetlist "Z"];
    if {$port!=0} {Net_Connect $net3 $inst $port};
}

# Instantiate buff in mynetlist
set inst [Netlist_Add $netlist [new_Instance "buff2" $buffnetlist]];
if {$inst!=0} {
    set port [Netlist_GetPort $buffnetlist "A"];
    if {$port!=0} {Net_Connect $net3 $inst $port};
    set port [Netlist_GetPort $buffnetlist "Z"];
    if {$port!=0} {Net_Connect $net2 $inst $port};
}

# Write output netlist
set cellname [DesignObj_Name [Netlist_Owner $netlist]];
set outfilename [append cellname ".v"];
write -format verilog $outfilename;

exit;
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Equivalent Python script:
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#!/usr/bin/python

import sys
sys.path.append('../py')

import Verific

# The global Libset is already at the top of the netlist database.
# No need to create, just get a handle to it.
libset = Verific.Libset_Global()

# Add library.  If RTL elaboration has been run, a library has been created
# already.  The default library is "work".
lib = Verific.Library("mylib")
lib.thisown = 0
libset.Add(lib)

# Add cell to the library.  In the Verilog netlist output, the cell name is the
# same as the module name.
cell = Verific.Cell("mycell")
cell.thisown = 0
lib.Add(cell)

# Add netlist to cell.  In the Verilog netlist output, the netlist name doesn't matter.
netlist = Verific.Netlist("mynetlist")
netlist.thisown = 0
cell.Add(netlist)

# Add ports to netlist
inport = Verific.Port("in", Verific.DIR_IN)
inport.thisown = 0
netlist.Add(inport)
outport = Verific.Port("out", Verific.DIR_OUT)
outport.thisown = 0
netlist.Add(outport)

# Add nets (Verilog: wire) to netlist
net1 = Verific.Net("in")
net1.thisown = 0
netlist.Add(net1)
net1.Connect(inport)

net2 = Verific.Net("out")
net2.thisown = 0
netlist.Add(net2)
net2.Connect(outport)

net3 = Verific.Net("n1")
net3.thisown = 0
netlist.Add(net3)

# Add library
primlib = Verific.Library("myprimitives")
primlib.thisown = 0
libset.Add(primlib)

# Create primitive inv
invcell = Verific.Cell("inv")
invcell.thisown = 0
primlib.Add(invcell)
invnetlist = Verific.Netlist("primitive")
invnetlist.thisown = 0
invcell.Add(invnetlist)
Ainport = Verific.Port("A", Verific.DIR_IN)
Ainport.thisown = 0
invnetlist.Add(Ainport)
Zoutport = Verific.Port("Z", Verific.DIR_OUT)
Zoutport.thisown = 0
invnetlist.Add(Zoutport)

# Create primitive buff
buffcell = Verific.Cell("buff")
buffcell.thisown = 0
primlib.Add(buffcell)
buffnetlist = Verific.Netlist("primitive")
buffnetlist.thisown = 0
buffcell.Add(buffnetlist)
Ainport = Verific.Port("A", Verific.DIR_IN)
Ainport.thisown = 0
buffnetlist.Add(Ainport)
Zoutport = Verific.Port("Z", Verific.DIR_OUT)
Zoutport.thisown = 0
buffnetlist.Add(Zoutport)

# Instantiate inv in mynetlist
inst = Verific.Instance("inv1", invnetlist)
inst.thisown = 0
netlist.Add(inst)
if (inst) :
    port = invnetlist.GetPort("A")
    if (port) :
        net1.Connect(inst, port)
    port = invnetlist.GetPort("Z")
    if (port) :
        net3.Connect(inst, port)

# Instantiate buff in mynetlist
inst = Verific.Instance("buff2", buffnetlist)
inst.thisown = 0
netlist.Add(inst)
if (inst) :
    port = buffnetlist.GetPort("A")
    if (port) :
        net3.Connect(inst, port)
    port = buffnetlist.GetPort("Z")
    if (port) :
        net2.Connect(inst, port)

# write netlist
veriWriter = Verific.VeriWrite()
veriWriter.thisown = 0
veriWriter.WriteFile(netlist.Owner().Name()+".v", netlist)

sys.exit(0)
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Output netlist:
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//
// Verific Verilog Description of module newcell
//

module newcell (in, out);
    input in;
    output out;


    wire n1;

    inv inv1 (in, n1);
    buff buff2 (n1, out);

endmodule

//
// Verific Verilog Description of module inv
//

module inv (A, Z);
    input A;
    output Z;



endmodule

//
// Verific Verilog Description of module buff
//

module buff (A, Z);
    input A;
    output Z;



endmodule
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