Difference between revisions of "Create a Netlist Database from scratch (not from RTL elaboration)"
From Verific Design Automation FAQ
(Created page with " <nowiki> #!/usr/bin/perl use strict; push (@INC,"../../../extra_tests/pm"); require "Verific.pm"; # The global Libset is already at the top of the netlist database. # No ne...") |
|||
Line 1: | Line 1: | ||
+ | Perl script: | ||
<nowiki> | <nowiki> | ||
#!/usr/bin/perl | #!/usr/bin/perl | ||
Line 107: | Line 108: | ||
return 0; | return 0; | ||
} | } | ||
+ | </nowiki> | ||
+ | Equivalent TCL script: | ||
+ | <nowiki> | ||
+ | # The global Libset is already at the top of the netlist database. | ||
+ | # No need to create, just get a handle to it. | ||
+ | set libset [Libset_Global]; | ||
+ | |||
+ | # Add new library. If RTL elaboration has been run, a library has been created | ||
+ | # already. The default library is "work". | ||
+ | set lib [new_Library "mylib"]; | ||
+ | Libset_Add $libset $lib; | ||
+ | |||
+ | # Add cell to the library. In the Verilog netlist output, the cell name is the | ||
+ | # same as the module name. | ||
+ | set cell [new_Cell "newcell"]; | ||
+ | Library_Add $lib $cell; | ||
+ | |||
+ | # Add netlist to cell. In the Verilog netlist output, the netlist name doesn't matter. | ||
+ | set netlist [new_Netlist "mynetlist"]; | ||
+ | Cell_Add $cell $netlist; | ||
+ | |||
+ | # Set the new netlist as present design | ||
+ | Netlist_SetPresentDesign $netlist; | ||
+ | |||
+ | # Add ports to netlist | ||
+ | set inport [new_Port "in" $DIR_IN]; | ||
+ | Netlist_Add $netlist $inport; | ||
+ | set outport [new_Port "out" $DIR_OUT]; | ||
+ | Netlist_Add $netlist $outport; | ||
+ | |||
+ | # Add nets (Verilog: wire) to netlist | ||
+ | set net1 [new_Net "in"]; | ||
+ | Netlist_Add $netlist $net1; | ||
+ | Net_Connect $net1 $inport; | ||
+ | |||
+ | set net2 [new_Net "out"]; | ||
+ | Netlist_Add $netlist $net2; | ||
+ | Net_Connect $net2 $outport; | ||
+ | |||
+ | set net3 [new_Net "n1"]; | ||
+ | Netlist_Add $netlist $net3; | ||
+ | |||
+ | # Add new library | ||
+ | set primlib [new_Library "myprimitives"]; | ||
+ | Libset_Add $libset $primlib; | ||
+ | |||
+ | # Create primitive inv | ||
+ | set invcell [new_Cell "inv"]; | ||
+ | Library_Add $primlib $invcell; | ||
+ | set invnetlist [new_Netlist "primitive"] | ||
+ | Cell_Add $invcell $invnetlist; | ||
+ | set Ainport [new_Port "A" $DIR_IN]; | ||
+ | Netlist_Add $invnetlist $Ainport | ||
+ | set Zinport [new_Port "Z" $DIR_OUT]; | ||
+ | Netlist_Add $invnetlist $Zinport | ||
+ | |||
+ | # Create primitive buff | ||
+ | set buffcell [new_Cell "buff"]; | ||
+ | Library_Add $primlib $buffcell; | ||
+ | set buffnetlist [new_Netlist "primitive"]; | ||
+ | Cell_Add $buffcell $buffnetlist | ||
+ | set Ainport [new_Port "A" $DIR_IN]; | ||
+ | Netlist_Add $buffnetlist $Ainport | ||
+ | set Zinport [new_Port "Z" $DIR_OUT]; | ||
+ | Netlist_Add $buffnetlist $Zinport | ||
+ | |||
+ | # Instantiate inv in mynetlist | ||
+ | set inst [Netlist_Add $netlist [new_Instance "inv1" $invnetlist]]; | ||
+ | if {$inst!=0} { | ||
+ | set port [Netlist_GetPort $invnetlist "A"]; | ||
+ | if {$port!=0} {Net_Connect $net1 $inst $port}; | ||
+ | set port [Netlist_GetPort $invnetlist "Z"]; | ||
+ | if {$port!=0} {Net_Connect $net3 $inst $port}; | ||
+ | } | ||
+ | |||
+ | # Instantiate buff in mynetlist | ||
+ | set inst [Netlist_Add $netlist [new_Instance "buff2" $buffnetlist]]; | ||
+ | if {$inst!=0} { | ||
+ | set port [Netlist_GetPort $buffnetlist "A"]; | ||
+ | if {$port!=0} {Net_Connect $net3 $inst $port}; | ||
+ | set port [Netlist_GetPort $buffnetlist "Z"]; | ||
+ | if {$port!=0} {Net_Connect $net2 $inst $port}; | ||
+ | } | ||
+ | |||
+ | # Write output netlist | ||
+ | set cellname [DesignObj_Name [Netlist_Owner $netlist]]; | ||
+ | set outfilename [append cellname ".v"]; | ||
+ | write -format verilog $outfilename; | ||
+ | |||
+ | exit; | ||
+ | </nowiki> | ||
+ | Output netlist: | ||
+ | <nowiki> | ||
+ | // | ||
+ | // Verific Verilog Description of module newcell | ||
+ | // | ||
+ | |||
+ | module newcell (in, out); | ||
+ | input in; | ||
+ | output out; | ||
+ | |||
+ | |||
+ | wire n1; | ||
+ | |||
+ | inv inv1 (in, n1); | ||
+ | buff buff2 (n1, out); | ||
+ | |||
+ | endmodule | ||
+ | |||
+ | // | ||
+ | // Verific Verilog Description of module inv | ||
+ | // | ||
+ | |||
+ | module inv (A, Z); | ||
+ | input A; | ||
+ | output Z; | ||
+ | |||
+ | |||
+ | |||
+ | endmodule | ||
+ | |||
+ | // | ||
+ | // Verific Verilog Description of module buff | ||
+ | // | ||
+ | |||
+ | module buff (A, Z); | ||
+ | input A; | ||
+ | output Z; | ||
+ | |||
+ | |||
+ | |||
+ | endmodule | ||
</nowiki> | </nowiki> |
Revision as of 18:02, 5 June 2020
Perl script:
#!/usr/bin/perl use strict; push (@INC,"../../../extra_tests/pm"); require "Verific.pm"; # The global Libset is already at the top of the netlist database. # No need to create, just get a handle to it. my $libset = Verific::Libset::Global(); # Add new library. If RTL elaboration has been run, a library has been created # already. The default library is "work". my $lib = Verific::Library->new("mylib"); $libset->Add($lib); # Add cell to the library. In the Verilog netlist output, the cell name is the # same as the module name. my $cell = Verific::Cell->new("mycell"); $lib->Add($cell); # Add netlist to cell. In the Verilog netlist output, the netlist name doesn't matter. my $netlist = Verific::Netlist->new("mynetlist"); $cell->Add($netlist); # Add ports to netlist my $inport = Verific::Port->new("in", $Verific::DIR_IN); $netlist->Add($inport); my $outport = Verific::Port->new("out", $Verific::DIR_OUT); $netlist->Add($outport); # Add nets (Verilog: wire) to netlist my $net1 = Verific::Net->new("in"); $netlist->Add($net1); $net1->Connect($inport); my $net2 = Verific::Net->new("out"); $netlist->Add($net2); $net2->Connect($outport); my $net3 = Verific::Net->new("n1"); $netlist->Add($net3); # Add new library my $primlib = Verific::Library->new("myprimitives"); $libset->Add($primlib); # Create primitive inv my $invcell = Verific::Cell->new("inv"); $primlib->Add($invcell); my $invnetlist = Verific::Netlist->new("primitive"); $invcell->Add($invnetlist); my $Ainport = Verific::Port->new("A", $Verific::DIR_IN); $invnetlist->Add($Ainport); my $Zoutport = Verific::Port->new("Z", $Verific::DIR_OUT); $invnetlist->Add($Zoutport); # Create primitive buff my $buffcell = Verific::Cell->new("buff"); $primlib->Add($buffcell); my $buffnetlist = Verific::Netlist->new("primitive"); $buffcell->Add($buffnetlist); $Ainport = Verific::Port->new("A", $Verific::DIR_IN); $buffnetlist->Add($Ainport); $Zoutport = Verific::Port->new("Z", $Verific::DIR_OUT); $buffnetlist->Add($Zoutport); # Instantiate inv in mynetlist my $inst = $netlist->Add(Verific::Instance->new("inv1", $invnetlist)); if ($inst) { my $port = $invnetlist->GetPort("A"); if ($port) {$net1->Connect($inst, $port);} $port = $invnetlist->GetPort("Z"); if ($port) {$net3->Connect($inst, $port);} } # Instantiate buff in mynetlist $inst = $netlist->Add(Verific::Instance->new("buff2", $buffnetlist)); if ($inst) { my $port = $buffnetlist->GetPort("A"); if ($port) {$net3->Connect($inst, $port);} $port = $buffnetlist->GetPort("Z"); if ($port) {$net2->Connect($inst, $port);} } # write netlist my $veriWriter = Verific::VeriWrite->new(); $veriWriter->WriteFile(sprintf("%s.v",$netlist->Owner->Name()), $netlist); exit(1); # moved this to a subroutine to keep above code clean, # this subroutine shows how to resolve linefile information sub vfcprintf { my ($format) = (@_[0]); my ($lf) = (@_[1]); my @PARAMS; for (my $i = 2; $i < scalar(@_); $i++) { push(@PARAMS,"@_[$i]"); } my $lf_format = ""; if (Verific::LineFile::GetFileName($lf) && Verific::LineFile::GetLineNo($lf)) { my $lf_format = sprintf("%s(%s)",Verific::LineFile::GetFileName($lf), Verific::LineFile::GetLineNo($lf)); printf "%s: $format\n",$lf_format,@PARAMS; } else { printf "$format\n",@PARAMS; } return 0; }
Equivalent TCL script:
# The global Libset is already at the top of the netlist database. # No need to create, just get a handle to it. set libset [Libset_Global]; # Add new library. If RTL elaboration has been run, a library has been created # already. The default library is "work". set lib [new_Library "mylib"]; Libset_Add $libset $lib; # Add cell to the library. In the Verilog netlist output, the cell name is the # same as the module name. set cell [new_Cell "newcell"]; Library_Add $lib $cell; # Add netlist to cell. In the Verilog netlist output, the netlist name doesn't matter. set netlist [new_Netlist "mynetlist"]; Cell_Add $cell $netlist; # Set the new netlist as present design Netlist_SetPresentDesign $netlist; # Add ports to netlist set inport [new_Port "in" $DIR_IN]; Netlist_Add $netlist $inport; set outport [new_Port "out" $DIR_OUT]; Netlist_Add $netlist $outport; # Add nets (Verilog: wire) to netlist set net1 [new_Net "in"]; Netlist_Add $netlist $net1; Net_Connect $net1 $inport; set net2 [new_Net "out"]; Netlist_Add $netlist $net2; Net_Connect $net2 $outport; set net3 [new_Net "n1"]; Netlist_Add $netlist $net3; # Add new library set primlib [new_Library "myprimitives"]; Libset_Add $libset $primlib; # Create primitive inv set invcell [new_Cell "inv"]; Library_Add $primlib $invcell; set invnetlist [new_Netlist "primitive"] Cell_Add $invcell $invnetlist; set Ainport [new_Port "A" $DIR_IN]; Netlist_Add $invnetlist $Ainport set Zinport [new_Port "Z" $DIR_OUT]; Netlist_Add $invnetlist $Zinport # Create primitive buff set buffcell [new_Cell "buff"]; Library_Add $primlib $buffcell; set buffnetlist [new_Netlist "primitive"]; Cell_Add $buffcell $buffnetlist set Ainport [new_Port "A" $DIR_IN]; Netlist_Add $buffnetlist $Ainport set Zinport [new_Port "Z" $DIR_OUT]; Netlist_Add $buffnetlist $Zinport # Instantiate inv in mynetlist set inst [Netlist_Add $netlist [new_Instance "inv1" $invnetlist]]; if {$inst!=0} { set port [Netlist_GetPort $invnetlist "A"]; if {$port!=0} {Net_Connect $net1 $inst $port}; set port [Netlist_GetPort $invnetlist "Z"]; if {$port!=0} {Net_Connect $net3 $inst $port}; } # Instantiate buff in mynetlist set inst [Netlist_Add $netlist [new_Instance "buff2" $buffnetlist]]; if {$inst!=0} { set port [Netlist_GetPort $buffnetlist "A"]; if {$port!=0} {Net_Connect $net3 $inst $port}; set port [Netlist_GetPort $buffnetlist "Z"]; if {$port!=0} {Net_Connect $net2 $inst $port}; } # Write output netlist set cellname [DesignObj_Name [Netlist_Owner $netlist]]; set outfilename [append cellname ".v"]; write -format verilog $outfilename; exit;
Output netlist:
// // Verific Verilog Description of module newcell // module newcell (in, out); input in; output out; wire n1; inv inv1 (in, n1); buff buff2 (n1, out); endmodule // // Verific Verilog Description of module inv // module inv (A, Z); input A; output Z; endmodule // // Verific Verilog Description of module buff // module buff (A, Z); input A; output Z; endmodule