Revision history of "Defined macros become undefined - MFCU vs SFCU"

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  • (cur | prev) 17:27, 28 December 2018Hoa (Talk | contribs). . (1,706 bytes) (+1,706). . (Created page with "'''Q: I have macros defined in a separate input file. Why does Verific analyzer complain about "undefined macros" in SystemVerilog mode but not in Verilog 2K mode?''' SystemV...")