Difference between revisions of "Defined macros become undefined - MFCU vs SFCU"

From Verific Design Automation FAQ
Jump to: navigation, search
(Created page with "'''Q: I have macros defined in a separate input file. Why does Verific analyzer complain about "undefined macros" in SystemVerilog mode but not in Verilog 2K mode?''' SystemV...")
 
Line 6: Line 6:
  
 
In SystemVerilog mode, in order for one file sees macros defined in another file, one needs to specify "multiple-file compilation unit" mode.
 
In SystemVerilog mode, in order for one file sees macros defined in another file, one needs to specify "multiple-file compilation unit" mode.
 
+
<nowiki>
   [hoa@awing6 181228]$ cat foo.v
+
   $ cat foo.v
 
   `define ZERO 0
 
   `define ZERO 0
   [hoa@awing6 181228]$ cat bar.v
+
 
 +
   $ cat bar.v
 
   module test (output oo);
 
   module test (output oo);
 
   assign oo = `ZERO;
 
   assign oo = `ZERO;
 
   endmodule
 
   endmodule
   [hoa@awing6 181228]$ verific-linux
+
    
 +
  $ verific-linux
 
   -- (c) Copyright 1999 - 2018 Verific Design Automation Inc. All rights reserved
 
   -- (c) Copyright 1999 - 2018 Verific Design Automation Inc. All rights reserved
 
   % analyze '''-verilog_2000''' foo.v bar.v
 
   % analyze '''-verilog_2000''' foo.v bar.v
Line 33: Line 35:
 
   -- Analyzing Verilog file 'bar.v' (VERI-1482)
 
   -- Analyzing Verilog file 'bar.v' (VERI-1482)
 
   % exit
 
   % exit
   [hoa@awing6 181228]$
+
 
 +
   $
 +
</nowiki>

Revision as of 10:33, 11 June 2021

Q: I have macros defined in a separate input file. Why does Verific analyzer complain about "undefined macros" in SystemVerilog mode but not in Verilog 2K mode?

SystemVerilog introduces "compilation unit." In general, constructs defined in one compilation unit is not visible in a different compilation unit.

The default mode in SystemVerilog is "single-file compilation unit." The default mode in Verilog 2K mode is "multiple-file compilation unit."

In SystemVerilog mode, in order for one file sees macros defined in another file, one needs to specify "multiple-file compilation unit" mode.

  $ cat foo.v
  `define ZERO 0

  $ cat bar.v
  module test (output oo);
  assign oo = `ZERO;
  endmodule
  
  $ verific-linux
  -- (c) Copyright 1999 - 2018 Verific Design Automation Inc. All rights reserved
  % analyze '''-verilog_2000''' foo.v bar.v
  -- Analyzing Verilog file 'foo.v' (VERI-1482)
  -- Analyzing Verilog file 'bar.v' (VERI-1482)
  % cleanup -all -static
  INFO: All parse-trees and netlists were deleted (CMD-2055)
  % analyze '''-sysv''' foo.v bar.v
  -- Analyzing Verilog file 'foo.v' (VERI-1482)
  -- Analyzing Verilog file 'bar.v' (VERI-1482)
  bar.v(2): WARNING: use of undefined macro 'ZERO' (VERI-1158)
  bar.v(2): ERROR: syntax error near ';' (VERI-1137)
  bar.v(3): ERROR: module 'test' ignored due to previous errors (VERI-1072)
  ERROR: analyze: failed (CMD-1014)
  % cleanup -all -static
  INFO: All parse-trees and netlists were deleted (CMD-2055)
  % analyze '''-sysv -mfcu''' foo.v bar.v
  -- Analyzing Verilog file 'foo.v' (VERI-1482)
  -- Analyzing Verilog file 'bar.v' (VERI-1482)
  % exit

  $