Difference between revisions of "Does Verific support XMR?"
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Without this product feature, support for XMR is full in analysis and static elaboration, and is very limited in RTL elaboration. | Without this product feature, support for XMR is full in analysis and static elaboration, and is very limited in RTL elaboration. | ||
| − | The main reason for limited support in RTL elaboration for XMR is that for Verilog, the order of elaboration of modules is nondeterministic. If module "foo" has not been elaborated, the elaborator will not be able to resolve "foo.bar". | + | The main reason for limited support in RTL elaboration for XMR is that for Verilog, the order of elaboration of modules is nondeterministic. If module "foo" has not been elaborated, the elaborator will not be able to resolve "foo.bar". As a collorary, without "hierarchy tree," "circular XMR," as in the testcase below (instance i1 refers to a signal in instance i2, and vice versa), is not supported: |
| + | |||
| + | module sub2(out); | ||
| + | output out; | ||
| + | assign top.i1.out = 0; | ||
| + | endmodule | ||
| + | module sub1(out); | ||
| + | output out; | ||
| + | assign top.i2.out = 0; | ||
| + | endmodule | ||
| + | module top(); | ||
| + | sub1 i1(); | ||
| + | sub2 i2(); | ||
| + | endmodule | ||
| + | |||
If the order of elaboration guarantees resolution of signals (e.g. module "foo" is elaborated before the module using "foo.bar" is), these runtime flags need to be enabled (set to 1) before design analysis: | If the order of elaboration guarantees resolution of signals (e.g. module "foo" is elaborated before the module using "foo.bar" is), these runtime flags need to be enabled (set to 1) before design analysis: | ||
Revision as of 11:49, 22 September 2016
Q: Does Verific support cross module references (XMR)?
Verific fully supports XMR with "hierarchy tree" feature. Please refer to Hierarchy Tree
Without this product feature, support for XMR is full in analysis and static elaboration, and is very limited in RTL elaboration.
The main reason for limited support in RTL elaboration for XMR is that for Verilog, the order of elaboration of modules is nondeterministic. If module "foo" has not been elaborated, the elaborator will not be able to resolve "foo.bar". As a collorary, without "hierarchy tree," "circular XMR," as in the testcase below (instance i1 refers to a signal in instance i2, and vice versa), is not supported:
module sub2(out);
output out;
assign top.i1.out = 0;
endmodule
module sub1(out);
output out;
assign top.i2.out = 0;
endmodule
module top();
sub1 i1();
sub2 i2();
endmodule
If the order of elaboration guarantees resolution of signals (e.g. module "foo" is elaborated before the module using "foo.bar" is), these runtime flags need to be enabled (set to 1) before design analysis:
veri_preserve_user_nets db_preserve_user_nets db_allow_external_nets
