Difference between revisions of "Does Verific support XMR?"
(Created page with "'''Q: Does Verific support cross module references (XMR)?''' Verific fully supports XMR with "hierarchy tree" feature. Please refer to http://www.verific.com/docs/index.php?t...") |
|||
| (5 intermediate revisions by the same user not shown) | |||
| Line 1: | Line 1: | ||
'''Q: Does Verific support cross module references (XMR)?''' | '''Q: Does Verific support cross module references (XMR)?''' | ||
| − | Verific fully supports XMR with "hierarchy tree" feature. Please refer to http://www.verific.com/docs/index.php?title=Hierarchy_Tree | + | Verific fully supports XMR with "hierarchy tree" feature. Please refer to [http://www.verific.com/docs/index.php?title=Hierarchy_Tree Hierarchy Tree] |
Without this product feature, support for XMR is full in analysis and static elaboration, and is very limited in RTL elaboration. | Without this product feature, support for XMR is full in analysis and static elaboration, and is very limited in RTL elaboration. | ||
| − | The main reason for limited support in RTL elaboration for XMR is that for Verilog, the order of elaboration of modules is nondeterministic. If module "foo" has not been elaborated, the elaborator will not be able to resolve "foo.bar". | + | The main reason for limited support in RTL elaboration for XMR is that for Verilog, the order of elaboration of modules is nondeterministic. If module "foo" has not been elaborated, the elaborator will not be able to resolve "foo.bar". As a collorary, without "hierarchy tree," "circular XMR," as in the testcase below (instance i1 refers to a signal in instance i2, and vice versa), is not supported: |
| − | + | module sub2(out); | |
| + | output out; | ||
| + | assign top.i1.out = 0; | ||
| + | endmodule | ||
| + | module sub1(out); | ||
| + | output out; | ||
| + | assign top.i2.out = 0; | ||
| + | endmodule | ||
| + | module top(); | ||
| + | sub1 i1(); | ||
| + | sub2 i2(); | ||
| + | endmodule | ||
| + | |||
| + | |||
| + | Note that for XMR support in RTL elaboration (even though limited), these runtime flags need to be enabled (set to 1) before design analysis: | ||
veri_preserve_user_nets | veri_preserve_user_nets | ||
db_preserve_user_nets | db_preserve_user_nets | ||
db_allow_external_nets | db_allow_external_nets | ||
| + | |||
| + | |||
| + | A side effect: defparam containing interface instance reference (SystemVerilog) is not supported in RTL elaboration. | ||
Revision as of 12:26, 11 September 2018
Q: Does Verific support cross module references (XMR)?
Verific fully supports XMR with "hierarchy tree" feature. Please refer to Hierarchy Tree
Without this product feature, support for XMR is full in analysis and static elaboration, and is very limited in RTL elaboration.
The main reason for limited support in RTL elaboration for XMR is that for Verilog, the order of elaboration of modules is nondeterministic. If module "foo" has not been elaborated, the elaborator will not be able to resolve "foo.bar". As a collorary, without "hierarchy tree," "circular XMR," as in the testcase below (instance i1 refers to a signal in instance i2, and vice versa), is not supported:
module sub2(out);
output out;
assign top.i1.out = 0;
endmodule
module sub1(out);
output out;
assign top.i2.out = 0;
endmodule
module top();
sub1 i1();
sub2 i2();
endmodule
Note that for XMR support in RTL elaboration (even though limited), these runtime flags need to be enabled (set to 1) before design analysis:
veri_preserve_user_nets db_preserve_user_nets db_allow_external_nets
A side effect: defparam containing interface instance reference (SystemVerilog) is not supported in RTL elaboration.
